forked from OSchip/llvm-project
AMDGPU: Fix folding immediate into readfirstlane through reg_sequence
The def instruction for the vreg may not match, because it may be folding through a reg_sequence. The assert was overly conservative and not necessary. It's not actually important if DefMI really defined the register, because the fold that will be done cares about the def of the value that will be folded. For some reason copies aren't making it through the reg_sequence, although they should. llvm-svn: 363876
This commit is contained in:
Matt Arsenault
parent
f8104f01e6
commit
4d000d2488
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@ -436,9 +436,11 @@ void SIFoldOperands::foldOperand(
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unsigned RegSeqDstReg = UseMI->getOperand(0).getReg();
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unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
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MachineRegisterInfo::use_iterator Next;
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for (MachineRegisterInfo::use_iterator
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RSUse = MRI->use_begin(RegSeqDstReg), RSE = MRI->use_end();
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RSUse != RSE; ++RSUse) {
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RSUse != RSE; RSUse = Next) {
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Next = std::next(RSUse);
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MachineInstr *RSUseMI = RSUse->getParent();
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if (RSUse->getSubReg() != RegSeqDstSubReg)
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@ -523,6 +525,9 @@ void SIFoldOperands::foldOperand(
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return;
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UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
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// FIXME: ChangeToImmediate should clear subreg
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UseMI->getOperand(1).setSubReg(0);
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UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
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UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
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return;
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@ -6079,7 +6079,6 @@ bool llvm::execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
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const MachineInstr &DefMI,
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const MachineInstr *UseMI) {
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assert(MRI.isSSA() && "Must be run on SSA");
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assert(DefMI.definesRegister(VReg) && "wrong def instruction");
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auto *TRI = MRI.getTargetRegisterInfo();
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auto *DefBB = DefMI.getParent();
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@ -279,12 +279,24 @@ define amdgpu_vs float @load_addr_no_fold(i32 addrspace(6)* inreg noalias %p0) #
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ret float %r2
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}
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; CHECK-LABEL: {{^}}vgpr_arg_src:
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; CHECK: v_readfirstlane_b32 s[[READLANE:[0-9]+]], v0
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; CHECK: s_mov_b32 s[[ZERO:[0-9]+]]
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; CHECK: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[READLANE]]:[[ZERO]]{{\]}}
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define amdgpu_vs float @vgpr_arg_src(<4 x i32> addrspace(6)* %arg) {
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main_body:
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%tmp9 = load <4 x i32>, <4 x i32> addrspace(6)* %arg
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%tmp10 = call nsz float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp9, i32 undef, i32 0, i32 0, i32 0) #1
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ret float %tmp10
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}
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; Function Attrs: nounwind readnone speculatable
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6
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; Function Attrs: nounwind readonly
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #7
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declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) #7
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!0 = !{}
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@ -248,3 +248,126 @@ body: |
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%1:sreg_32_xm0 = S_MOV_B32 12
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%2:sreg_32_xm0 = V_READLANE_B32 %0, %1, implicit $exec
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...
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# Constant for subreg0
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# GCN-LABEL: name: fold-imm-readfirstlane-regsequence0{{$}}
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# GCN: %0:vgpr_32 = COPY $vgpr0
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# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
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# GCN-NEXT: %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0, implicit $exec
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# GCN-NEXT: %4:sgpr_32 = S_MOV_B32 0
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---
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name: fold-imm-readfirstlane-regsequence0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
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%3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
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%4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
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...
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# Constant for subreg1
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# GCN-LABEL: name: fold-imm-readfirstlane-regsequence1{{$}}
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# GCN: %0:vgpr_32 = COPY $vgpr0
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# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, killed %0, %subreg.sub1
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# GCN-NEXT: %3:sgpr_32 = S_MOV_B32 0
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# GCN-NEXT: %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1, implicit $exec
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---
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name: fold-imm-readfirstlane-regsequence1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%2:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, killed %0:vgpr_32, %subreg.sub1
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%3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
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%4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
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...
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# Different constant regs for each subreg
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# GCN-LABEL: name: fold-imm-readfirstlane-regsequence2{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
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# GCN-NEXT: %3:sgpr_32 = S_MOV_B32 0
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# GCN-NEXT: %4:sgpr_32 = S_MOV_B32 1
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---
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name: fold-imm-readfirstlane-regsequence2
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
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%3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
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%4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
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...
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# Same constant reg for each subreg, so there are multiple constant uses
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# GCN-LABEL: name: fold-imm-readfirstlane-regsequence3{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
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# GCN-NEXT: %3:sgpr_32 = S_MOV_B32 0
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# GCN-NEXT: %4:sgpr_32 = S_MOV_B32 0
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---
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name: fold-imm-readfirstlane-regsequence3
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
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%3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
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%4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
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...
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# FIXME: This should fold
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# GCN-LABEL: name: fold-copy-readfirstlane-regsequence0{{$}}
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# GCN: %0:vgpr_32 = COPY $sgpr10
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# GCN-NEXT: %1:vgpr_32 = COPY $sgpr11
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# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
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# GCN-NEXT: %3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0, implicit $exec
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# GCN-NEXT: %4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1, implicit $exec
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---
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name: fold-copy-readfirstlane-regsequence0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr10, $sgpr11
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%0:vgpr_32 = COPY $sgpr10
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%1:vgpr_32 = COPY $sgpr11
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%2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
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%3:sgpr_32 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
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%4:sgpr_32 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
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...
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# GCN-LABEL: name: fold-copy-readfirstlane-regsequence1{{$}}
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# GCN: %0:sreg_32_xm0 = COPY $sgpr10
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# GCN-NEXT: %1:sreg_32_xm0 = COPY $sgpr11
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# GCN-NEXT: %2:vgpr_32 = COPY %0
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# GCN-NEXT: %3:vgpr_32 = COPY %1
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# GCN-NEXT: %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, killed %3, %subreg.sub1
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# GCN-NEXT: %5:sgpr_32 = V_READFIRSTLANE_B32 %4.sub0, implicit $exec
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# GCN-NEXT: %6:sgpr_32 = V_READFIRSTLANE_B32 %4.sub1, implicit $exec
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---
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name: fold-copy-readfirstlane-regsequence1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr10, $sgpr11
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%0:sreg_32_xm0 = COPY $sgpr10
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%1:sreg_32_xm0 = COPY $sgpr11
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%2:vgpr_32 = COPY %0
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%3:vgpr_32 = COPY %1
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%4:vreg_64 = REG_SEQUENCE %2:vgpr_32, %subreg.sub0, killed %3:vgpr_32, %subreg.sub1
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%5:sgpr_32 = V_READFIRSTLANE_B32 %4.sub0:vreg_64, implicit $exec
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%6:sgpr_32 = V_READFIRSTLANE_B32 %4.sub1:vreg_64, implicit $exec
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...
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