forked from OSchip/llvm-project
parent
4c7b604091
commit
4cfcb544bf
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@ -654,8 +654,12 @@ void DAGISelEmitter::ParseAndResolveInstructions() {
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I->error("Could not infer all types in pattern!");
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}
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// SetDestinations - Keep track of all the virtual registers that are 'set'
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// in the instruction, including what reg class they are.
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std::map<std::string, Record*> SetDestinations;
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// Verify that the top-level forms in the instruction are of void type, and
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// figure out how many of the instruction operands are destinations.
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// fill in the SetDestinations map.
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for (unsigned j = 0, e = I->getNumTrees(); j != e; ++j) {
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TreePatternNode *Pat = I->getTree(j);
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if (Pat->getType() != MVT::isVoid) {
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@ -677,16 +681,29 @@ void DAGISelEmitter::ParseAndResolveInstructions() {
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TreePatternNode *Dest = Pat->getChild(i);
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if (!Dest->isLeaf())
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I->error("set destination should be a virtual register!");
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DefInit *Val = dynamic_cast<DefInit*>(Dest->getLeafValue());
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if (!Val)
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I->error("set destination should be a virtual register!");
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if (!Val->getDef()->isSubClassOf("RegisterClass"))
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I->error("set destination should be a virtual register!");
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if (Dest->getName().empty())
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I->error("set destination must have a name!");
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if (SetDestinations.count(Dest->getName()))
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I->error("cannot set '" + Dest->getName() +"' multiple times");
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SetDestinations[Dest->getName()] = Val->getDef();
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}
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}
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}
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// Now that we have operands that are sets, inspect the operands list for
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// the instruction. This determines the order that operands are added to
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// the machine instruction the node corresponds to.
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assert(SetDestinations.size() == 1 &&
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"This code only handles a single set right now!");
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DEBUG(I->dump());
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Instructions.push_back(I);
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