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[NFC][MC] MCRegister API typing. 

Mostly LiveIntervals, with their effects (users).

Differential Revision: https://reviews.llvm.org/D89018
This commit is contained in:
Mircea Trofin 2020-10-07 16:11:50 -07:00
parent 19119dda16
commit 4cfc4025cc
12 changed files with 39 additions and 33 deletions
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2
llvm/include/llvm/CodeGen/LiveIntervals.h
View File

@ -431,7 +431,7 @@ class VirtRegMap;
/// Remove value numbers and related live segments starting at position
/// \p Pos that are part of any liverange of physical register \p Reg or one
/// of its subregisters.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos);
/// Remove value number and related live segments of \p LI and its subranges
/// that start at position \p Pos.

4
llvm/include/llvm/CodeGen/VirtRegMap.h
View File

@ -98,9 +98,9 @@ class TargetInstrInfo;
/// returns the physical register mapped to the specified
/// virtual register
Register getPhys(Register virtReg) const {
MCRegister getPhys(Register virtReg) const {
assert(virtReg.isVirtual());
return Virt2PhysMap[virtReg.id()];
return MCRegister::from(Virt2PhysMap[virtReg.id()]);
}
/// creates a mapping for the specified virtual register to

2
llvm/lib/CodeGen/InlineSpiller.cpp
View File

@ -881,7 +881,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
// FoldMI does not define this physreg. Remove the LI segment.
assert(MO->isDead() && "Cannot fold physreg def");
SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
LIS.removePhysRegDefAt(Reg, Idx);
LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
}
int FI;

5
llvm/lib/CodeGen/LiveIntervals.cpp
View File

@ -1037,7 +1037,8 @@ public:
// For physregs, only update the regunits that actually have a
// precomputed live range.
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
++Units)
if (LiveRange *LR = getRegUnitLI(*Units))
updateRange(*LR, *Units, LaneBitmask::getNone());
}
@ -1683,7 +1684,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
}
}
void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
void LiveIntervals::removePhysRegDefAt(MCRegister Reg, SlotIndex Pos) {
for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
if (LiveRange *LR = getCachedRegUnit(*Unit))
if (VNInfo *VNI = LR->getVNInfoAt(Pos))

2
llvm/lib/CodeGen/LiveRangeEdit.cpp
View File

@ -316,7 +316,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
ReadsPhysRegs = true;
else if (MOI->isDef())
LIS.removePhysRegDefAt(Reg, Idx);
LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
continue;
}
LiveInterval &LI = LIS.getInterval(Reg);

2
llvm/lib/CodeGen/RegAllocGreedy.cpp
View File

@ -2866,7 +2866,7 @@ void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
// Get the current assignment.
Register OtherPhysReg = Register::isPhysicalRegister(OtherReg)
? OtherReg
: VRM->getPhys(OtherReg);
: Register(VRM->getPhys(OtherReg));
// Push the collected information.
Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
OtherPhysReg));

25
llvm/lib/CodeGen/RegisterCoalescer.cpp
View File

@ -173,7 +173,7 @@ namespace {
SmallVector<MachineInstr*, 8> DeadDefs;
/// Virtual registers to be considered for register class inflation.
SmallVector<unsigned, 8> InflateRegs;
SmallVector<Register, 8> InflateRegs;
/// The collection of live intervals which should have been updated
/// immediately after rematerialiation but delayed until
@ -285,7 +285,7 @@ namespace {
/// number if it is not zero. If DstReg is a physical register and the
/// existing subregister number of the def / use being updated is not zero,
/// make sure to set it to the correct physical subregister.
void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
/// If the given machine operand reads only undefined lanes add an undef
/// flag.
@ -1246,9 +1246,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
MachineInstr *CopyMI,
bool &IsDefCopy) {
IsDefCopy = false;
unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
if (Register::isPhysicalRegister(SrcReg))
return false;
@ -1700,7 +1700,7 @@ void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
}
}
void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, unsigned DstReg,
void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
unsigned SubIdx) {
bool DstIsPhys = Register::isPhysicalRegister(DstReg);
LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
@ -1942,7 +1942,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
if (Changed) {
deleteInstr(CopyMI);
if (Shrink) {
unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
LiveInterval &DstLI = LIS->getInterval(DstReg);
shrinkToUses(&DstLI);
LLVM_DEBUG(dbgs() << "\t\tshrunk: " << DstLI << '\n');
@ -2034,8 +2034,8 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
}
bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
unsigned DstReg = CP.getDstReg();
unsigned SrcReg = CP.getSrcReg();
Register DstReg = CP.getDstReg();
Register SrcReg = CP.getSrcReg();
assert(CP.isPhys() && "Must be a physreg copy");
assert(MRI->isReserved(DstReg) && "Not a reserved register");
LiveInterval &RHS = LIS->getInterval(SrcReg);
@ -2132,7 +2132,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "
<< printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
LIS->removePhysRegDefAt(DstReg.asMCReg(), CopyRegIdx);
// Create a new dead def at the new def location.
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
LiveRange &LR = LIS->getRegUnit(*UI);
@ -2393,14 +2393,15 @@ class JoinVals {
bool isPrunedValue(unsigned ValNo, JoinVals &Other);
public:
JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask,
SmallVectorImpl<VNInfo *> &newVNInfo, const CoalescerPair &cp,
LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
bool TrackSubRegLiveness)
: LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {}
TRI(TRI), Assignments(LR.getNumValNums(), -1),
Vals(LR.getNumValNums()) {}
/// Analyze defs in LR and compute a value mapping in NewVNInfo.
/// Returns false if any conflicts were impossible to resolve.

10
llvm/lib/CodeGen/RegisterCoalescer.h
View File

@ -14,6 +14,8 @@
#ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
#define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
#include "llvm/CodeGen/Register.h"
namespace llvm {
class MachineInstr;
@ -28,10 +30,10 @@ class TargetRegisterInfo;
/// The register that will be left after coalescing. It can be a
/// virtual or physical register.
unsigned DstReg = 0;
Register DstReg;
/// The virtual register that will be coalesced into dstReg.
unsigned SrcReg = 0;
Register SrcReg;
/// The sub-register index of the old DstReg in the new coalesced register.
unsigned DstIdx = 0;
@ -92,10 +94,10 @@ class TargetRegisterInfo;
/// Return the register (virtual or physical) that will remain
/// after coalescing.
unsigned getDstReg() const { return DstReg; }
Register getDstReg() const { return DstReg; }
/// Return the virtual register that will be coalesced away.
unsigned getSrcReg() const { return SrcReg; }
Register getSrcReg() const { return SrcReg; }
/// Return the subregister index that DstReg will be coalesced into, or 0.
unsigned getDstIdx() const { return DstIdx; }

2
llvm/lib/CodeGen/VirtRegMap.cpp
View File

@ -104,7 +104,7 @@ bool VirtRegMap::hasPreferredPhys(Register VirtReg) {
return false;
if (Hint.isVirtual())
Hint = getPhys(Hint);
return getPhys(VirtReg) == Hint;
return Register(getPhys(VirtReg)) == Hint;
}
bool VirtRegMap::hasKnownPreference(Register VirtReg) {

5
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -1196,7 +1196,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
Register Reg = MI.getOperand(I).getReg();
Register PhysReg = Register::isVirtualRegister(Reg)
? (VRM ? VRM->getPhys(Reg) : Register())
? (VRM ? Register(VRM->getPhys(Reg)) : Register())
: Reg;
if (!PhysReg ||
!(SystemZ::FP32BitRegClass.contains(PhysReg) ||
@ -1242,7 +1242,8 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
else {
Register DstReg = MI.getOperand(0).getReg();
Register DstPhys =
(Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
(Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
: DstReg);
Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
: ((OpNum == 1 && MI.isCommutable())
? MI.getOperand(2).getReg()

5
llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -109,8 +109,9 @@ bool SystemZRegisterInfo::getRegAllocationHints(
auto tryAddHint = [&](const MachineOperand *MO) -> void {
Register Reg = MO->getReg();
Register PhysReg =
Register::isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
Register PhysReg = Register::isPhysicalRegister(Reg)
? Reg
: Register(VRM->getPhys(Reg));
if (PhysReg) {
if (MO->getSubReg())
PhysReg = getSubReg(PhysReg, MO->getSubReg());

2
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
View File

@ -595,7 +595,7 @@ static MachineInstr *rematerializeCheapDef(
if (IsDead) {
LLVM_DEBUG(dbgs() << " - Deleting original\n");
SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
LIS.removePhysRegDefAt(MCRegister::from(WebAssembly::ARGUMENTS), Idx);
LIS.removeInterval(Reg);
LIS.RemoveMachineInstrFromMaps(Def);
Def.eraseFromParent();