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Encode predict = 1 by default, because the Sparc assembler does this. 

llvm-svn: 7181
This commit is contained in:
Misha Brukman 2003-07-15 21:26:49 +00:00
parent c7efa119ac
commit 4cf012d845
1 changed files with 4 additions and 4 deletions
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8
llvm/lib/Target/Sparc/SparcV9_F2.td
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@ -38,21 +38,21 @@ class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
bits<2> cc; bits<2> cc;
bits<19> disp; bits<19> disp;
bit predict; bit predict = 1;
bit annul; bit annul;
set Name = name; set Name = name;
set Inst{29} = annul; set Inst{29} = annul;
set Inst{28-25} = cond; set Inst{28-25} = cond;
set Inst{21-20} = cc; set Inst{21-20} = cc;
set Inst{19} = predict; set Inst{19} = 1; // predict;
set Inst{18-0} = disp; set Inst{18-0} = disp;
} }
class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
bits<5> rs1; bits<5> rs1;
bits<16> disp; bits<16> disp;
bit predict; bit predict = 1;
bit annul; bit annul;
set Name = name; set Name = name;
@ -60,7 +60,7 @@ class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
set Inst{28} = 0; set Inst{28} = 0;
set Inst{27-25} = rcond; set Inst{27-25} = rcond;
set Inst{21-20} = disp{15-14}; set Inst{21-20} = disp{15-14};
set Inst{19} = predict; set Inst{19} = 1; // predict;
set Inst{18-14} = rs1; set Inst{18-14} = rs1;
set Inst{13-0 } = disp{13-0}; set Inst{13-0 } = disp{13-0};
} }