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[ARM] MVE integer abs 

Similar to floating point abs, we also have instructions for integers.

Differential Revision: https://reviews.llvm.org/D64027

llvm-svn: 366005
This commit is contained in:
David Green 2019-07-13 14:58:32 +00:00
parent 701bf714db
commit 4ce648b5e8
3 changed files with 48 additions and 0 deletions
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1
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -254,6 +254,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
setOperationAction(ISD::SMAX, VT, Legal);
setOperationAction(ISD::UMIN, VT, Legal);
setOperationAction(ISD::UMAX, VT, Legal);
setOperationAction(ISD::ABS, VT, Legal);
// No native support for these.
setOperationAction(ISD::UDIV, VT, Expand);

9
llvm/lib/Target/ARM/ARMInstrMVE.td
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@ -2189,6 +2189,15 @@ def MVE_VABSs8 : MVE_VABSNEG_int<"vabs", "s8", 0b00, 0b0>;
def MVE_VABSs16 : MVE_VABSNEG_int<"vabs", "s16", 0b01, 0b0>;
def MVE_VABSs32 : MVE_VABSNEG_int<"vabs", "s32", 0b10, 0b0>;
let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 (abs (v16i8 MQPR:$v))),
(v16i8 (MVE_VABSs8 $v))>;
def : Pat<(v8i16 (abs (v8i16 MQPR:$v))),
(v8i16 (MVE_VABSs16 $v))>;
def : Pat<(v4i32 (abs (v4i32 MQPR:$v))),
(v4i32 (MVE_VABSs32 $v))>;
}
def MVE_VNEGs8 : MVE_VABSNEG_int<"vneg", "s8", 0b00, 0b1>;
def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>;
def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>;

38
llvm/test/CodeGen/Thumb2/mve-abs.ll Normal file
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@ -0,0 +1,38 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) {
; CHECK-LABEL: abs_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <16 x i8> %s1, zeroinitializer
%1 = sub nsw <16 x i8> zeroinitializer, %s1
%2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %s1
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @abs_v8i16(<8 x i16> %s1) {
; CHECK-LABEL: abs_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <8 x i16> %s1, zeroinitializer
%1 = sub nsw <8 x i16> zeroinitializer, %s1
%2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %s1
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @abs_v4i32(<4 x i32> %s1) {
; CHECK-LABEL: abs_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <4 x i32> %s1, zeroinitializer
%1 = sub nsw <4 x i32> zeroinitializer, %s1
%2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1
ret <4 x i32> %2
}