forked from OSchip/llvm-project
[NFC][PowerPC] Add the inheritable and additional features to make the processor definition more clear
The old processor design assume that, all the old processor's feature must be inherited into future processor. That is not true as instruction fusion or some implementation defined features are not inheritable. What this patch did: * Rename the old "specific features" to "additional features" that keep the new added inheritable features. * Use the "specific features" to keep those features only for specific processor. * Add the "inheritable features" to keep all the features that inherited from early processor. Differential Revision: https://reviews.llvm.org/D70768
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QingShan Zhang
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f1e3988aa6
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4cde2d6b8d
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@ -211,52 +211,94 @@ def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
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// came before them, the idea is to make implementations of new processors
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// less error prone and easier to read.
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// Namely:
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// list<SubtargetFeature> Power8FeatureList = ...
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// list<SubtargetFeature> FutureProcessorSpecificFeatureList =
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// [ features that Power8 does not support ]
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// list<SubtargetFeature> FutureProcessorFeatureList =
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// !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
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// list<SubtargetFeature> P8InheritableFeatures = ...
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// list<SubtargetFeature> FutureProcessorAddtionalFeatures =
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// [ features that Power8 does not support but inheritable ]
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// list<SubtargetFeature> FutureProcessorSpecificFeatures =
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// [ features that Power8 does not support and not inheritable ]
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// list<SubtargetFeature> FutureProcessorInheritableFeatures =
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// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
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// list<SubtargetFeature> FutureProcessorFeatures =
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// !listconcat(FutureProcessorInheritableFeatures,
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// FutureProcessorSpecificFeatures)
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// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
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// well as providing a single point of definition if the feature set will be
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// used elsewhere.
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def ProcessorFeatures {
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list<SubtargetFeature> Power7FeatureList =
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[DirectivePwr7, FeatureAltivec, FeatureVSX,
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FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
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FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
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FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureBPERMD, FeatureExtDiv,
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FeatureMFTB, DeprecatedDST, FeatureTwoConstNR];
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list<SubtargetFeature> Power8SpecificFeatures =
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[DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
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FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
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list<SubtargetFeature> Power8FeatureList =
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!listconcat(Power7FeatureList, Power8SpecificFeatures);
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list<SubtargetFeature> Power9SpecificFeatures =
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[DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
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// Power7
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list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
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FeatureAltivec,
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FeatureVSX,
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FeatureMFOCRF,
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FeatureFCPSGN,
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FeatureFSqrt,
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FeatureFRE,
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FeatureFRES,
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FeatureFRSQRTE,
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FeatureFRSQRTES,
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FeatureRecipPrec,
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FeatureSTFIWX,
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FeatureLFIWAX,
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FeatureFPRND,
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FeatureFPCVT,
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FeatureISEL,
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FeaturePOPCNTD,
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FeatureCMPB,
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FeatureLDBRX,
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Feature64Bit,
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/* Feature64BitRegs, */
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FeatureBPERMD,
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FeatureExtDiv,
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FeatureMFTB,
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DeprecatedDST,
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FeatureTwoConstNR];
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list<SubtargetFeature> P7SpecificFeatures = [];
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list<SubtargetFeature> P7Features =
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!listconcat(P7InheritableFeatures, P7SpecificFeatures);
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// Power8
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list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8,
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FeatureP8Altivec,
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FeatureP8Vector,
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FeatureP8Crypto,
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FeatureHTM,
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FeatureDirectMove,
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FeatureICBT,
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FeaturePartwordAtomic];
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list<SubtargetFeature> P8SpecificFeatures = [];
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list<SubtargetFeature> P8InheritableFeatures =
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!listconcat(P7InheritableFeatures, P8AdditionalFeatures);
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list<SubtargetFeature> P8Features =
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!listconcat(P8InheritableFeatures, P8SpecificFeatures);
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// Power9
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list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9,
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FeatureP9Altivec,
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FeatureP9Vector,
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FeatureISA3_0];
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// Some features are unique to Power9 and there is no reason to assume
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// they will be part of any future CPUs. One example is the narrower
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// dispatch for vector operations than scalar ones. For the time being,
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// this list also includes scheduling-related features since we do not have
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// enough info to create custom scheduling strategies for future CPUs.
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list<SubtargetFeature> Power9OnlyFeatures =
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[FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
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list<SubtargetFeature> Power9FeatureList =
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!listconcat(Power8FeatureList, Power9SpecificFeatures);
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list<SubtargetFeature> Power9ImplList =
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!listconcat(Power9FeatureList, Power9OnlyFeatures);
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list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
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FeaturePPCPreRASched,
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FeaturePPCPostRASched];
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list<SubtargetFeature> P9InheritableFeatures =
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!listconcat(P8InheritableFeatures, P9AdditionalFeatures);
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list<SubtargetFeature> P9Features =
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!listconcat(P9InheritableFeatures, P9SpecificFeatures);
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// Future
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// For future CPU we assume that all of the existing features from Power 9
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// still exist with the exception of those we know are Power 9 specific.
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list<SubtargetFeature> FutureSpecificFeatures =
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[];
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list<SubtargetFeature> FutureFeatureList =
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!listconcat(Power9FeatureList, FutureSpecificFeatures);
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list<SubtargetFeature> FutureAdditionalFeatures = [];
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list<SubtargetFeature> FutureSpecificFeatures = [];
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list<SubtargetFeature> FutureInheritableFeatures =
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!listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
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list<SubtargetFeature> FutureFeatures =
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!listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
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}
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// Note: Future features to add when support is extended to more
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@ -456,12 +498,12 @@ def : ProcessorModel<"pwr6x", G5Model,
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FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
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FeatureFPRND, Feature64Bit,
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FeatureMFTB, DeprecatedDST]>;
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def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
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def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
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def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9ImplList>;
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def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
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def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
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def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
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// No scheduler model for future CPU.
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def : ProcessorModel<"future", NoSchedModel,
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ProcessorFeatures.FutureFeatureList>;
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ProcessorFeatures.FutureFeatures>;
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def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
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FeatureMFTB]>;
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def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
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@ -472,7 +514,7 @@ def : ProcessorModel<"ppc64", G5Model,
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FeatureFRSQRTE, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureMFTB]>;
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def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
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def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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