[X86] Automatically generate shift tests. NFC

llvm-svn: 369475

llvm/test/CodeGen/X86/shift-avx2-crash.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s  -mcpu=core-avx2 > /dev/null
 ; This test crashed on variable shift creation on AVX2
 
@@ -29,7 +30,7 @@ if_then18.i:
   br label %__fast_idiv___UM_vyuunu.exit
 
 
-__fast_idiv___UM_vyuunu.exit:                   
+__fast_idiv___UM_vyuunu.exit:
   %calltmp_to_float = uitofp <8 x i32> %bitop22_to_uint32.i to <8 x float>
   %ptrcast = bitcast float* %RET to <8 x float>*
   store <8 x float> %calltmp_to_float, <8 x float>* %ptrcast, align 4

llvm/test/CodeGen/X86/shift-coalesce.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \
 ; RUN:   grep "shld.*cl"
 ; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \

llvm/test/CodeGen/X86/shift-combine-crash.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null
 
 ; Verify that DAGCombiner doesn't crash with an assertion failure in the

llvm/test/CodeGen/X86/shift-one.ll

@@ -1,8 +1,14 @@
-; RUN: llc < %s -mtriple=i686-- | not grep leal
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 @x = external global i32                ; <i32*> [#uses=1]
 
 define i32 @test() {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl x, %eax
+; CHECK-NEXT:    addl %eax, %eax
+; CHECK-NEXT:    retl
         %tmp.0 = load i32, i32* @x           ; <i32> [#uses=1]
         %tmp.1 = shl i32 %tmp.0, 1              ; <i32> [#uses=1]
         ret i32 %tmp.1

llvm/test/CodeGen/X86/shift-parts.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
 ; PR4736
 
@@ -5,9 +6,25 @@
 
 @g_144 = external global %0, align 8              ; <%0*> [#uses=1]
 
-; CHECK: shrdq
-
 define i32 @int87(i32 %uint64p_8, i1 %cond) nounwind {
+; CHECK-LABEL: int87:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq g_144+{{.*}}(%rip), %rax
+; CHECK-NEXT:    movq g_144+{{.*}}(%rip), %rdx
+; CHECK-NEXT:    movzbl %sil, %ecx
+; CHECK-NEXT:    shll $6, %ecx
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %for.cond
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movq %rdx, %rsi
+; CHECK-NEXT:    shrdq %cl, %rax, %rsi
+; CHECK-NEXT:    testb $64, %cl
+; CHECK-NEXT:    cmovneq %rax, %rsi
+; CHECK-NEXT:    orl $0, %esi
+; CHECK-NEXT:    je .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %if.then
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    retq
 entry:
   %srcval4 = load i320, i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
   br label %for.cond