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[mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test. 

This update is a preparation for the addition of Mips64 MSA tests.

No functional changes.

llvm-svn: 200399
This commit is contained in:
Matheus Almeida 2014-01-29 14:32:03 +00:00
parent 74070327b2
commit 4cb577c614
1 changed files with 29 additions and 27 deletions
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56
llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
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@ -1,8 +1,10 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format and
; convert scalars to vectors.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@ -17,11 +19,11 @@ entry:
declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
; CHECK: llvm_mips_fill_b_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.b [[R2]],
; CHECK: .size llvm_mips_fill_b_test
; MIPS-ANY: llvm_mips_fill_b_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.b [[R2]],
; MIPS-ANY: .size llvm_mips_fill_b_test
;
@llvm_mips_fill_h_ARG1 = global i32 23, align 16
@llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
@ -36,11 +38,11 @@ entry:
declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
; CHECK: llvm_mips_fill_h_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.h [[R2]],
; CHECK: .size llvm_mips_fill_h_test
; MIPS-ANY: llvm_mips_fill_h_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.h [[R2]],
; MIPS-ANY: .size llvm_mips_fill_h_test
;
@llvm_mips_fill_w_ARG1 = global i32 23, align 16
@llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@ -55,11 +57,11 @@ entry:
declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
; CHECK: llvm_mips_fill_w_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.w [[R2]],
; CHECK: .size llvm_mips_fill_w_test
; MIPS-ANY: llvm_mips_fill_w_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]],
; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
; MIPS-ANY-DAG: st.w [[R2]],
; MIPS-ANY: .size llvm_mips_fill_w_test
;
@llvm_mips_fill_d_ARG1 = global i64 23, align 16
@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
@ -74,14 +76,14 @@ entry:
declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
; CHECK: llvm_mips_fill_d_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0
; CHECK-DAG: insert.w [[R3]][0], [[R1]]
; CHECK-DAG: insert.w [[R3]][1], [[R2]]
; CHECK-DAG: insert.w [[R3]][2], [[R1]]
; CHECK-DAG: insert.w [[R3]][3], [[R2]]
; CHECK-DAG: st.w [[R3]],
; CHECK: .size llvm_mips_fill_d_test
; MIPS-ANY: llvm_mips_fill_d_test:
; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(
; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(
; MIPS32-DAG: ldi.b [[R3:\$w[0-9]+]], 0
; MIPS32-DAG: insert.w [[R3]][0], [[R1]]
; MIPS32-DAG: insert.w [[R3]][1], [[R2]]
; MIPS32-DAG: insert.w [[R3]][2], [[R1]]
; MIPS32-DAG: insert.w [[R3]][3], [[R2]]
; MIPS32-DAG: st.w [[R3]],
; MIPS-ANY: .size llvm_mips_fill_d_test
;