forked from OSchip/llvm-project
parent
0d5dc010fa
commit
4c8a2120aa
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@ -44,7 +44,7 @@ ifdef ENABLE_SPARC_JIT
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JITLIBS += sparcv9
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ARCHLIBS += sched sparcv9livevar instrument.a profpaths \
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bcwriter transforms.a ipo.a ipa.a datastructure.a \
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sparcv9regalloc sparcv9select
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sparcv9regalloc
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endif
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USEDLIBS = lli-interpreter $(JITLIBS) $(ARCHLIBS) scalaropts analysis.a \
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