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[MCA] Add support for BeginGroup/EndGroup. 

llvm-svn: 349354
This commit is contained in:
Andrea Di Biagio 2018-12-17 14:27:33 +00:00
parent 6c933a2bed
commit 4c73711069
4 changed files with 22 additions and 10 deletions
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2
llvm/include/llvm/MCA/Instruction.h
View File

@ -334,6 +334,8 @@ struct InstrDesc {
bool MayLoad;
bool MayStore;
bool HasSideEffects;
bool BeginGroup;
bool EndGroup;
// A zero latency instruction doesn't consume any scheduler resources.
bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }

2
llvm/lib/MCA/InstrBuilder.cpp
View File

@ -536,6 +536,8 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
ID->MayLoad = MCDesc.mayLoad();
ID->MayStore = MCDesc.mayStore();
ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
ID->BeginGroup = SCDesc.BeginGroup;
ID->EndGroup = SCDesc.EndGroup;
initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
computeMaxLatency(*ID, MCDesc, SCDesc, STI);

8
llvm/lib/MCA/Stages/DispatchStage.cpp
View File

@ -99,6 +99,10 @@ Error DispatchStage::dispatch(InstRef IR) {
AvailableEntries -= NumMicroOps;
}
// Check if this instructions ends the dispatch group.
if (Desc.EndGroup)
AvailableEntries = 0;
// Check if this is an optimizable reg-reg move.
bool IsEliminated = false;
if (IS.isOptimizableMove()) {
@ -164,6 +168,10 @@ bool DispatchStage::isAvailable(const InstRef &IR) const {
unsigned Required = std::min(Desc.NumMicroOps, DispatchWidth);
if (Required > AvailableEntries)
return false;
if (Desc.BeginGroup && AvailableEntries != DispatchWidth)
return false;
// The dispatch logic doesn't internally buffer instructions. It only accepts
// instructions that can be successfully moved to the next stage during this
// same cycle.

20
llvm/test/tools/llvm-mca/SystemZ/stm-lm.s
View File

@ -6,7 +6,7 @@ lmg %r6, %r15, 48(%r15)
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
# CHECK-NEXT: Total Cycles: 1003
# CHECK-NEXT: Total Cycles: 1004
# CHECK-NEXT: Total uOps: 600
# CHECK: Dispatch Width: 6
@ -51,15 +51,15 @@ lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: - - - - 0.10 4.90 - - - - - - - lmg %r6, %r15, 48(%r15)
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 012
# CHECK-NEXT: 0123456789 0123
# CHECK-NEXT: Index 0123456789 0123456789
# CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [0,1] DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [1,0] .D=========eER . . . . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [1,1] .D=========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [2,0] . D==================eER . . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [2,1] . D==================eeeeeeeeeeER lmg %r6, %r15, 48(%r15)
# CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [0,1] .DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [1,0] . D=========eER. . . . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [1,1] . D========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [2,0] . D=================eER. . . stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [2,1] . D================eeeeeeeeeeER lmg %r6, %r15, 48(%r15)
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@ -68,5 +68,5 @@ lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 10.0 0.3 0.0 stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: 1. 3 10.0 0.3 0.0 lmg %r6, %r15, 48(%r15)
# CHECK-NEXT: 0. 3 9.7 0.3 0.0 stmg %r6, %r15, 48(%r15)
# CHECK-NEXT: 1. 3 9.0 0.3 0.0 lmg %r6, %r15, 48(%r15)