forked from OSchip/llvm-project
Inserting a base test for X86 performance nops
Change-Id: I69da08b617d7fae8024c5aee04720eb465f39b81 llvm-svn: 318041
This commit is contained in:
Omer Paparo Bivas
parent
769b21eaf2
commit
4c679e1435
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@ -0,0 +1,288 @@
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# RUN: llc -mcpu=haswell -filetype=obj -start-before stack-protector -O2 %s -o - | llvm-objdump -d - | FileCheck %s
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# Test 1:
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#
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# Source C code:
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# volatile int y;
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# volatile int x;
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#
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# int switchCase(int z, int w) {
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# int result = 0;
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# while (x > 0 && y < 0) {
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# switch(z) {
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# case 0:
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# result+=result*5;break;
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# case 1:
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# result--; break;
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# case 2:
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# result *= result; break;
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# case 3:
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# result <<= 7; break;
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# case 4:
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# result >>= 7; break;
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# case 5:
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# result = result * 16 | ~result; break;
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# }
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# }
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# return result;
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# }
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#
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# CHECK: 49: eb 4a jmp 74 <switchCase+0x95>
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# CHECK: 57: eb 3c jmp 60 <switchCase+0x95>
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# CHECK: 65: eb 2e jmp 46 <switchCase+0x95>
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# CHECK: 73: eb 20 jmp 32 <switchCase+0x95>
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# CHECK: 81: eb 12 jmp 18 <switchCase+0x95>
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# CHECK: 93: 7f 8b jg -117 <switchCase+0x20>
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# Test 2:
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#
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# Source C code:
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#
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# int ifElse(int z) {
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# int w = 0;
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# while(1) {
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# if(x < 0)
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# w++;
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# else if(y > 0)
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# w--;
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# else if((x & y) == 3)
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# w*=2;
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# else if ((x | y) == 18)
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# w += 2;
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# else if ((y ^ x) == 154)
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# w -= 3;
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# else if(((y ^ x) & 1) != 0)
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# break;
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# }
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# return w;
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# }
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#
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# CHECK: 129: eb 13 jmp 19 <ifElse+0x7E>
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# CHECK: 12e: eb a0 jmp -96 <ifElse+0x10>
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# CHECK: 132: eb 9c jmp -100 <ifElse+0x10>
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# CHECK: 137: eb 97 jmp -105 <ifElse+0x10>
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# CHECK: 13c: eb 92 jmp -110 <ifElse+0x10>
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--- |
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; ModuleID = 'D:\iusers\opaparo\dev_test\branch_instruction_and_target_split_perf_nops.ll'
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source_filename = "D:\5C\5Ciusers\5C\5Copaparo\5C\5Cdev_test\5C\5Cbranch_instruction_and_target_split_perf_nops.c"
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target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-windows-msvc19.0.24210"
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@x = common global i32 0, align 4
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@y = common global i32 0, align 4
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; Function Attrs: norecurse nounwind uwtable
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define i32 @switchCase(i32 %z, i32 %w) local_unnamed_addr #0 {
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entry:
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%0 = load volatile i32, i32* @x, align 4, !tbaa !3
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%cmp19 = icmp sgt i32 %0, 0
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br i1 %cmp19, label %land.rhs.preheader, label %while.end
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land.rhs.preheader: ; preds = %entry
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br label %land.rhs
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land.rhs: ; preds = %sw.epilog, %land.rhs.preheader
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%result.020 = phi i32 [ %result.1, %sw.epilog ], [ 0, %land.rhs.preheader ]
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%1 = load volatile i32, i32* @y, align 4, !tbaa !3
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%cmp1 = icmp slt i32 %1, 0
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br i1 %cmp1, label %while.body, label %while.end
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while.body: ; preds = %land.rhs
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switch i32 %z, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb2
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i32 2, label %sw.bb3
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i32 3, label %sw.bb5
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i32 4, label %sw.bb6
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i32 5, label %sw.bb7
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]
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sw.bb: ; preds = %while.body
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%add = mul nsw i32 %result.020, 6
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br label %sw.epilog
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sw.bb2: ; preds = %while.body
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%dec = add nsw i32 %result.020, -1
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br label %sw.epilog
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sw.bb3: ; preds = %while.body
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%mul4 = mul nsw i32 %result.020, %result.020
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br label %sw.epilog
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sw.bb5: ; preds = %while.body
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%shl = shl i32 %result.020, 7
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br label %sw.epilog
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sw.bb6: ; preds = %while.body
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%shr = ashr i32 %result.020, 7
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br label %sw.epilog
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sw.bb7: ; preds = %while.body
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%mul8 = shl nsw i32 %result.020, 4
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%neg = xor i32 %result.020, -1
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%or = or i32 %mul8, %neg
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb7, %sw.bb6, %sw.bb5, %sw.bb3, %sw.bb2, %sw.bb, %while.body
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%result.1 = phi i32 [ %result.020, %while.body ], [ %or, %sw.bb7 ], [ %shr, %sw.bb6 ], [ %shl, %sw.bb5 ], [ %mul4, %sw.bb3 ], [ %dec, %sw.bb2 ], [ %add, %sw.bb ]
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%2 = load volatile i32, i32* @x, align 4, !tbaa !3
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%cmp = icmp sgt i32 %2, 0
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br i1 %cmp, label %land.rhs, label %while.end
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while.end: ; preds = %sw.epilog, %land.rhs, %entry
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%result.0.lcssa = phi i32 [ 0, %entry ], [ %result.020, %land.rhs ], [ %result.1, %sw.epilog ]
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ret i32 %result.0.lcssa
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}
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; Function Attrs: norecurse nounwind uwtable
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define i32 @ifElse(i32 %z) local_unnamed_addr #0 {
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entry:
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br label %while.cond.outer
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while.cond.outer: ; preds = %if.then, %if.then2, %if.then5, %if.then8, %if.then11, %entry
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%w.0.ph = phi i32 [ 0, %entry ], [ %sub, %if.then11 ], [ %add, %if.then8 ], [ %mul, %if.then5 ], [ %dec, %if.then2 ], [ %inc, %if.then ]
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br label %while.cond
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while.cond: ; preds = %if.else12, %while.cond.outer
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%0 = load volatile i32, i32* @x, align 4, !tbaa !3
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%cmp = icmp slt i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %while.cond
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%inc = add nsw i32 %w.0.ph, 1
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br label %while.cond.outer
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if.else: ; preds = %while.cond
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%1 = load volatile i32, i32* @y, align 4, !tbaa !3
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%cmp1 = icmp sgt i32 %1, 0
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br i1 %cmp1, label %if.then2, label %if.else3
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if.then2: ; preds = %if.else
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%dec = add nsw i32 %w.0.ph, -1
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br label %while.cond.outer
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if.else3: ; preds = %if.else
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%2 = load volatile i32, i32* @x, align 4, !tbaa !3
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%3 = load volatile i32, i32* @y, align 4, !tbaa !3
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%and = and i32 %3, %2
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%cmp4 = icmp eq i32 %and, 3
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br i1 %cmp4, label %if.then5, label %if.else6
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if.then5: ; preds = %if.else3
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%mul = shl nsw i32 %w.0.ph, 1
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br label %while.cond.outer
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if.else6: ; preds = %if.else3
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%4 = load volatile i32, i32* @x, align 4, !tbaa !3
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%5 = load volatile i32, i32* @y, align 4, !tbaa !3
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%or = or i32 %5, %4
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%cmp7 = icmp eq i32 %or, 18
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br i1 %cmp7, label %if.then8, label %if.else9
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if.then8: ; preds = %if.else6
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%add = add nsw i32 %w.0.ph, 2
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br label %while.cond.outer
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if.else9: ; preds = %if.else6
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%6 = load volatile i32, i32* @y, align 4, !tbaa !3
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%7 = load volatile i32, i32* @x, align 4, !tbaa !3
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%xor = xor i32 %7, %6
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%cmp10 = icmp eq i32 %xor, 154
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br i1 %cmp10, label %if.then11, label %if.else12
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if.then11: ; preds = %if.else9
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%sub = add nsw i32 %w.0.ph, -3
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br label %while.cond.outer
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if.else12: ; preds = %if.else9
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%8 = load volatile i32, i32* @y, align 4, !tbaa !3
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%9 = load volatile i32, i32* @x, align 4, !tbaa !3
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%xor13 = xor i32 %9, %8
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%and14 = and i32 %xor13, 1
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%cmp15 = icmp eq i32 %and14, 0
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br i1 %cmp15, label %while.cond, label %while.end
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while.end: ; preds = %if.else12
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ret i32 %w.0.ph
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}
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attributes #0 = { norecurse nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="haswell" "target-features"="+aes,+avx,+avx2,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 2}
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!1 = !{i32 7, !"PIC Level", i32 2}
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!2 = !{!"clang version 6.0.0 (ssh://git-amr-1.devtools.intel.com:29418/dpd_icl-llvm_clang_worldread 3789ad4283ec09df1ed8411abbb227d76e7ef8cb) (ssh://git-amr-1.devtools.intel.com:29418/dpd_icl-llvm_llvm_worldread 42897913cc9fac0d94e8636d9aed4dc193d7864e)"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"int", !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C/C++ TBAA"}
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...
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---
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name: switchCase
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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...
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---
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name: ifElse
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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...
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