[AArch64][SVE] Add reg+imm addressing mode for unpredicated loads

Reviewers: efriedma, sdesmalen, david-arm

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82893
This commit is contained in:
Kerry McLaughlin 2020-07-01 10:00:35 +01:00
parent 7dcc3858e7
commit 4c6683eafc
2 changed files with 111 additions and 2 deletions

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@ -1719,8 +1719,15 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
multiclass unpred_load<PatFrag Load, ValueType Ty, Instruction RegImmInst,
Instruction PTrue> {
def : Pat<(Ty (Load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
let AddedComplexity = 1 in {
def _imm: Pat<(Ty (Load (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset))),
(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
}
let AddedComplexity = 2 in {
def _fi : Pat<(Ty (Load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
}
def : Pat<(Ty (Load GPR64:$base)),
(RegImmInst (PTrue 31), GPR64:$base, (i64 0))>;

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@ -0,0 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; LD1B
define <vscale x 16 x i8> @ld1b_lower_bound(<vscale x 16 x i8>* %a) {
; CHECK-LABEL: ld1b_lower_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #-8, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -8
%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
ret <vscale x 16 x i8> %load
}
define <vscale x 16 x i8> @ld1b_inbound(<vscale x 16 x i8>* %a) {
; CHECK-LABEL: ld1b_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 2
%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
ret <vscale x 16 x i8> %load
}
define <vscale x 16 x i8> @ld1b_upper_bound(<vscale x 16 x i8>* %a) {
; CHECK-LABEL: ld1b_upper_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #7, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
ret <vscale x 16 x i8> %load
}
define <vscale x 16 x i8> @ld1b_out_of_upper_bound(<vscale x 16 x i8>* %a) {
; CHECK-LABEL: ld1b_out_of_upper_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #8
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
ret <vscale x 16 x i8> %load
}
define <vscale x 16 x i8> @ld1b_out_of_lower_bound(<vscale x 16 x i8>* %a) {
; CHECK-LABEL: ld1b_out_of_lower_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #-9
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
ret <vscale x 16 x i8> %load
}
; LD1H
define <vscale x 8 x i16> @ld1h_inbound(<vscale x 8 x i16>* %a) {
; CHECK-LABEL: ld1h_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #-2, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %a, i64 -2
%load = load <vscale x 8 x i16>, <vscale x 8 x i16>* %base
ret <vscale x 8 x i16> %load
}
; LD1W
define <vscale x 4 x i32> @ld1s_inbound(<vscale x 4 x i32>* %a) {
; CHECK-LABEL: ld1s_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, #4, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 4
%load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %base
ret <vscale x 4 x i32> %load
}
; LD1D
define <vscale x 2 x i64> @ld1d_inbound(<vscale x 2 x i64>* %a) {
; CHECK-LABEL: ld1d_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #6, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %a, i64 6
%load = load <vscale x 2 x i64>, <vscale x 2 x i64>* %base
ret <vscale x 2 x i64> %load
}