forked from OSchip/llvm-project
[AArch64][SVE] Add reg+imm addressing mode for unpredicated loads
Reviewers: efriedma, sdesmalen, david-arm Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D82893
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@ -1719,8 +1719,15 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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multiclass unpred_load<PatFrag Load, ValueType Ty, Instruction RegImmInst,
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Instruction PTrue> {
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def : Pat<(Ty (Load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
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(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
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let AddedComplexity = 1 in {
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def _imm: Pat<(Ty (Load (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset))),
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(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
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}
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let AddedComplexity = 2 in {
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def _fi : Pat<(Ty (Load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
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(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
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}
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def : Pat<(Ty (Load GPR64:$base)),
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(RegImmInst (PTrue 31), GPR64:$base, (i64 0))>;
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@ -0,0 +1,102 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; LD1B
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define <vscale x 16 x i8> @ld1b_lower_bound(<vscale x 16 x i8>* %a) {
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; CHECK-LABEL: ld1b_lower_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #-8, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -8
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%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
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ret <vscale x 16 x i8> %load
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}
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define <vscale x 16 x i8> @ld1b_inbound(<vscale x 16 x i8>* %a) {
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; CHECK-LABEL: ld1b_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 2
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%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
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ret <vscale x 16 x i8> %load
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}
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define <vscale x 16 x i8> @ld1b_upper_bound(<vscale x 16 x i8>* %a) {
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; CHECK-LABEL: ld1b_upper_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #7, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
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%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
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ret <vscale x 16 x i8> %load
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}
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define <vscale x 16 x i8> @ld1b_out_of_upper_bound(<vscale x 16 x i8>* %a) {
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; CHECK-LABEL: ld1b_out_of_upper_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #8
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
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%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
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ret <vscale x 16 x i8> %load
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}
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define <vscale x 16 x i8> @ld1b_out_of_lower_bound(<vscale x 16 x i8>* %a) {
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; CHECK-LABEL: ld1b_out_of_lower_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #-9
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
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%load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
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ret <vscale x 16 x i8> %load
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}
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; LD1H
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define <vscale x 8 x i16> @ld1h_inbound(<vscale x 8 x i16>* %a) {
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; CHECK-LABEL: ld1h_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #-2, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %a, i64 -2
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%load = load <vscale x 8 x i16>, <vscale x 8 x i16>* %base
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ret <vscale x 8 x i16> %load
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}
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; LD1W
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define <vscale x 4 x i32> @ld1s_inbound(<vscale x 4 x i32>* %a) {
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; CHECK-LABEL: ld1s_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, #4, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 4
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%load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %base
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ret <vscale x 4 x i32> %load
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}
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; LD1D
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define <vscale x 2 x i64> @ld1d_inbound(<vscale x 2 x i64>* %a) {
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; CHECK-LABEL: ld1d_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #6, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %a, i64 6
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%load = load <vscale x 2 x i64>, <vscale x 2 x i64>* %base
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ret <vscale x 2 x i64> %load
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}
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