maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Optimize immediate materialisation with SH*ADD 

Use LUI+SH*ADD+ADDI to compose specific immediates.

Reviewed By: craig.topper, luismarques

Differential Revision: https://reviews.llvm.org/D113568
This commit is contained in:
Ben Shi 2021-11-11 12:57:33 +00:00
parent 39256ed58c
commit 4c3d916c4b
3 changed files with 56 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
View File

@ -284,6 +284,32 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
if (TmpSeq.size() < Res.size())
Res = TmpSeq;
}
// Try to use LUI+SH*ADD+ADDI.
int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
int64_t Lo12 = SignExtend64<12>(Val);
Div = 0;
if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
Div = 3;
Opc = RISCV::SH1ADD;
} else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
Div = 5;
Opc = RISCV::SH2ADD;
} else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
Div = 9;
Opc = RISCV::SH3ADD;
}
// Build the new instruction sequence.
if (Div > 0) {
// For Val that has zero Lo12 (implies Val equals to Hi52) should has
// already been processed to LUI+SH*ADD by previous optimization.
assert(Lo12 != 0 &&
"unexpected instruction sequence for immediate materialisation");
generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq);
TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0));
TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
if (TmpSeq.size() < Res.size())
Res = TmpSeq;
}
}
return Res;

25
llvm/test/CodeGen/RISCV/imm.ll
View File

@ -1712,9 +1712,8 @@ define i64 @imm_7158272001() {
;
; RV64IZBA-LABEL: imm_7158272001:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 427
; RV64IZBA-NEXT: addiw a0, a0, -1367
; RV64IZBA-NEXT: slli a0, a0, 12
; RV64IZBA-NEXT: lui a0, 349525
; RV64IZBA-NEXT: sh2add a0, a0, a0
; RV64IZBA-NEXT: addi a0, a0, 1
; RV64IZBA-NEXT: ret
;
@ -1746,9 +1745,8 @@ define i64 @imm_12884889601() {
;
; RV64IZBA-LABEL: imm_12884889601:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 768
; RV64IZBA-NEXT: addiw a0, a0, -3
; RV64IZBA-NEXT: slli a0, a0, 12
; RV64IZBA-NEXT: lui a0, 349525
; RV64IZBA-NEXT: sh3add a0, a0, a0
; RV64IZBA-NEXT: addi a0, a0, 1
; RV64IZBA-NEXT: ret
;
@ -1780,9 +1778,8 @@ define i64 @imm_neg_3435982847() {
;
; RV64IZBA-LABEL: imm_neg_3435982847:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 1048371
; RV64IZBA-NEXT: addiw a0, a0, 817
; RV64IZBA-NEXT: slli a0, a0, 12
; RV64IZBA-NEXT: lui a0, 768955
; RV64IZBA-NEXT: sh1add a0, a0, a0
; RV64IZBA-NEXT: addi a0, a0, 1
; RV64IZBA-NEXT: ret
;
@ -1813,9 +1810,8 @@ define i64 @imm_neg_5726842879() {
;
; RV64IZBA-LABEL: imm_neg_5726842879:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 1048235
; RV64IZBA-NEXT: addiw a0, a0, -1419
; RV64IZBA-NEXT: slli a0, a0, 12
; RV64IZBA-NEXT: lui a0, 768945
; RV64IZBA-NEXT: sh2add a0, a0, a0
; RV64IZBA-NEXT: addi a0, a0, 1
; RV64IZBA-NEXT: ret
;
@ -1846,9 +1842,8 @@ define i64 @imm_neg_10307948543() {
;
; RV64IZBA-LABEL: imm_neg_10307948543:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 1047962
; RV64IZBA-NEXT: addiw a0, a0, -1645
; RV64IZBA-NEXT: slli a0, a0, 12
; RV64IZBA-NEXT: lui a0, 768955
; RV64IZBA-NEXT: sh3add a0, a0, a0
; RV64IZBA-NEXT: addi a0, a0, 1
; RV64IZBA-NEXT: ret
;

50
llvm/test/MC/RISCV/rv64zba-aliases-valid.s
View File

@ -117,52 +117,42 @@ li x6, 12900925247761
# CHECK-S-OBJ-NEXT: addi t1, t1, -1366
li x6, 12900918536874
# CHECK-S-OBJ-NOALIAS: lui t1, 427
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -1367
# CHECK-S-OBJ-NOALIAS-NEXT: slli t1, t1, 12
# CHECK-S-OBJ-NOALIAS: lui t1, 349525
# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
# CHECK-S-OBJ-NOALIAS-NEXT: addi t1, t1, 1
# CHECK-S-OBJ: lui t1, 427
# CHECK-S-OBJ-NEXT: addiw t1, t1, -1367
# CHECK-S-OBJ-NEXT: slli t1, t1, 12
# CHECK-S-OBJ: lui t1, 349525
# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
# CHECK-S-OBJ-NEXT: addi t1, t1, 1
li x6, 7158272001 # 0x0000_0001_aaaa_9001
# CHECK-S-OBJ-NOALIAS: lui t1, 768
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -3
# CHECK-S-OBJ-NOALIAS-NEXT: slli t1, t1, 12
# CHECK-S-OBJ-NOALIAS: lui t1, 349525
# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
# CHECK-S-OBJ-NOALIAS-NEXT: addi t1, t1, 1
# CHECK-S-OBJ: lui t1, 768
# CHECK-S-OBJ-NEXT: addiw t1, t1, -3
# CHECK-S-OBJ-NEXT: slli t1, t1, 12
# CHECK-S-OBJ: lui t1, 349525
# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
# CHECK-S-OBJ-NEXT: addi t1, t1, 1
li x6, 12884889601 # 0x0000_0002_ffff_d001
# CHECK-S-OBJ-NOALIAS: lui t1, 1048371
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 817
# CHECK-S-OBJ-NOALIAS-NEXT: slli t1, t1, 12
# CHECK-S-OBJ-NOALIAS: lui t1, 768955
# CHECK-S-OBJ-NOALIAS-NEXT: sh1add t1, t1, t1
# CHECK-S-OBJ-NOALIAS-NEXT: addi t1, t1, 1
# CHECK-S-OBJ: lui t1, 1048371
# CHECK-S-OBJ-NEXT: addiw t1, t1, 817
# CHECK-S-OBJ-NEXT: slli t1, t1, 12
# CHECK-S-OBJ: lui t1, 768955
# CHECK-S-OBJ-NEXT: sh1add t1, t1, t1
# CHECK-S-OBJ-NEXT: addi t1, t1, 1
li x6, -3435982847 # 0xffff_ffff_3333_1001
# CHECK-S-OBJ-NOALIAS: lui t1, 1048235
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -1419
# CHECK-S-OBJ-NOALIAS-NEXT: slli t1, t1, 12
# CHECK-S-OBJ-NOALIAS: lui t1, 768945
# CHECK-S-OBJ-NOALIAS-NEXT: sh2add t1, t1, t1
# CHECK-S-OBJ-NOALIAS-NEXT: addi t1, t1, 1
# CHECK-S-OBJ: lui t1, 1048235
# CHECK-S-OBJ-NEXT: addiw t1, t1, -1419
# CHECK-S-OBJ-NEXT: slli t1, t1, 12
# CHECK-S-OBJ: lui t1, 768945
# CHECK-S-OBJ-NEXT: sh2add t1, t1, t1
# CHECK-S-OBJ-NEXT: addi t1, t1, 1
li x6, -5726842879 # 0xffff_fffe_aaa7_5001
# CHECK-S-OBJ-NOALIAS: lui t1, 1047962
# CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -1645
# CHECK-S-OBJ-NOALIAS-NEXT: slli t1, t1, 12
# CHECK-S-OBJ-NOALIAS: lui t1, 768955
# CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
# CHECK-S-OBJ-NOALIAS-NEXT: addi t1, t1, 1
# CHECK-S-OBJ: lui t1, 1047962
# CHECK-S-OBJ-NEXT: addiw t1, t1, -1645
# CHECK-S-OBJ-NEXT: slli t1, t1, 12
# CHECK-S-OBJ: lui t1, 768955
# CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
# CHECK-S-OBJ-NEXT: addi t1, t1, 1
li x6, -10307948543 # 0xffff_fffd_9999_3001