forked from OSchip/llvm-project
parent
3c0d6afeec
commit
4c0a71223a
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@ -562,14 +562,13 @@ bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
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RegDU.init(*Slot);
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if (searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler)) {
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MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler))
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return false;
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return false;
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MBB.splice(llvm::next(Slot), &MBB, llvm::next(Filler).base());
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
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@ -583,14 +582,13 @@ bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
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RegDU.setCallerSaved(*Slot);
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if (searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler)) {
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MBB.splice(llvm::next(Slot), &MBB, Filler);
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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if (!searchRange(MBB, llvm::next(Slot), MBB.end(), RegDU, NM, Filler))
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return false;
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return false;
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MBB.splice(llvm::next(Slot), &MBB, Filler);
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MIBundleBuilder(MBB, Slot, llvm::next(llvm::next(Slot)));
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++UsefulSlots;
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return true;
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}
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bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
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@ -68,7 +68,7 @@ static const uint16_t Mips64DPRegs[8] = {
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// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
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static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
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if (!isShiftedMask_64(I))
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return false;
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return false;
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Size = CountPopulation_64(I);
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Pos = countTrailingZeros(I);
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@ -915,8 +915,7 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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// thisMBB:
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@ -947,7 +946,7 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
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BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
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MI->eraseFromParent(); // The instruction is gone now.
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MI->eraseFromParent(); // The instruction is gone now.
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return exitMBB;
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}
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@ -958,7 +957,7 @@ MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
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unsigned Size, unsigned BinOpcode,
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bool Nand) const {
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assert((Size == 1 || Size == 2) &&
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"Unsupported size for EmitAtomicBinaryPartial.");
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"Unsupported size for EmitAtomicBinaryPartial.");
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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@ -1075,7 +1074,7 @@ MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
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// and newval, binopres, mask
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BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
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BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
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} else {// atomic.swap
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} else { // atomic.swap
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// and newval, incr2, mask
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BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
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}
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@ -1106,15 +1105,14 @@ MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
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BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
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.addReg(SllRes).addImm(ShiftImm);
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MI->eraseFromParent(); // The instruction is gone now.
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MI->eraseFromParent(); // The instruction is gone now.
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return exitMBB;
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}
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MachineBasicBlock *
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MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size) const {
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MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size) const {
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assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
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MachineFunction *MF = BB->getParent();
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@ -1130,8 +1128,7 @@ MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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ZERO = Mips::ZERO;
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BNE = Mips::BNE;
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BEQ = Mips::BEQ;
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}
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else {
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} else {
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LL = Mips::LLD;
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SC = Mips::SCD;
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ZERO = Mips::ZERO_64;
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@ -1188,7 +1185,7 @@ MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
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BuildMI(BB, DL, TII->get(BEQ))
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.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
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MI->eraseFromParent(); // The instruction is gone now.
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MI->eraseFromParent(); // The instruction is gone now.
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return exitMBB;
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}
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@ -1374,9 +1371,7 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
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}
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SDValue MipsTargetLowering::
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lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
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{
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SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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// The first operand is the chain, the second is the condition, the third is
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// the block to branch to if the condition is true.
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SDValue Chain = Op.getOperand(0);
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@ -2117,19 +2112,14 @@ SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
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// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
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//===----------------------------------------------------------------------===//
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static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
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MVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State,
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const uint16_t *F64Regs) {
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static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
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CCState &State, const uint16_t *F64Regs) {
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static const unsigned IntRegsSize=4, FloatRegsSize=2;
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static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
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static const uint16_t IntRegs[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const uint16_t F32Regs[] = {
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Mips::F12, Mips::F14
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};
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static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
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static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 };
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// Do not process byval args here.
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if (ArgFlags.isByVal())
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@ -2924,7 +2914,7 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
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if (VT == MVT::Other)
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VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
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RC= getRegClassFor(VT);
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RC = getRegClassFor(VT);
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if (RC == &Mips::AFGR64RegClass) {
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assert(Reg % 2 == 0);
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@ -3092,8 +3082,8 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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bool
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MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
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bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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Type *Ty) const {
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// No global is ever allowed as a base.
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if (AM.BaseGV)
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return false;
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@ -3157,13 +3147,13 @@ static bool isF128SoftLibCall(const char *CallSym) {
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"log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
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"truncl"};
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const char * const *End = LibCalls + array_lengthof(LibCalls);
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const char *const *End = LibCalls + array_lengthof(LibCalls);
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// Check that LibCalls is sorted alphabetically.
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MipsTargetLowering::LTStr Comp;
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#ifndef NDEBUG
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for (const char * const *I = LibCalls; I < End - 1; ++I)
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for (const char *const *I = LibCalls; I < End - 1; ++I)
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assert(Comp(*I, *(I + 1)));
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#endif
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@ -3202,7 +3192,7 @@ MipsTargetLowering::MipsCC::SpecialCallingConvType
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MipsTargetLowering::MipsCC::MipsCC(
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CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
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MipsCC::SpecialCallingConvType SpecialCallingConv_)
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MipsCC::SpecialCallingConvType SpecialCallingConv_)
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: CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
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SpecialCallingConv(SpecialCallingConv_){
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// Pre-allocate reserved argument area.
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@ -3317,11 +3307,10 @@ analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
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analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
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}
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void
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MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
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MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags) {
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void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
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MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags) {
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assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
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struct ByValArgInfo ByVal;
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@ -3541,17 +3530,15 @@ passByValArg(SDValue Chain, SDLoc DL,
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DAG.getConstant(Offset, PtrTy));
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SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
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DAG.getIntPtrConstant(ByVal.Address));
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Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
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DAG.getConstant(MemCpySize, PtrTy), Alignment,
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/*isVolatile=*/false, /*AlwaysInline=*/false,
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Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
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Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
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MachinePointerInfo(0), MachinePointerInfo(0));
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MemOpChains.push_back(Chain);
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}
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void
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MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
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const MipsCC &CC, SDValue Chain,
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SDLoc DL, SelectionDAG &DAG) const {
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void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
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const MipsCC &CC, SDValue Chain,
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SDLoc DL, SelectionDAG &DAG) const {
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unsigned NumRegs = CC.numIntArgRegs();
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const uint16_t *ArgRegs = CC.intArgRegs();
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const CCState &CCInfo = CC.getCCInfo();
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if (NumRegs == Idx)
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VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
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else
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VaArgOffset =
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(int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
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VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
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// Record the frame index of the first variable argument
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// which is a value necessary to VASTART.
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