forked from OSchip/llvm-project
All PPC instructions are now auto-printed
32 and 64 bit AsmWriters unified Darwin and AIX specific features of AsmWriter split out llvm-svn: 16163
This commit is contained in:
Nate Begeman
parent
b9c90a2b02
commit
4bfceb1ed5
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@ -1,4 +1,4 @@
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//===-- PPC32AsmPrinter.cpp - Print machine instrs to PowerPC assembly ----===//
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//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -18,7 +18,7 @@
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#define DEBUG_TYPE "asmprinter"
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#include "PowerPC.h"
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#include "PPC32TargetMachine.h"
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#include "PowerPCTargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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@ -42,26 +42,20 @@ namespace {
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struct PPC32AsmPrinter : public AsmPrinter {
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std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
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std::set<std::string> Strings;
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PPC32AsmPrinter(std::ostream &O, TargetMachine &TM)
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: AsmPrinter(O, TM), LabelNumber(0) {
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CommentString = ";";
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GlobalPrefix = "_";
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ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
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Data64bitsDirective = 0; // we can't emit a 64-bit unit
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AlignmentIsInBytes = false; // Alignment is by power of 2.
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}
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: AsmPrinter(O, TM), LabelNumber(0) {}
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/// Unique incrementer for label values for referencing Global values.
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///
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unsigned LabelNumber;
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virtual const char *getPassName() const {
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return "PPC32 Assembly Printer";
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return "PowerPC Assembly Printer";
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}
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PPC32TargetMachine &getTM() {
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return static_cast<PPC32TargetMachine&>(TM);
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PowerPCTargetMachine &getTM() {
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return static_cast<PowerPCTargetMachine&>(TM);
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}
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/// printInstruction - This method is automatically generated by tablegen
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@ -72,7 +66,6 @@ namespace {
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool LoadAddrOp = false);
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void printImmOp(const MachineOperand &MO, unsigned ArgType);
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void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
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const MachineOperand &MO = MI->getOperand(OpNo);
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@ -98,13 +91,24 @@ namespace {
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assert(value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)value;
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}
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void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (short)MI->getOperand(OpNo).getImmedValue();
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}
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void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
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}
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void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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printOp(MI->getOperand(OpNo));
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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if (MI->getOperand(OpNo).isImmediate()) {
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O << "$+" << MI->getOperand(OpNo).getImmedValue() << '\n';
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} else {
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printOp(MI->getOperand(OpNo));
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}
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}
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void printPICLabel(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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@ -112,80 +116,195 @@ namespace {
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O << "\"L0000" << LabelNumber << "$pb\"\n";
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O << "\"L0000" << LabelNumber << "$pb\":";
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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O << "ha16(";
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printOp(MI->getOperand(OpNo), true /* LoadAddrOp */);
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O << "-\"L0000" << LabelNumber << "$pb\")";
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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// FIXME: Because LFS, LFD, and LWZ can be used either with a s16imm or
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// a lo16 of a global or constant pool operand, we must handle both here.
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// this isn't a great design, but it works for now.
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if (MI->getOperand(OpNo).isImmediate()) {
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O << (short)MI->getOperand(OpNo).getImmedValue();
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} else {
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O << "lo16(";
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printOp(MI->getOperand(OpNo), true /* LoadAddrOp */);
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O << "-\"L0000" << LabelNumber << "$pb\")";
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}
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}
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virtual void printConstantPool(MachineConstantPool *MCP) = 0;
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virtual bool runOnMachineFunction(MachineFunction &F) = 0;
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virtual bool doFinalization(Module &M) = 0;
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};
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//
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//
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struct DarwinAsmPrinter : public PPC32AsmPrinter {
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DarwinAsmPrinter(std::ostream &O, TargetMachine &TM)
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: PPC32AsmPrinter(O, TM) {
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CommentString = ";";
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GlobalPrefix = "_";
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ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
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Data64bitsDirective = 0; // we can't emit a 64-bit unit
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AlignmentIsInBytes = false; // Alignment is by power of 2.
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}
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virtual const char *getPassName() const {
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return "Darwin PPC Assembly Printer";
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}
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doFinalization(Module &M);
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};
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//
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//
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struct AIXAsmPrinter : public PPC32AsmPrinter {
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/// Map for labels corresponding to global variables
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///
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std::map<const GlobalVariable*,std::string> GVToLabelMap;
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AIXAsmPrinter(std::ostream &O, TargetMachine &TM)
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: PPC32AsmPrinter(O, TM) {
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CommentString = "#";
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GlobalPrefix = "_";
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ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
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Data64bitsDirective = 0; // we can't emit a 64-bit unit
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AlignmentIsInBytes = false; // Alignment is by power of 2.
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}
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virtual const char *getPassName() const {
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return "AIX PPC Assembly Printer";
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}
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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};
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} // end of anonymous namespace
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/// createPPC32AsmPrinterPass - Returns a pass that prints the PPC
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/// assembly code for a MachineFunction to the given output stream,
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/// using the given target machine description. This should work
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/// regardless of whether the function is in SSA form or not.
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// SwitchSection - Switch to the specified section of the executable if we are
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// not already in it!
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//
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static void SwitchSection(std::ostream &OS, std::string &CurSection,
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const char *NewSection) {
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if (CurSection != NewSection) {
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CurSection = NewSection;
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if (!CurSection.empty())
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OS << "\t" << NewSection << "\n";
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}
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}
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/// isStringCompatible - Can we treat the specified array as a string?
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/// Only if it is an array of ubytes or non-negative sbytes.
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///
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FunctionPass *llvm::createPPC32AsmPrinter(std::ostream &o, TargetMachine &tm) {
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return new PPC32AsmPrinter(o, tm);
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static bool isStringCompatible(const ConstantArray *CVA) {
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const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType();
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if (ETy == Type::UByteTy) return true;
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if (ETy != Type::SByteTy) return false;
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for (unsigned i = 0; i < CVA->getNumOperands(); ++i)
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if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0)
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return false;
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return true;
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}
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/// toOctal - Convert the low order bits of X into an octal digit.
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///
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static inline char toOctal(int X) {
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return (X&7)+'0';
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}
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// Possible states while outputting ASCII strings
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namespace {
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enum StringSection {
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None,
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Alpha,
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Numeric
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};
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}
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/// SwitchStringSection - manage the changes required to output bytes as
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/// characters in a string vs. numeric decimal values
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///
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static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
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StringSection &Current) {
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if (Current == None) {
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if (NewSect == Alpha)
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O << "\t.byte \"";
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else if (NewSect == Numeric)
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O << "\t.byte ";
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} else if (Current == Alpha) {
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if (NewSect == None)
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O << "\"";
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else if (NewSect == Numeric)
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O << "\"\n"
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<< "\t.byte ";
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} else if (Current == Numeric) {
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if (NewSect == Alpha)
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O << '\n'
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<< "\t.byte \"";
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else if (NewSect == Numeric)
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O << ", ";
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}
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Current = NewSect;
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}
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/// getAsCString - Return the specified array as a C compatible
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/// string, only if the predicate isStringCompatible is true.
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///
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static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
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assert(isStringCompatible(CVA) && "Array is not string compatible!");
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if (CVA->getNumOperands() == 0)
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return;
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StringSection Current = None;
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for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) {
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unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
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if (C == '"') {
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SwitchStringSection(O, Alpha, Current);
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O << "\"\"";
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} else if (isprint(C)) {
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SwitchStringSection(O, Alpha, Current);
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O << C;
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} else {
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SwitchStringSection(O, Numeric, Current);
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O << utostr((unsigned)C);
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}
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}
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SwitchStringSection(O, None, Current);
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O << '\n';
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}
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/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
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/// code for a MachineFunction to the given output stream, in a format that the
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/// Darwin assembler can deal with.
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///
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FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
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return new DarwinAsmPrinter(o, tm);
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}
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/// createAIXAsmPrinterPass - Returns a pass that prints the PPC assembly code
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/// for a MachineFunction to the given output stream, in a format that the
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/// AIX 5L assembler can deal with.
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///
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FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
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return new AIXAsmPrinter(o, tm);
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}
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// Include the auto-generated portion of the assembly writer
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#include "PowerPCGenAsmWriter.inc"
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/// printConstantPool - Print to the current output stream assembly
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/// representations of the constants in the constant pool MCP. This is
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/// used to print out constants which have been "spilled to memory" by
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/// the code generator.
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///
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void PPC32AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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const std::vector<Constant*> &CP = MCP->getConstants();
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const TargetData &TD = TM.getTargetData();
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if (CP.empty()) return;
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for (unsigned i = 0, e = CP.size(); i != e; ++i) {
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O << "\t.const\n";
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emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
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O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
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<< *CP[i] << "\n";
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emitGlobalConstant(CP[i]);
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}
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool PPC32AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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setupMachineFunction(MF);
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O << "\n\n";
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// Print out constants referenced by the function
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printConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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O << "\t.text\n";
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emitAlignment(2);
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << CurrentFnName << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
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<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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++LabelNumber;
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// We didn't modify anything.
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return false;
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}
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void PPC32AsmPrinter::printOp(const MachineOperand &MO,
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bool LoadAddrOp /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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@ -268,15 +387,6 @@ void PPC32AsmPrinter::printOp(const MachineOperand &MO,
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}
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}
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void PPC32AsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) {
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int Imm = MO.getImmedValue();
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if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
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O << (short)Imm;
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} else {
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O << Imm;
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}
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}
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/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
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/// the current output stream.
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///
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@ -284,100 +394,68 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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if (printInstruction(MI))
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return; // Printer was automatically generated
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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unsigned i;
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unsigned ArgCount = MI->getNumOperands();
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unsigned ArgType[] = {
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(Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
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(Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
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(Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
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(Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
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(Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
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};
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assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
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"Instruction requires VMX support");
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assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
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"Instruction requires 64 bit support");
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O << TII.getName(Opcode) << " ";
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if (Opcode == PPC::LOADHiAddr) {
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printOp(MI->getOperand(0));
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O << ", ";
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if (MI->getOperand(1).getReg() == PPC::R0)
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O << "0";
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else
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printOp(MI->getOperand(1));
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O << ", ha16(" ;
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printOp(MI->getOperand(2), true /* LoadAddrOp */);
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O << "-\"L0000" << LabelNumber << "$pb\")\n";
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} else if (ArgCount == 3 && (MI->getOperand(2).isConstantPoolIndex()
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|| MI->getOperand(2).isGlobalAddress())) {
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printOp(MI->getOperand(0));
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O << ", lo16(";
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printOp(MI->getOperand(2), true /* LoadAddrOp */);
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O << "-\"L0000" << LabelNumber << "$pb\")";
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O << "(";
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if (MI->getOperand(1).getReg() == PPC::R0)
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O << "0";
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else
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printOp(MI->getOperand(1));
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O << ")\n";
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} else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
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printOp(MI->getOperand(0));
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O << ", ";
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printImmOp(MI->getOperand(1), ArgType[1]);
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O << "(";
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if (MI->getOperand(2).hasAllocatedReg() &&
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MI->getOperand(2).getReg() == PPC::R0)
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O << "0";
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else
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printOp(MI->getOperand(2));
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O << ")\n";
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} else {
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for (i = 0; i < ArgCount; ++i) {
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// addi and friends
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if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
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MI->getOperand(1).hasAllocatedReg() &&
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MI->getOperand(1).getReg() == PPC::R0) {
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O << "0";
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// for long branch support, bc $+8
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} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
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TII.isBranch(MI->getOpcode())) {
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O << "$+8";
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assert(8 == MI->getOperand(i).getImmedValue()
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&& "branch off PC not to pc+8?");
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//printOp(MI->getOperand(i));
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} else if (MI->getOperand(i).isImmediate()) {
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printImmOp(MI->getOperand(i), ArgType[i]);
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} else {
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printOp(MI->getOperand(i));
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}
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if (ArgCount - 1 == i)
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O << "\n";
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else
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O << ", ";
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}
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}
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assert(0 && "Unhandled instruction in asm writer!");
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abort();
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return;
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}
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// SwitchSection - Switch to the specified section of the executable if we are
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// not already in it!
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//
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static void SwitchSection(std::ostream &OS, std::string &CurSection,
|
||||
const char *NewSection) {
|
||||
if (CurSection != NewSection) {
|
||||
CurSection = NewSection;
|
||||
if (!CurSection.empty())
|
||||
OS << "\t" << NewSection << "\n";
|
||||
/// runOnMachineFunction - This uses the printMachineInstruction()
|
||||
/// method to print assembly for each instruction.
|
||||
///
|
||||
bool DarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
||||
setupMachineFunction(MF);
|
||||
O << "\n\n";
|
||||
|
||||
// Print out constants referenced by the function
|
||||
printConstantPool(MF.getConstantPool());
|
||||
|
||||
// Print out labels for the function.
|
||||
O << "\t.text\n";
|
||||
emitAlignment(2);
|
||||
O << "\t.globl\t" << CurrentFnName << "\n";
|
||||
O << CurrentFnName << ":\n";
|
||||
|
||||
// Print out code for the function.
|
||||
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
|
||||
I != E; ++I) {
|
||||
// Print a label for the basic block.
|
||||
O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
|
||||
<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
|
||||
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
|
||||
II != E; ++II) {
|
||||
// Print the assembly for the instruction.
|
||||
O << "\t";
|
||||
printMachineInstruction(II);
|
||||
}
|
||||
}
|
||||
++LabelNumber;
|
||||
|
||||
// We didn't modify anything.
|
||||
return false;
|
||||
}
|
||||
|
||||
/// printConstantPool - Print to the current output stream assembly
|
||||
/// representations of the constants in the constant pool MCP. This is
|
||||
/// used to print out constants which have been "spilled to memory" by
|
||||
/// the code generator.
|
||||
///
|
||||
void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
|
||||
const std::vector<Constant*> &CP = MCP->getConstants();
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
|
||||
if (CP.empty()) return;
|
||||
|
||||
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
|
||||
O << "\t.const\n";
|
||||
emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
|
||||
O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
|
||||
<< *CP[i] << "\n";
|
||||
emitGlobalConstant(CP[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bool PPC32AsmPrinter::doFinalization(Module &M) {
|
||||
bool DarwinAsmPrinter::doFinalization(Module &M) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
std::string CurSection;
|
||||
|
||||
|
|
@ -487,3 +565,145 @@ bool PPC32AsmPrinter::doFinalization(Module &M) {
|
|||
AsmPrinter::doFinalization(M);
|
||||
return false; // success
|
||||
}
|
||||
|
||||
/// runOnMachineFunction - This uses the printMachineInstruction()
|
||||
/// method to print assembly for each instruction.
|
||||
///
|
||||
bool AIXAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
||||
CurrentFnName = MF.getFunction()->getName();
|
||||
|
||||
// Print out constants referenced by the function
|
||||
printConstantPool(MF.getConstantPool());
|
||||
|
||||
// Print out header for the function.
|
||||
O << "\t.csect .text[PR]\n"
|
||||
<< "\t.align 2\n"
|
||||
<< "\t.globl " << CurrentFnName << '\n'
|
||||
<< "\t.globl ." << CurrentFnName << '\n'
|
||||
<< "\t.csect " << CurrentFnName << "[DS],3\n"
|
||||
<< CurrentFnName << ":\n"
|
||||
<< "\t.llong ." << CurrentFnName << ", TOC[tc0], 0\n"
|
||||
<< "\t.csect .text[PR]\n"
|
||||
<< '.' << CurrentFnName << ":\n";
|
||||
|
||||
// Print out code for the function.
|
||||
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
|
||||
I != E; ++I) {
|
||||
// Print a label for the basic block.
|
||||
O << "LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# "
|
||||
<< I->getBasicBlock()->getName() << "\n";
|
||||
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
|
||||
II != E; ++II) {
|
||||
// Print the assembly for the instruction.
|
||||
O << "\t";
|
||||
printMachineInstruction(II);
|
||||
}
|
||||
}
|
||||
++LabelNumber;
|
||||
|
||||
O << "LT.." << CurrentFnName << ":\n"
|
||||
<< "\t.long 0\n"
|
||||
<< "\t.byte 0,0,32,65,128,0,0,0\n"
|
||||
<< "\t.long LT.." << CurrentFnName << "-." << CurrentFnName << '\n'
|
||||
<< "\t.short 3\n"
|
||||
<< "\t.byte \"" << CurrentFnName << "\"\n"
|
||||
<< "\t.align 2\n";
|
||||
|
||||
// We didn't modify anything.
|
||||
return false;
|
||||
}
|
||||
|
||||
/// printConstantPool - Print to the current output stream assembly
|
||||
/// representations of the constants in the constant pool MCP. This is
|
||||
/// used to print out constants which have been "spilled to memory" by
|
||||
/// the code generator.
|
||||
///
|
||||
void AIXAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
|
||||
const std::vector<Constant*> &CP = MCP->getConstants();
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
|
||||
if (CP.empty()) return;
|
||||
|
||||
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
|
||||
O << "\t.const\n";
|
||||
O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
|
||||
<< "\n";
|
||||
O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t;"
|
||||
<< *CP[i] << "\n";
|
||||
emitGlobalConstant(CP[i]);
|
||||
}
|
||||
}
|
||||
|
||||
bool AIXAsmPrinter::doInitialization(Module &M) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
std::string CurSection;
|
||||
|
||||
O << "\t.machine \"ppc64\"\n"
|
||||
<< "\t.toc\n"
|
||||
<< "\t.csect .text[PR]\n";
|
||||
|
||||
// Print out module-level global variables
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
if (!I->hasInitializer())
|
||||
continue;
|
||||
|
||||
std::string Name = I->getName();
|
||||
Constant *C = I->getInitializer();
|
||||
// N.B.: We are defaulting to writable strings
|
||||
if (I->hasExternalLinkage()) {
|
||||
O << "\t.globl " << Name << '\n'
|
||||
<< "\t.csect .data[RW],3\n";
|
||||
} else {
|
||||
O << "\t.csect _global.rw_c[RW],3\n";
|
||||
}
|
||||
O << Name << ":\n";
|
||||
emitGlobalConstant(C);
|
||||
}
|
||||
|
||||
// Output labels for globals
|
||||
if (M.gbegin() != M.gend()) O << "\t.toc\n";
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
const GlobalVariable *GV = I;
|
||||
// Do not output labels for unused variables
|
||||
if (GV->isExternal() && GV->use_begin() == GV->use_end())
|
||||
continue;
|
||||
|
||||
std::string Name = GV->getName();
|
||||
std::string Label = "LC.." + utostr(LabelNumber++);
|
||||
GVToLabelMap[GV] = Label;
|
||||
O << Label << ":\n"
|
||||
<< "\t.tc " << Name << "[TC]," << Name;
|
||||
if (GV->isExternal()) O << "[RW]";
|
||||
O << '\n';
|
||||
}
|
||||
|
||||
Mang = new Mangler(M, ".");
|
||||
return false; // success
|
||||
}
|
||||
|
||||
bool AIXAsmPrinter::doFinalization(Module &M) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
// Print out module-level global variables
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
if (I->hasInitializer() || I->hasExternalLinkage())
|
||||
continue;
|
||||
|
||||
std::string Name = I->getName();
|
||||
if (I->hasInternalLinkage()) {
|
||||
O << "\t.lcomm " << Name << ",16,_global.bss_c";
|
||||
} else {
|
||||
O << "\t.comm " << Name << "," << TD.getTypeSize(I->getType())
|
||||
<< "," << log2((unsigned)TD.getTypeAlignment(I->getType()));
|
||||
}
|
||||
O << "\t\t# ";
|
||||
WriteAsOperand(O, I, true, true, &M);
|
||||
O << "\n";
|
||||
}
|
||||
|
||||
O << "_section_.text:\n"
|
||||
<< "\t.csect .data[RW],3\n"
|
||||
<< "\t.llong _section_.text\n";
|
||||
|
||||
delete Mang;
|
||||
return false; // success
|
||||
}
|
||||
|
|
|
|||
|
|
@ -624,12 +624,13 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
|
|||
copyGlobalBaseToRegister(MBB, IP, GlobalBase);
|
||||
BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
|
||||
.addConstantPoolIndex(CPI);
|
||||
BuildMI(*MBB, IP, Opcode, 2, R).addReg(Reg1).addConstantPoolIndex(CPI);
|
||||
BuildMI(*MBB, IP, Opcode, 2, R).addConstantPoolIndex(CPI).addReg(Reg1);
|
||||
} else if (isa<ConstantPointerNull>(C)) {
|
||||
// Copy zero (null pointer) to the register.
|
||||
BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
|
||||
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
|
||||
// GV is located at base + distance
|
||||
|
||||
unsigned GlobalBase = makeAnotherReg(Type::IntTy);
|
||||
unsigned TmpReg = makeAnotherReg(GV->getType());
|
||||
unsigned Opcode = (GV->hasWeakLinkage()
|
||||
|
|
@ -640,7 +641,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
|
|||
copyGlobalBaseToRegister(MBB, IP, GlobalBase);
|
||||
BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg).addReg(GlobalBase)
|
||||
.addGlobalAddress(GV);
|
||||
BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
|
||||
BuildMI(*MBB, IP, Opcode, 2, R).addGlobalAddress(GV).addReg(TmpReg);
|
||||
|
||||
// Add the GV to the list of things whose addresses have been taken.
|
||||
TM.AddressTaken.insert(GV);
|
||||
|
|
@ -1179,7 +1180,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
|
|||
Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
|
||||
} else {
|
||||
unsigned CondReg = getReg(Cond, MBB, IP);
|
||||
BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
|
||||
BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
|
||||
Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
|
||||
}
|
||||
unsigned TrueValue = getReg(TrueVal, BB, BB->end());
|
||||
|
|
|
|||
|
|
@ -17,11 +17,9 @@
|
|||
#include "PowerPCTargetMachine.h"
|
||||
#include "PPC32InstrInfo.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include <set>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class GlobalValue;
|
||||
class IntrinsicLowering;
|
||||
|
||||
class PPC32TargetMachine : public PowerPCTargetMachine {
|
||||
|
|
@ -38,11 +36,6 @@ public:
|
|||
|
||||
bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE);
|
||||
|
||||
// Two shared sets between the instruction selector and the printer allow for
|
||||
// correct linkage on Darwin
|
||||
std::set<GlobalValue*> CalledFunctions;
|
||||
std::set<GlobalValue*> AddressTaken;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
|||
|
|
@ -1,700 +0,0 @@
|
|||
//===-- PPC64AsmPrinter.cpp - Print machine instrs to PowerPC assembly ----===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains a printer that converts from our internal representation
|
||||
// of machine-dependent LLVM code to PowerPC assembly language. This printer is
|
||||
// the output mechanism used by `llc'.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#define DEBUG_TYPE "asmprinter"
|
||||
#include "PowerPC.h"
|
||||
#include "PowerPCInstrInfo.h"
|
||||
#include "PPC64TargetMachine.h"
|
||||
#include "llvm/Constants.h"
|
||||
#include "llvm/DerivedTypes.h"
|
||||
#include "llvm/Module.h"
|
||||
#include "llvm/Assembly/Writer.h"
|
||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/Support/Mangler.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
#include <set>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
namespace {
|
||||
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
|
||||
|
||||
struct Printer : public MachineFunctionPass {
|
||||
/// Output stream on which we're printing assembly code.
|
||||
///
|
||||
std::ostream &O;
|
||||
|
||||
/// Target machine description which we query for reg. names, data
|
||||
/// layout, etc.
|
||||
///
|
||||
PPC64TargetMachine &TM;
|
||||
|
||||
/// Name-mangler for global names.
|
||||
///
|
||||
Mangler *Mang;
|
||||
|
||||
/// Map for labels corresponding to global variables
|
||||
///
|
||||
std::map<const GlobalVariable*,std::string> GVToLabelMap;
|
||||
|
||||
Printer(std::ostream &o, TargetMachine &tm) : O(o),
|
||||
TM(reinterpret_cast<PPC64TargetMachine&>(tm)), LabelNumber(0) {}
|
||||
|
||||
/// Cache of mangled name for current function. This is
|
||||
/// recalculated at the beginning of each call to
|
||||
/// runOnMachineFunction().
|
||||
///
|
||||
std::string CurrentFnName;
|
||||
|
||||
/// Unique incrementer for label values for referencing Global values.
|
||||
///
|
||||
unsigned LabelNumber;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
return "PPC64 Assembly Printer";
|
||||
}
|
||||
|
||||
void printMachineInstruction(const MachineInstr *MI);
|
||||
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
|
||||
void printImmOp(const MachineOperand &MO, unsigned ArgType);
|
||||
void printConstantPool(MachineConstantPool *MCP);
|
||||
bool runOnMachineFunction(MachineFunction &F);
|
||||
bool doInitialization(Module &M);
|
||||
bool doFinalization(Module &M);
|
||||
void emitGlobalConstant(const Constant* CV);
|
||||
void emitConstantValueOnly(const Constant *CV);
|
||||
};
|
||||
} // end of anonymous namespace
|
||||
|
||||
/// createPPC64AsmPrinterPass - Returns a pass that prints the PPC
|
||||
/// assembly code for a MachineFunction to the given output stream,
|
||||
/// using the given target machine description. This should work
|
||||
/// regardless of whether the function is in SSA form or not.
|
||||
///
|
||||
FunctionPass *createPPC64AsmPrinter(std::ostream &o,TargetMachine &tm) {
|
||||
return new Printer(o, tm);
|
||||
}
|
||||
|
||||
/// isStringCompatible - Can we treat the specified array as a string?
|
||||
/// Only if it is an array of ubytes or non-negative sbytes.
|
||||
///
|
||||
static bool isStringCompatible(const ConstantArray *CVA) {
|
||||
const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType();
|
||||
if (ETy == Type::UByteTy) return true;
|
||||
if (ETy != Type::SByteTy) return false;
|
||||
|
||||
for (unsigned i = 0; i < CVA->getNumOperands(); ++i)
|
||||
if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// toOctal - Convert the low order bits of X into an octal digit.
|
||||
///
|
||||
static inline char toOctal(int X) {
|
||||
return (X&7)+'0';
|
||||
}
|
||||
|
||||
// Possible states while outputting ASCII strings
|
||||
namespace {
|
||||
enum StringSection {
|
||||
None,
|
||||
Alpha,
|
||||
Numeric
|
||||
};
|
||||
}
|
||||
|
||||
/// SwitchStringSection - manage the changes required to output bytes as
|
||||
/// characters in a string vs. numeric decimal values
|
||||
///
|
||||
static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
|
||||
StringSection &Current) {
|
||||
if (Current == None) {
|
||||
if (NewSect == Alpha)
|
||||
O << "\t.byte \"";
|
||||
else if (NewSect == Numeric)
|
||||
O << "\t.byte ";
|
||||
} else if (Current == Alpha) {
|
||||
if (NewSect == None)
|
||||
O << "\"";
|
||||
else if (NewSect == Numeric)
|
||||
O << "\"\n"
|
||||
<< "\t.byte ";
|
||||
} else if (Current == Numeric) {
|
||||
if (NewSect == Alpha)
|
||||
O << '\n'
|
||||
<< "\t.byte \"";
|
||||
else if (NewSect == Numeric)
|
||||
O << ", ";
|
||||
}
|
||||
|
||||
Current = NewSect;
|
||||
}
|
||||
|
||||
/// getAsCString - Return the specified array as a C compatible
|
||||
/// string, only if the predicate isStringCompatible is true.
|
||||
///
|
||||
static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
|
||||
assert(isStringCompatible(CVA) && "Array is not string compatible!");
|
||||
|
||||
if (CVA->getNumOperands() == 0)
|
||||
return;
|
||||
|
||||
StringSection Current = None;
|
||||
for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) {
|
||||
unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
|
||||
if (C == '"') {
|
||||
SwitchStringSection(O, Alpha, Current);
|
||||
O << "\"\"";
|
||||
} else if (isprint(C)) {
|
||||
SwitchStringSection(O, Alpha, Current);
|
||||
O << C;
|
||||
} else {
|
||||
SwitchStringSection(O, Numeric, Current);
|
||||
O << utostr((unsigned)C);
|
||||
}
|
||||
}
|
||||
SwitchStringSection(O, None, Current);
|
||||
O << '\n';
|
||||
}
|
||||
|
||||
// Print out the specified constant, without a storage class. Only the
|
||||
// constants valid in constant expressions can occur here.
|
||||
void Printer::emitConstantValueOnly(const Constant *CV) {
|
||||
if (CV->isNullValue())
|
||||
O << "0";
|
||||
else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
|
||||
assert(CB == ConstantBool::True);
|
||||
O << "1";
|
||||
} else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV))
|
||||
O << CI->getValue();
|
||||
else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV))
|
||||
O << CI->getValue();
|
||||
else if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV))
|
||||
// This is a constant address for a global variable or function. Use the
|
||||
// name of the variable or function as the address value.
|
||||
O << Mang->getValueName(GV);
|
||||
else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
switch (CE->getOpcode()) {
|
||||
case Instruction::GetElementPtr: {
|
||||
// generate a symbolic expression for the byte address
|
||||
const Constant *ptrVal = CE->getOperand(0);
|
||||
std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end());
|
||||
if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) {
|
||||
O << "(";
|
||||
emitConstantValueOnly(ptrVal);
|
||||
O << ") + " << Offset;
|
||||
} else {
|
||||
emitConstantValueOnly(ptrVal);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case Instruction::Cast: {
|
||||
// Support only non-converting or widening casts for now, that is, ones
|
||||
// that do not involve a change in value. This assertion is really gross,
|
||||
// and may not even be a complete check.
|
||||
Constant *Op = CE->getOperand(0);
|
||||
const Type *OpTy = Op->getType(), *Ty = CE->getType();
|
||||
|
||||
// Remember, kids, pointers on x86 can be losslessly converted back and
|
||||
// forth into 32-bit or wider integers, regardless of signedness. :-P
|
||||
assert(((isa<PointerType>(OpTy)
|
||||
&& (Ty == Type::LongTy || Ty == Type::ULongTy
|
||||
|| Ty == Type::IntTy || Ty == Type::UIntTy))
|
||||
|| (isa<PointerType>(Ty)
|
||||
&& (OpTy == Type::LongTy || OpTy == Type::ULongTy
|
||||
|| OpTy == Type::IntTy || OpTy == Type::UIntTy))
|
||||
|| (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy))
|
||||
&& OpTy->isLosslesslyConvertibleTo(Ty))))
|
||||
&& "FIXME: Don't yet support this kind of constant cast expr");
|
||||
O << "(";
|
||||
emitConstantValueOnly(Op);
|
||||
O << ")";
|
||||
break;
|
||||
}
|
||||
case Instruction::Add:
|
||||
O << "(";
|
||||
emitConstantValueOnly(CE->getOperand(0));
|
||||
O << ") + (";
|
||||
emitConstantValueOnly(CE->getOperand(1));
|
||||
O << ")";
|
||||
break;
|
||||
default:
|
||||
assert(0 && "Unsupported operator!");
|
||||
}
|
||||
} else {
|
||||
assert(0 && "Unknown constant value!");
|
||||
}
|
||||
}
|
||||
|
||||
// Print a constant value or values, with the appropriate storage class as a
|
||||
// prefix.
|
||||
void Printer::emitGlobalConstant(const Constant *CV) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
|
||||
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
|
||||
if (isStringCompatible(CVA)) {
|
||||
printAsCString(O, CVA);
|
||||
} else { // Not a string. Print the values in successive locations
|
||||
for (unsigned i=0, e = CVA->getNumOperands(); i != e; i++)
|
||||
emitGlobalConstant(CVA->getOperand(i));
|
||||
}
|
||||
return;
|
||||
} else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
|
||||
// Print the fields in successive locations. Pad to align if needed!
|
||||
const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType());
|
||||
unsigned sizeSoFar = 0;
|
||||
for (unsigned i = 0, e = CVS->getNumOperands(); i != e; i++) {
|
||||
const Constant* field = CVS->getOperand(i);
|
||||
|
||||
// Check if padding is needed and insert one or more 0s.
|
||||
unsigned fieldSize = TD.getTypeSize(field->getType());
|
||||
unsigned padSize = ((i == e-1? cvsLayout->StructSize
|
||||
: cvsLayout->MemberOffsets[i+1])
|
||||
- cvsLayout->MemberOffsets[i]) - fieldSize;
|
||||
sizeSoFar += fieldSize + padSize;
|
||||
|
||||
// Now print the actual field value
|
||||
emitGlobalConstant(field);
|
||||
|
||||
// Insert the field padding unless it's zero bytes...
|
||||
if (padSize)
|
||||
O << "\t.space\t " << padSize << "\n";
|
||||
}
|
||||
assert(sizeSoFar == cvsLayout->StructSize &&
|
||||
"Layout of constant struct may be incorrect!");
|
||||
return;
|
||||
} else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
|
||||
// FP Constants are printed as integer constants to avoid losing
|
||||
// precision...
|
||||
double Val = CFP->getValue();
|
||||
switch (CFP->getType()->getTypeID()) {
|
||||
default: assert(0 && "Unknown floating point type!");
|
||||
case Type::FloatTyID: {
|
||||
union FU { // Abide by C TBAA rules
|
||||
float FVal;
|
||||
unsigned UVal;
|
||||
} U;
|
||||
U.FVal = Val;
|
||||
O << "\t.long " << U.UVal << "\t# float " << Val << "\n";
|
||||
return;
|
||||
}
|
||||
case Type::DoubleTyID: {
|
||||
union DU { // Abide by C TBAA rules
|
||||
double FVal;
|
||||
uint64_t UVal;
|
||||
struct {
|
||||
uint32_t MSWord;
|
||||
uint32_t LSWord;
|
||||
} T;
|
||||
} U;
|
||||
U.FVal = Val;
|
||||
|
||||
O << ".long " << U.T.MSWord << "\t# double most significant word "
|
||||
<< Val << "\n";
|
||||
O << ".long " << U.T.LSWord << "\t# double least significant word "
|
||||
<< Val << "\n";
|
||||
return;
|
||||
}
|
||||
}
|
||||
} else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) {
|
||||
if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
|
||||
union DU { // Abide by C TBAA rules
|
||||
int64_t UVal;
|
||||
struct {
|
||||
uint32_t MSWord;
|
||||
uint32_t LSWord;
|
||||
} T;
|
||||
} U;
|
||||
U.UVal = CI->getRawValue();
|
||||
|
||||
O << ".long " << U.T.MSWord << "\t# Double-word most significant word "
|
||||
<< U.UVal << "\n";
|
||||
O << ".long " << U.T.LSWord << "\t# Double-word least significant word "
|
||||
<< U.UVal << "\n";
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
const Type *type = CV->getType();
|
||||
O << "\t";
|
||||
switch (type->getTypeID()) {
|
||||
case Type::UByteTyID: case Type::SByteTyID:
|
||||
O << "\t.byte";
|
||||
break;
|
||||
case Type::UShortTyID: case Type::ShortTyID:
|
||||
O << "\t.short";
|
||||
break;
|
||||
case Type::BoolTyID:
|
||||
case Type::PointerTyID:
|
||||
case Type::UIntTyID: case Type::IntTyID:
|
||||
O << "\t.long";
|
||||
break;
|
||||
case Type::ULongTyID: case Type::LongTyID:
|
||||
assert (0 && "Should have already output double-word constant.");
|
||||
case Type::FloatTyID: case Type::DoubleTyID:
|
||||
assert (0 && "Should have already output floating point constant.");
|
||||
default:
|
||||
if (CV == Constant::getNullValue(type)) { // Zero initializer?
|
||||
O << "\t.space " << TD.getTypeSize(type) << "\n";
|
||||
return;
|
||||
}
|
||||
std::cerr << "Can't handle printing: " << *CV;
|
||||
abort();
|
||||
break;
|
||||
}
|
||||
O << ' ';
|
||||
emitConstantValueOnly(CV);
|
||||
O << '\n';
|
||||
}
|
||||
|
||||
/// printConstantPool - Print to the current output stream assembly
|
||||
/// representations of the constants in the constant pool MCP. This is
|
||||
/// used to print out constants which have been "spilled to memory" by
|
||||
/// the code generator.
|
||||
///
|
||||
void Printer::printConstantPool(MachineConstantPool *MCP) {
|
||||
const std::vector<Constant*> &CP = MCP->getConstants();
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
|
||||
if (CP.empty()) return;
|
||||
|
||||
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
|
||||
O << "\t.const\n";
|
||||
O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
|
||||
<< "\n";
|
||||
O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t;"
|
||||
<< *CP[i] << "\n";
|
||||
emitGlobalConstant(CP[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/// runOnMachineFunction - This uses the printMachineInstruction()
|
||||
/// method to print assembly for each instruction.
|
||||
///
|
||||
bool Printer::runOnMachineFunction(MachineFunction &MF) {
|
||||
CurrentFnName = MF.getFunction()->getName();
|
||||
|
||||
// Print out constants referenced by the function
|
||||
printConstantPool(MF.getConstantPool());
|
||||
|
||||
// Print out header for the function.
|
||||
O << "\t.csect .text[PR]\n"
|
||||
<< "\t.align 2\n"
|
||||
<< "\t.globl " << CurrentFnName << '\n'
|
||||
<< "\t.globl ." << CurrentFnName << '\n'
|
||||
<< "\t.csect " << CurrentFnName << "[DS],3\n"
|
||||
<< CurrentFnName << ":\n"
|
||||
<< "\t.llong ." << CurrentFnName << ", TOC[tc0], 0\n"
|
||||
<< "\t.csect .text[PR]\n"
|
||||
<< '.' << CurrentFnName << ":\n";
|
||||
|
||||
// Print out code for the function.
|
||||
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
|
||||
I != E; ++I) {
|
||||
// Print a label for the basic block.
|
||||
O << "LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# "
|
||||
<< I->getBasicBlock()->getName() << "\n";
|
||||
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
|
||||
II != E; ++II) {
|
||||
// Print the assembly for the instruction.
|
||||
O << "\t";
|
||||
printMachineInstruction(II);
|
||||
}
|
||||
}
|
||||
++LabelNumber;
|
||||
|
||||
O << "LT.." << CurrentFnName << ":\n"
|
||||
<< "\t.long 0\n"
|
||||
<< "\t.byte 0,0,32,65,128,0,0,0\n"
|
||||
<< "\t.long LT.." << CurrentFnName << "-." << CurrentFnName << '\n'
|
||||
<< "\t.short 3\n"
|
||||
<< "\t.byte \"" << CurrentFnName << "\"\n"
|
||||
<< "\t.align 2\n";
|
||||
|
||||
// We didn't modify anything.
|
||||
return false;
|
||||
}
|
||||
|
||||
void Printer::printOp(const MachineOperand &MO,
|
||||
bool elideOffsetKeyword /* = false */) {
|
||||
const MRegisterInfo &RI = *TM.getRegisterInfo();
|
||||
int new_symbol;
|
||||
|
||||
switch (MO.getType()) {
|
||||
case MachineOperand::MO_VirtualRegister:
|
||||
if (Value *V = MO.getVRegValueOrNull()) {
|
||||
O << "<" << V->getName() << ">";
|
||||
return;
|
||||
}
|
||||
// FALLTHROUGH
|
||||
case MachineOperand::MO_MachineRegister:
|
||||
case MachineOperand::MO_CCRegister: {
|
||||
// On AIX, do not print out the 'R' (GPR) or 'F' (FPR) in reg names
|
||||
const char *regName = RI.get(MO.getReg()).Name;
|
||||
if (regName[0] == 'R' || regName[0] == 'F')
|
||||
O << ®Name[1];
|
||||
else
|
||||
O << regName;
|
||||
return;
|
||||
}
|
||||
|
||||
case MachineOperand::MO_SignExtendedImmed:
|
||||
case MachineOperand::MO_UnextendedImmed:
|
||||
std::cerr << "printOp() does not handle immediate values\n";
|
||||
abort();
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_PCRelativeDisp:
|
||||
std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
|
||||
abort();
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_MachineBasicBlock: {
|
||||
MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
|
||||
O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
|
||||
<< "_" << MBBOp->getNumber() << "\t# "
|
||||
<< MBBOp->getBasicBlock()->getName();
|
||||
return;
|
||||
}
|
||||
|
||||
case MachineOperand::MO_ConstantPoolIndex:
|
||||
O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_ExternalSymbol:
|
||||
O << MO.getSymbolName();
|
||||
return;
|
||||
|
||||
case MachineOperand::MO_GlobalAddress:
|
||||
if (!elideOffsetKeyword) {
|
||||
GlobalValue *GV = MO.getGlobal();
|
||||
|
||||
if (Function *F = dyn_cast<Function>(GV)) {
|
||||
O << Mang->getValueName(F);
|
||||
} else if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) {
|
||||
// output the label name
|
||||
O << GVToLabelMap[GVar];
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
default:
|
||||
O << "<unknown operand type: " << MO.getType() << ">";
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
|
||||
int Imm = MO.getImmedValue();
|
||||
if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
|
||||
O << (short)Imm;
|
||||
} else {
|
||||
O << Imm;
|
||||
}
|
||||
}
|
||||
|
||||
/// printMachineInstruction -- Print out a single PPC LLVM instruction
|
||||
/// MI in Darwin syntax to the current output stream.
|
||||
///
|
||||
void Printer::printMachineInstruction(const MachineInstr *MI) {
|
||||
unsigned Opcode = MI->getOpcode();
|
||||
const TargetInstrInfo &TII = *TM.getInstrInfo();
|
||||
const TargetInstrDescriptor &Desc = TII.get(Opcode);
|
||||
unsigned i;
|
||||
|
||||
unsigned ArgCount = MI->getNumOperands();
|
||||
unsigned ArgType[] = {
|
||||
(Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
|
||||
(Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
|
||||
(Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
|
||||
(Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
|
||||
(Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
|
||||
};
|
||||
assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
|
||||
"Instruction requires VMX support");
|
||||
++EmittedInsts;
|
||||
|
||||
// CALLpcrel and CALLindirect are handled specially here to print only the
|
||||
// appropriate number of args that the assembler expects. This is because
|
||||
// may have many arguments appended to record the uses of registers that are
|
||||
// holding arguments to the called function.
|
||||
if (Opcode == PPC::COND_BRANCH) {
|
||||
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
|
||||
abort();
|
||||
} else if (Opcode == PPC::IMPLICIT_DEF) {
|
||||
O << "# IMPLICIT DEF ";
|
||||
printOp(MI->getOperand(0));
|
||||
O << "\n";
|
||||
return;
|
||||
} else if (Opcode == PPC::CALLpcrel) {
|
||||
O << TII.getName(Opcode) << " ";
|
||||
printOp(MI->getOperand(0));
|
||||
O << "\n";
|
||||
return;
|
||||
} else if (Opcode == PPC::CALLindirect) {
|
||||
O << TII.getName(Opcode) << " ";
|
||||
printImmOp(MI->getOperand(0), ArgType[0]);
|
||||
O << ", ";
|
||||
printImmOp(MI->getOperand(1), ArgType[0]);
|
||||
O << "\n";
|
||||
return;
|
||||
} else if (Opcode == PPC::MovePCtoLR) {
|
||||
// FIXME: should probably be converted to cout.width and cout.fill
|
||||
O << "bl \"L0000" << LabelNumber << "$pb\"\n";
|
||||
O << "\"L0000" << LabelNumber << "$pb\":\n";
|
||||
O << "\tmflr ";
|
||||
printOp(MI->getOperand(0));
|
||||
O << "\n";
|
||||
return;
|
||||
}
|
||||
|
||||
O << LowercaseString(TII.getName(Opcode)) << " ";
|
||||
if (Opcode == PPC::BLR || Opcode == PPC::NOP) {
|
||||
O << "\n";
|
||||
} else if (ArgCount == 3 &&
|
||||
(ArgType[1] == PPCII::Disimm16 || ArgType[1] == PPCII::Disimm14)) {
|
||||
printOp(MI->getOperand(0));
|
||||
O << ", ";
|
||||
MachineOperand MO = MI->getOperand(1);
|
||||
if (MO.isImmediate())
|
||||
printImmOp(MO, ArgType[1]);
|
||||
else
|
||||
printOp(MO);
|
||||
O << "(";
|
||||
printOp(MI->getOperand(2));
|
||||
O << ")\n";
|
||||
} else {
|
||||
for (i = 0; i < ArgCount; ++i) {
|
||||
// addi and friends
|
||||
if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
|
||||
MI->getOperand(1).hasAllocatedReg() &&
|
||||
MI->getOperand(1).getReg() == PPC::R0) {
|
||||
O << "0";
|
||||
// for long branch support, bc $+8
|
||||
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
|
||||
TII.isBranch(MI->getOpcode())) {
|
||||
O << "$+8";
|
||||
assert(8 == MI->getOperand(i).getImmedValue()
|
||||
&& "branch off PC not to pc+8?");
|
||||
//printOp(MI->getOperand(i));
|
||||
} else if (MI->getOperand(i).isImmediate()) {
|
||||
printImmOp(MI->getOperand(i), ArgType[i]);
|
||||
} else {
|
||||
printOp(MI->getOperand(i));
|
||||
}
|
||||
if (ArgCount - 1 == i)
|
||||
O << "\n";
|
||||
else
|
||||
O << ", ";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// SwitchSection - Switch to the specified section of the executable if we are
|
||||
// not already in it!
|
||||
//
|
||||
static void SwitchSection(std::ostream &OS, std::string &CurSection,
|
||||
const char *NewSection) {
|
||||
if (CurSection != NewSection) {
|
||||
CurSection = NewSection;
|
||||
if (!CurSection.empty())
|
||||
OS << "\t" << NewSection << "\n";
|
||||
}
|
||||
}
|
||||
|
||||
bool Printer::doInitialization(Module &M) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
std::string CurSection;
|
||||
|
||||
O << "\t.machine \"ppc64\"\n"
|
||||
<< "\t.toc\n"
|
||||
<< "\t.csect .text[PR]\n";
|
||||
|
||||
// Print out module-level global variables
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
if (!I->hasInitializer())
|
||||
continue;
|
||||
|
||||
std::string Name = I->getName();
|
||||
Constant *C = I->getInitializer();
|
||||
// N.B.: We are defaulting to writable strings
|
||||
if (I->hasExternalLinkage()) {
|
||||
O << "\t.globl " << Name << '\n'
|
||||
<< "\t.csect .data[RW],3\n";
|
||||
} else {
|
||||
O << "\t.csect _global.rw_c[RW],3\n";
|
||||
}
|
||||
O << Name << ":\n";
|
||||
emitGlobalConstant(C);
|
||||
}
|
||||
|
||||
// Output labels for globals
|
||||
if (M.gbegin() != M.gend()) O << "\t.toc\n";
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
const GlobalVariable *GV = I;
|
||||
// Do not output labels for unused variables
|
||||
if (GV->isExternal() && GV->use_begin() == GV->use_end())
|
||||
continue;
|
||||
|
||||
std::string Name = GV->getName();
|
||||
std::string Label = "LC.." + utostr(LabelNumber++);
|
||||
GVToLabelMap[GV] = Label;
|
||||
O << Label << ":\n"
|
||||
<< "\t.tc " << Name << "[TC]," << Name;
|
||||
if (GV->isExternal()) O << "[RW]";
|
||||
O << '\n';
|
||||
}
|
||||
|
||||
Mang = new Mangler(M, ".");
|
||||
return false; // success
|
||||
}
|
||||
|
||||
bool Printer::doFinalization(Module &M) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
// Print out module-level global variables
|
||||
for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
|
||||
if (I->hasInitializer() || I->hasExternalLinkage())
|
||||
continue;
|
||||
|
||||
std::string Name = I->getName();
|
||||
if (I->hasInternalLinkage()) {
|
||||
O << "\t.lcomm " << Name << ",16,_global.bss_c";
|
||||
} else {
|
||||
O << "\t.comm " << Name << "," << TD.getTypeSize(I->getType())
|
||||
<< "," << log2((unsigned)TD.getTypeAlignment(I->getType()));
|
||||
}
|
||||
O << "\t\t# ";
|
||||
WriteAsOperand(O, I, true, true, &M);
|
||||
O << "\n";
|
||||
}
|
||||
|
||||
O << "_section_.text:\n"
|
||||
<< "\t.csect .data[RW],3\n"
|
||||
<< "\t.llong _section_.text\n";
|
||||
|
||||
delete Mang;
|
||||
return false; // success
|
||||
}
|
||||
|
||||
} // End llvm namespace
|
||||
|
|
@ -24,9 +24,9 @@ class TargetMachine;
|
|||
|
||||
FunctionPass *createPPCBranchSelectionPass();
|
||||
FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
|
||||
FunctionPass *createPPC32AsmPrinter(std::ostream &OS, TargetMachine &TM);
|
||||
FunctionPass *createPPC64ISelSimple(TargetMachine &TM);
|
||||
FunctionPass *createPPC64AsmPrinter(std::ostream &OS, TargetMachine &TM);
|
||||
FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
|
||||
FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
|
||||
|
||||
} // end namespace llvm;
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,8 @@ def Imm6 : Format<23>;
|
|||
//
|
||||
// PowerPC instruction formats
|
||||
|
||||
class I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
|
||||
class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: Instruction {
|
||||
field bits<32> Inst;
|
||||
|
||||
bits<3> ArgCount;
|
||||
|
|
@ -54,14 +55,16 @@ class I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
|
|||
bit PPC64 = ppc64;
|
||||
bit VMX = vmx;
|
||||
|
||||
let Name = name;
|
||||
let Name = "";
|
||||
let Namespace = "PPC";
|
||||
let Inst{0-5} = opcode;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
// 1.7.1 I-Form
|
||||
class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<24> LI;
|
||||
|
||||
let ArgCount = 1;
|
||||
|
|
@ -74,13 +77,11 @@ class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
|
|||
let Inst{6-29} = LI;
|
||||
let Inst{30} = aa;
|
||||
let Inst{31} = lk;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
// 1.7.2 B-Form
|
||||
class BForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
|
||||
: I<name, opcode, ppc64, vmx> {
|
||||
class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> BO;
|
||||
field bits<5> BI;
|
||||
field bits<14> BD;
|
||||
|
|
@ -99,9 +100,9 @@ class BForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
|
|||
let Inst{31} = lk;
|
||||
}
|
||||
|
||||
class BForm_ext<string name, bits<6> opcode, bit aa, bit lk, bits<5> bo,
|
||||
bits<5> bi, bit ppc64, bit vmx>
|
||||
: BForm<name, opcode, aa, lk, ppc64, vmx> {
|
||||
class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<5> bi,
|
||||
bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
|
||||
let ArgCount = 2;
|
||||
let Arg2Type = Imm5.Value;
|
||||
let Arg1Type = PCRelimm14.Value;
|
||||
|
|
@ -111,8 +112,8 @@ class BForm_ext<string name, bits<6> opcode, bit aa, bit lk, bits<5> bo,
|
|||
}
|
||||
|
||||
// 1.7.4 D-Form
|
||||
class DForm_base<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: I<name, opcode, ppc64, vmx> {
|
||||
class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> A;
|
||||
field bits<5> B;
|
||||
field bits<16> C;
|
||||
|
|
@ -129,32 +130,41 @@ class DForm_base<string name, bits<6> opcode, bit ppc64, bit vmx>
|
|||
let Inst{16-31} = C;
|
||||
}
|
||||
|
||||
class DForm_1<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_base<name, opcode, ppc64, vmx> {
|
||||
class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_base<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let Arg1Type = Disimm16.Value;
|
||||
let Arg2Type = Gpr0.Value;
|
||||
let Arg2Type = Gpr.Value;
|
||||
}
|
||||
|
||||
class DForm_2<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_base<name, opcode, ppc64, vmx>;
|
||||
class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_base<opcode, ppc64, vmx, OL, asmstr>;
|
||||
|
||||
class DForm_2_r0<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_base<name, opcode, ppc64, vmx> {
|
||||
let Arg1Type = Gpr0.Value;
|
||||
class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> A;
|
||||
field bits<16> B;
|
||||
|
||||
let ArgCount = 2;
|
||||
let Arg0Type = Gpr.Value;
|
||||
let Arg1Type = Simm16.Value;
|
||||
let Arg2Type = 0;
|
||||
let Arg3Type = 0;
|
||||
let Arg4Type = 0;
|
||||
|
||||
let Inst{6-10} = A;
|
||||
let Inst{11-15} = 0;
|
||||
let Inst{16-31} = B;
|
||||
}
|
||||
|
||||
// Currently we make the use/def reg distinction in ISel, not tablegen
|
||||
class DForm_3<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_1<name, opcode, ppc64, vmx>;
|
||||
class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_1<opcode, ppc64, vmx, OL, asmstr>;
|
||||
|
||||
class DForm_4<bits<6> opcode, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : DForm_base<"", opcode, ppc64, vmx> {
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : DForm_1<"", opcode, ppc64, vmx> {
|
||||
class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_base<opcode, ppc64, vmx, OL, asmstr>;
|
||||
|
||||
class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let ArgCount = 0;
|
||||
let Arg0Type = 0;
|
||||
let Arg1Type = 0;
|
||||
|
|
@ -162,12 +172,10 @@ class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx,
|
|||
let A = 0;
|
||||
let B = 0;
|
||||
let C = 0;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class DForm_5<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: I<name, opcode, ppc64, vmx> {
|
||||
class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<3> BF;
|
||||
field bits<1> L;
|
||||
field bits<5> RA;
|
||||
|
|
@ -187,8 +195,8 @@ class DForm_5<string name, bits<6> opcode, bit ppc64, bit vmx>
|
|||
let Inst{16-31} = I;
|
||||
}
|
||||
|
||||
class DForm_5_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_5<name, opcode, ppc64, vmx> {
|
||||
class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_5<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let L = ppc64;
|
||||
let ArgCount = 3;
|
||||
let Arg0Type = Imm3.Value;
|
||||
|
|
@ -197,15 +205,10 @@ class DForm_5_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
|
|||
let Arg3Type = 0;
|
||||
}
|
||||
|
||||
class DForm_6<bits<6> opcode, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr>
|
||||
: DForm_5<"", opcode, ppc64, vmx> {
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_5<opcode, ppc64, vmx, OL, asmstr>;
|
||||
|
||||
class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr>
|
||||
class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_6<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let L = ppc64;
|
||||
let ArgCount = 3;
|
||||
|
|
@ -215,24 +218,19 @@ class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx,
|
|||
let Arg3Type = 0;
|
||||
}
|
||||
|
||||
class DForm_7<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_base<name, opcode, ppc64, vmx> {
|
||||
let Arg1Type = Imm5.Value;
|
||||
}
|
||||
|
||||
class DForm_8<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_1<name, opcode, ppc64, vmx> {
|
||||
class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let Arg0Type = Fpr.Value;
|
||||
}
|
||||
|
||||
class DForm_9<string name, bits<6> opcode, bit ppc64, bit vmx>
|
||||
: DForm_1<name, opcode, ppc64, vmx> {
|
||||
class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
|
||||
: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let Arg0Type = Fpr.Value;
|
||||
}
|
||||
|
||||
// 1.7.5 DS-Form
|
||||
class DSForm_1<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx>
|
||||
: I<name, opcode, ppc64, vmx> {
|
||||
class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> RST;
|
||||
field bits<14> DS;
|
||||
field bits<5> RA;
|
||||
|
|
@ -250,12 +248,14 @@ class DSForm_1<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx>
|
|||
let Inst{30-31} = xo;
|
||||
}
|
||||
|
||||
class DSForm_2<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx>
|
||||
: DSForm_1<name, opcode, xo, ppc64, vmx>;
|
||||
class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr>
|
||||
: DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
|
||||
|
||||
// 1.7.6 X-Form
|
||||
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr>
|
||||
: I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> RST;
|
||||
field bits<5> A;
|
||||
field bits<5> B;
|
||||
|
|
@ -272,8 +272,6 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{16-20} = B;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -314,7 +312,7 @@ class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
|
|||
}
|
||||
|
||||
class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<3> BF;
|
||||
field bits<1> L;
|
||||
field bits<5> RA;
|
||||
|
|
@ -334,8 +332,6 @@ class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
|||
let Inst{16-20} = RB;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = 0;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
||||
|
|
@ -349,7 +345,7 @@ class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
|||
}
|
||||
|
||||
class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<3> BF;
|
||||
field bits<5> FRA;
|
||||
field bits<5> FRB;
|
||||
|
|
@ -367,8 +363,6 @@ class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
|||
let Inst{16-20} = FRB;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = 0;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
||||
|
|
@ -405,7 +399,7 @@ class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
|||
}
|
||||
|
||||
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> BO;
|
||||
field bits<5> BI;
|
||||
field bits<2> BH;
|
||||
|
|
@ -423,8 +417,6 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
|
|||
let Inst{19-20} = BH;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = lk;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
|
||||
|
|
@ -442,7 +434,7 @@ class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
|
|||
|
||||
// 1.7.8 XFX-Form
|
||||
class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> ST;
|
||||
field bits<10> SPR;
|
||||
|
||||
|
|
@ -457,8 +449,6 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
|
|||
let Inst{11-20} = SPR;
|
||||
let Inst{21-30} = xo;
|
||||
let Inst{31} = 0;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
|
||||
|
|
@ -485,7 +475,7 @@ class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
|
|||
|
||||
// 1.7.10 XS-Form
|
||||
class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> RS;
|
||||
field bits<5> A;
|
||||
field bits<6> SH;
|
||||
|
|
@ -503,13 +493,11 @@ class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{21-29} = xo;
|
||||
let Inst{30} = SH{0};
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
// 1.7.11 XO-Form
|
||||
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
field bits<5> RT;
|
||||
field bits<5> RA;
|
||||
field bits<5> RB;
|
||||
|
|
@ -527,8 +515,6 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{21} = oe;
|
||||
let Inst{22-30} = xo;
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
|
||||
|
|
@ -547,7 +533,7 @@ class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
|
|||
|
||||
// 1.7.12 A-Form
|
||||
class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let ArgCount = 4;
|
||||
field bits<5> FRT;
|
||||
field bits<5> FRA;
|
||||
|
|
@ -566,8 +552,6 @@ class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{21-25} = FRC;
|
||||
let Inst{26-30} = xo;
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class AForm_2<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
|
||||
|
|
@ -588,7 +572,7 @@ class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
|
|||
|
||||
// 1.7.13 M-Form
|
||||
class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let ArgCount = 5;
|
||||
field bits<5> RS;
|
||||
field bits<5> RA;
|
||||
|
|
@ -608,8 +592,6 @@ class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{21-25} = MB;
|
||||
let Inst{26-30} = ME;
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
|
||||
|
|
@ -620,7 +602,7 @@ class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
|
|||
|
||||
// 1.7.14 MD-Form
|
||||
class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
|
||||
dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
|
||||
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
|
||||
let ArgCount = 4;
|
||||
field bits<5> RS;
|
||||
field bits<5> RA;
|
||||
|
|
@ -640,13 +622,11 @@ class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
|
|||
let Inst{27-29} = xo;
|
||||
let Inst{30} = SH{0};
|
||||
let Inst{31} = rc;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class Pseudo<dag OL, string asmstr> : I<"", 0, 0, 0> {
|
||||
class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {
|
||||
let ArgCount = 0;
|
||||
let PPC64 = 0;
|
||||
let VMX = 0;
|
||||
|
|
@ -658,6 +638,4 @@ class Pseudo<dag OL, string asmstr> : I<"", 0, 0, 0> {
|
|||
let Arg4Type = 0;
|
||||
|
||||
let Inst{31-0} = 0;
|
||||
let OperandList = OL;
|
||||
let AsmString = asmstr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,6 +23,9 @@ def u5imm : Operand<i8> {
|
|||
def u6imm : Operand<i8> {
|
||||
let PrintMethod = "printU6ImmOperand";
|
||||
}
|
||||
def s16imm : Operand<i16> {
|
||||
let PrintMethod = "printS16ImmOperand";
|
||||
}
|
||||
def u16imm : Operand<i16> {
|
||||
let PrintMethod = "printU16ImmOperand";
|
||||
}
|
||||
|
|
@ -32,6 +35,12 @@ def target : Operand<i32> {
|
|||
def piclabel: Operand<i32> {
|
||||
let PrintMethod = "printPICLabel";
|
||||
}
|
||||
def symbolHi: Operand<i32> {
|
||||
let PrintMethod = "printSymbolHi";
|
||||
}
|
||||
def symbolLo: Operand<i32> {
|
||||
let PrintMethod = "printSymbolLo";
|
||||
}
|
||||
|
||||
// Pseudo-instructions:
|
||||
def PHI : Pseudo<(ops), "; PHI">;
|
||||
|
|
@ -45,12 +54,18 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
|
||||
// FIXME: 4*CR# needs to be added to the BI field!
|
||||
// This will only work for CR0 as it stands now
|
||||
def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
|
||||
def BLE : BForm_ext<"ble", 16, 0, 0, 4, 1, 0, 0>;
|
||||
def BEQ : BForm_ext<"beq", 16, 0, 0, 12, 2, 0, 0>;
|
||||
def BGE : BForm_ext<"bge", 16, 0, 0, 4, 0, 0, 0>;
|
||||
def BGT : BForm_ext<"bgt", 16, 0, 0, 12, 1, 0, 0>;
|
||||
def BNE : BForm_ext<"bne", 16, 0, 0, 4, 2, 0, 0>;
|
||||
def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"blt $block">;
|
||||
def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"ble $block">;
|
||||
def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"beq $block">;
|
||||
def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"bge $block">;
|
||||
def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"bgt $block">;
|
||||
def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
|
||||
"bne $block">;
|
||||
}
|
||||
|
||||
let isBranch = 1, isTerminator = 1, isCall = 1,
|
||||
|
|
@ -64,46 +79,55 @@ let isBranch = 1, isTerminator = 1, isCall = 1,
|
|||
def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">;
|
||||
}
|
||||
|
||||
def LA : DForm_2<"la", 14, 0, 0>;
|
||||
def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
|
||||
|
||||
def LBZ : DForm_1<"lbz", 35, 0, 0>;
|
||||
def LHA : DForm_1<"lha", 42, 0, 0>;
|
||||
def LHZ : DForm_1<"lhz", 40, 0, 0>;
|
||||
def LMW : DForm_1<"lmw", 46, 0, 0>;
|
||||
def LWZ : DForm_1<"lwz", 32, 0, 0>;
|
||||
def ADDI : DForm_2<"addi", 14, 0, 0>;
|
||||
def ADDIC : DForm_2<"addic", 12, 0, 0>;
|
||||
def ADDICo : DForm_2<"addic.", 13, 0, 0>;
|
||||
def ADDIS : DForm_2<"addis", 15, 0, 0>;
|
||||
def MULLI : DForm_2<"mulli", 7, 0, 0>;
|
||||
def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
|
||||
def SUBI : DForm_2<"subi", 14, 0, 0>;
|
||||
def LI : DForm_2_r0<"li", 14, 0, 0>;
|
||||
def LIS : DForm_2_r0<"lis", 15, 0, 0>;
|
||||
def STMW : DForm_3<"stmw", 47, 0, 0>;
|
||||
def STB : DForm_3<"stb", 38, 0, 0>;
|
||||
def STBU : DForm_3<"stbu", 39, 0, 0>;
|
||||
def STH : DForm_3<"sth", 44, 0, 0>;
|
||||
def STHU : DForm_3<"sthu", 45, 0, 0>;
|
||||
def STW : DForm_3<"stw", 36, 0, 0>;
|
||||
def STWU : DForm_3<"stwu", 37, 0, 0>;
|
||||
def CMPI : DForm_5<"cmpi", 11, 0, 0>;
|
||||
def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
|
||||
def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
|
||||
def LFS : DForm_8<"lfs", 48, 0, 0>;
|
||||
def LFD : DForm_8<"lfd", 50, 0, 0>;
|
||||
def STFS : DForm_9<"stfs", 52, 0, 0>;
|
||||
def STFD : DForm_9<"stfd", 54, 0, 0>;
|
||||
|
||||
def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
|
||||
def LD : DSForm_2<"ld", 58, 0, 1, 0>;
|
||||
def STD : DSForm_2<"std", 62, 0, 1, 0>;
|
||||
def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
|
||||
|
||||
// D-Form instructions. Most instructions that perform an operation on a
|
||||
// register and an immediate are of this type.
|
||||
//
|
||||
def LBZ : DForm_1<35, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lbz $rD, $disp($rA)">;
|
||||
def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lha $rD, $disp($rA)">;
|
||||
def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lhz $rD, $disp($rA)">;
|
||||
def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
|
||||
"lmw $rD, $disp($rA)">;
|
||||
def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lwz $rD, $disp($rA)">;
|
||||
def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addi $rD, $rA, $imm">;
|
||||
def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addic $rD, $rA, $imm">;
|
||||
def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addic. $rD, $rA, $imm">;
|
||||
def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"addis $rD, $rA, $imm">;
|
||||
def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, symbolLo:$sym, GPRC:$rA),
|
||||
"la $rD, $sym($rA)">;
|
||||
def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
|
||||
"addis $rD, $rA, $sym">;
|
||||
def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"mulli $rD, $rA, $imm">;
|
||||
def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"subfic $rD, $rA, $imm">;
|
||||
def SUBI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
|
||||
"subi $rD, $rA, $imm">;
|
||||
def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
|
||||
"li $rD, $imm">;
|
||||
def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
|
||||
"lis $rD, $imm">;
|
||||
def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stmw $rS, $disp($rA)">;
|
||||
def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stb $rS, $disp($rA)">;
|
||||
def STBU : DForm_3<39, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stbu $rS, $disp($rA)">;
|
||||
def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"sth $rS, $disp($rA)">;
|
||||
def STHU : DForm_3<45, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"sthu $rS, $disp($rA)">;
|
||||
def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stw $rS, $disp($rA)">;
|
||||
def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stwu $rS, $disp($rA)">;
|
||||
def ANDIo : DForm_4<28, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"andi. $dst, $src1, $src2">;
|
||||
|
|
@ -119,16 +143,42 @@ def XORI : DForm_4<26, 0, 0,
|
|||
def XORIS : DForm_4<27, 0, 0,
|
||||
(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"xoris $dst, $src1, $src2">;
|
||||
def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
|
||||
def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
|
||||
def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
|
||||
"cmpi $crD, $L, $rA, $imm">;
|
||||
def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
|
||||
"cmpwi $crD, $rA, $imm">;
|
||||
def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
|
||||
"cmpdi $crD, $rA, $imm">;
|
||||
def CMPLI : DForm_6<10, 0, 0,
|
||||
(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
|
||||
"cmpli $dst, $size, $src1, $src2">;
|
||||
(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
|
||||
"cmpli $dst, $size, $src1, $src2">;
|
||||
def CMPLWI : DForm_6_ext<10, 0, 0,
|
||||
(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"cmplwi $dst, $src1, $src2">;
|
||||
def CMPLDI : DForm_6_ext<10, 1, 0,
|
||||
(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
|
||||
"cmpldi $dst, $src1, $src2">;
|
||||
def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lfs $rD, $disp($rA)">;
|
||||
def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lfd $rD, $disp($rA)">;
|
||||
def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stfs $rS, $disp($rA)">;
|
||||
def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
|
||||
"stfd $rS, $disp($rA)">;
|
||||
|
||||
|
||||
// DS-Form instructions. Load/Store instructions available in PPC-64
|
||||
//
|
||||
def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"lwa $rT, $DS($rA)">;
|
||||
def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"ld $rT, $DS($rA)">;
|
||||
def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"std $rT, $DS($rA)">;
|
||||
def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"stdu $rT, $DS($rA)">;
|
||||
|
||||
// X-Form instructions. Most instructions that perform an operation on a
|
||||
// register and another register are of this type.
|
||||
|
|
|
|||
|
|
@ -105,9 +105,9 @@ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
|
|||
PM.add(createPPCBranchSelectionPass());
|
||||
|
||||
if (AIX)
|
||||
PM.add(createPPC64AsmPrinter(Out, *this));
|
||||
PM.add(createAIXAsmPrinter(Out, *this));
|
||||
else
|
||||
PM.add(createPPC32AsmPrinter(Out, *this));
|
||||
PM.add(createDarwinAsmPrinter(Out, *this));
|
||||
|
||||
PM.add(createMachineCodeDeleter());
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include "PowerPCJITInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include <set>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
|
|
@ -41,6 +42,11 @@ public:
|
|||
static unsigned getJITMatchQuality();
|
||||
|
||||
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
||||
|
||||
// Two shared sets between the instruction selector and the printer allow for
|
||||
// correct linkage on Darwin
|
||||
std::set<GlobalValue*> CalledFunctions;
|
||||
std::set<GlobalValue*> AddressTaken;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
TODO:
|
||||
* switch to auto-generated asm writer
|
||||
* implement not-R0 register GPR class
|
||||
* fix rlwimi generation to be use-and-def
|
||||
* implement scheduling info
|
||||
* implement powerpc-64 for darwin
|
||||
|
|
|
|||
Loading…
Reference in New Issue