forked from OSchip/llvm-project
parent
cb6f943ada
commit
4be00f8ad1
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@ -707,24 +707,26 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
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SDValue XCoreTargetLowering::
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LowerVAARG(SDValue Op, SelectionDAG &DAG) const
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{
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llvm_unreachable("unimplemented");
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// FIXME Arguments passed by reference need a extra dereference.
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// Whist llvm does not support aggregate varargs we can ignore
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// the possibility of the ValueType being an implicit byVal vararg.
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SDNode *Node = Op.getNode();
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EVT VT = Node->getValueType(0); // not an aggregate
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SDValue InChain = Node->getOperand(0);
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SDValue VAListPtr = Node->getOperand(1);
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EVT PtrVT = VAListPtr.getValueType();
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDLoc dl(Node);
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const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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EVT VT = Node->getValueType(0);
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SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
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Node->getOperand(1), MachinePointerInfo(V),
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SDValue VAList = DAG.getLoad(PtrVT, dl, InChain,
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VAListPtr, MachinePointerInfo(SV),
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false, false, false, 0);
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// Increment the pointer, VAList, to the next vararg
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SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
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DAG.getConstant(VT.getSizeInBits(),
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getPointerTy()));
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SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
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DAG.getIntPtrConstant(VT.getSizeInBits() / 8));
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// Store the incremented VAList to the legalized pointer
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Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
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MachinePointerInfo(V), false, false, 0);
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InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
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MachinePointerInfo(SV), false, false, 0);
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// Load the actual argument out of the pointer VAList
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return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
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return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
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false, false, false, 0);
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}
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@ -1,17 +0,0 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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define void @_Z1fz(...) {
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entry:
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; CHECK-LABEL: _Z1fz:
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; CHECK: extsp 3
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: ldaw sp, sp[3]
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; CHECK: retsp 0
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ret void
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}
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@ -0,0 +1,55 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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define void @_Z1fz(...) {
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entry:
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; CHECK-LABEL: _Z1fz:
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; CHECK: extsp 3
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: stw r[[REG:[0-3]{1,1}]]
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; CHECK: , sp{{\[}}[[REG]]{{\]}}
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; CHECK: ldaw sp, sp[3]
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; CHECK: retsp 0
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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declare void @f(i32) nounwind
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define void @test_vararg(...) nounwind {
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entry:
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; CHECK-LABEL: test_vararg
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; CHECK: extsp 6
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; CHECK: stw lr, sp[1]
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; CHECK: stw r0, sp[3]
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; CHECK: stw r1, sp[4]
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; CHECK: stw r2, sp[5]
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; CHECK: stw r3, sp[6]
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; CHECK: ldaw r0, sp[3]
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; CHECK: stw r0, sp[2]
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%list = alloca i8*, align 4
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%list1 = bitcast i8** %list to i8*
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call void @llvm.va_start(i8* %list1)
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br label %for.cond
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; CHECK-LABEL: .LBB1_1
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; CHECK: ldw r0, sp[2]
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; CHECK: add r1, r0, 4
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; CHECK: stw r1, sp[2]
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; CHECK: ldw r0, r0[0]
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; CHECK: bl f
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; CHECK: bu .LBB1_1
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for.cond:
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%0 = va_arg i8** %list, i32
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call void @f(i32 %0)
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br label %for.cond
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call void @llvm.va_end(i8* %list1)
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ret void
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}
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