forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select init_exec intrinsic
Change imm with timm in pattern for SI_INIT_EXEC_LO and remove regbank mappings for non register operands. Differential Revision: https://reviews.llvm.org/D82885
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@ -4230,8 +4230,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32);
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break;
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}
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case Intrinsic::amdgcn_end_cf:
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case Intrinsic::amdgcn_init_exec: {
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case Intrinsic::amdgcn_end_cf: {
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unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
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OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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@ -4287,7 +4286,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_init_exec_from_input: {
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unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
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OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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}
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case Intrinsic::amdgcn_ds_gws_init:
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@ -447,7 +447,7 @@ def SI_INIT_EXEC_FROM_INPUT : SPseudoInstSI <
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def : GCNPat <
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(int_amdgcn_init_exec timm:$src),
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(SI_INIT_EXEC_LO (as_i32imm imm:$src))> {
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(SI_INIT_EXEC_LO (as_i32timm timm:$src))> {
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let WaveSizePredicate = isWave32;
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}
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@ -1,2 +1,2 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll
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; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -global-isel -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll
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