forked from OSchip/llvm-project
[GlobalISel][InlineAsm] Add support for matching input constraints
Find def operand that corresponds to matching constraint and tie input to that operand. Differential Revision: https://reviews.llvm.org/D82651
This commit is contained in:
Petar Avramovic
parent
446b90135f
commit
4b980cc9ca
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@ -232,6 +232,11 @@ static void computeConstraintToUse(const TargetLowering *TLI,
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}
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}
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static unsigned getNumOpRegs(const MachineInstr &I, unsigned OpIdx) {
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unsigned Flag = I.getOperand(OpIdx).getImm();
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return InlineAsm::getNumOperandRegisters(Flag);
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}
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bool InlineAsmLowering::lowerInlineAsm(
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MachineIRBuilder &MIRBuilder, const CallBase &Call,
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std::function<ArrayRef<Register>(const Value &Val)> GetOrCreateVRegs)
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@ -317,6 +322,10 @@ bool InlineAsmLowering::lowerInlineAsm(
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.addExternalSymbol(IA->getAsmString().c_str())
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.addImm(ExtraInfo.get());
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// Starting from this operand: flag followed by register(s) will be added as
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// operands to Inst for each constraint. Used for matching input constraints.
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unsigned StartIdx = Inst->getNumOperands();
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// Collects the output operands for later processing
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GISelAsmOperandInfoVector OutputOperands;
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@ -390,8 +399,31 @@ bool InlineAsmLowering::lowerInlineAsm(
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break;
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case InlineAsm::isInput: {
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if (OpInfo.isMatchingInputConstraint()) {
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LLVM_DEBUG(dbgs() << "Tied input operands not supported yet\n");
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return false;
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unsigned DefIdx = OpInfo.getMatchedOperand();
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// Find operand with register def that corresponds to DefIdx.
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unsigned InstFlagIdx = StartIdx;
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for (unsigned i = 0; i < DefIdx; ++i)
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InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1;
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assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag");
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// We want to tie input to register in next operand.
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unsigned DefRegIdx = InstFlagIdx + 1;
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Register Def = Inst->getOperand(DefRegIdx).getReg();
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// Copy input to new vreg with same reg class as Def
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const TargetRegisterClass *RC = MRI->getRegClass(Def);
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ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
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assert(SrcRegs.size() == 1 && "Single register is expected here");
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Register Tmp = MRI->createVirtualRegister(RC);
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MIRBuilder.buildCopy(Tmp, SrcRegs[0]);
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// Add Flag and input register operand (Tmp) to Inst. Tie Tmp to Def.
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unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
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unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
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Inst.addImm(Flag);
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Inst.addReg(Tmp);
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Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1);
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break;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Other &&
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@ -0,0 +1,83 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -verify-machineinstrs -o - %s | FileCheck %s
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define i32 @test_sgpr_reg_class_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_reg_class_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s5, 8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_add_u32 s4, s4, s5
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
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%asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,s"(i32 %asm0, i32 %asm1) nounwind
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ret i32 %asm2
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}
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define i32 @test_sgpr_matching_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_matching_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s5, 8
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_add_u32 s5, s4, s5
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s5
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
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%asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind
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ret i32 %asm2
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}
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define i32 @test_sgpr_to_vgpr_move_reg_class_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_to_vgpr_move_reg_class_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32 v0, s4
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,s"(i32 %asm0) nounwind
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ret i32 %asm1
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}
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define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
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; CHECK-LABEL: test_sgpr_to_vgpr_move_matching_constraint:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 s4, 7
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32 v0, v0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind
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ret i32 %asm1
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}
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!0 = !{i32 70}
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@ -234,4 +234,96 @@ define i32 @test_memory_constraint(i32 addrspace(3)* %a) nounwind {
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ret i32 %1
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}
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define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {
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; CHECK-LABEL: name: test_vgpr_matching_constraint
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[AND]](s32)
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; CHECK: INLINEASM &";", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_32 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY2]](tied-def 3)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %4
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; CHECK: $vgpr0 = COPY [[COPY3]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%and = and i32 %a, 1
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%asm = call i32 asm sideeffect ";", "=v,0"(i32 %and)
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ret i32 %asm
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}
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define i32 @test_sgpr_matching_constraint() nounwind {
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; CHECK-LABEL: name: test_sgpr_matching_constraint
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; CHECK: bb.1.entry:
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %3
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %3
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; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY2]](s32)
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; CHECK: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %5, 9 /* reguse */, [[COPY3]], 2147483657 /* reguse tiedto:$0 */, [[COPY4]](tied-def 3)
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; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY %5
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; CHECK: $vgpr0 = COPY [[COPY5]](s32)
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; CHECK: [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY6]], implicit $vgpr0
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
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%asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind
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ret i32 %asm2
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}
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define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: name: test_many_matching_constraints
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
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; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)
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; CHECK: INLINEASM &"; ", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_32 */, def %4, 1835018 /* regdef:VGPR_32 */, def %5, 1835018 /* regdef:VGPR_32 */, def %6, 2147483657 /* reguse tiedto:$0 */, [[COPY4]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY5]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY6]](tied-def 5)
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; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY %4
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; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY %5
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; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY %6
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; CHECK: G_STORE [[COPY7]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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; CHECK: G_STORE [[COPY8]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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; CHECK: G_STORE [[COPY9]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
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; CHECK: S_SETPC_B64_return [[COPY10]]
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%asm = call {i32, i32, i32} asm sideeffect "; ", "=v,=v,=v,0,2,1"(i32 %c, i32 %a, i32 %b)
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%asmresult0 = extractvalue {i32, i32, i32} %asm, 0
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store i32 %asmresult0, i32 addrspace(1)* undef
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%asmresult1 = extractvalue {i32, i32, i32} %asm, 1
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store i32 %asmresult1, i32 addrspace(1)* undef
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%asmresult2 = extractvalue {i32, i32, i32} %asm, 2
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store i32 %asmresult2, i32 addrspace(1)* undef
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ret void
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}
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define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
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; CHECK-LABEL: name: test_sgpr_to_vgpr_move_matching_constraint
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; CHECK: bb.1.entry:
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; CHECK: liveins: $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)
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; CHECK: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %3, 2147483657 /* reguse tiedto:$0 */, [[COPY2]](tied-def 3)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %3
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; CHECK: $vgpr0 = COPY [[COPY3]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
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; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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entry:
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%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
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%asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind
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ret i32 %asm1
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}
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!0 = !{i32 70}
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