[llvm][MIRVRegNamer] Avoid collisions across constant pool indices.

When hashing on MachineOperand::MO_ConstantPoolIndex, now MIR-Canon and
MIRVRegNamer will no longer result in a hash collision.

Differential Revision: https://reviews.llvm.org/D74449

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

@@ -69,6 +69,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
     case MachineOperand::MO_TargetIndex:
       return MO.getOffset() | (MO.getTargetFlags() << 16);
     case MachineOperand::MO_FrameIndex:
+    case MachineOperand::MO_ConstantPoolIndex:
       return llvm::hash_value(MO);
 
     // We could explicitly handle all the types of the MachineOperand,
@@ -79,7 +80,6 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
 
     // TODO: Handle the following Index/ID/Predicate cases. They can
     // be hashed on in a stable manner.
-    case MachineOperand::MO_ConstantPoolIndex:
     case MachineOperand::MO_JumpTableIndex:
     case MachineOperand::MO_CFIIndex:
     case MachineOperand::MO_IntrinsicID:

llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir

@@ -0,0 +1,20 @@
+# RUN: llc -o - -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
+--- |
+  target triple = "aarch64-unknown-unknown"
+  define void @f() { unreachable }
+...
+---
+name: f
+constants:
+  - id:              0
+    value:           '<1 x i8> <i8 0>'
+  - id:              1
+    value:           '<1 x i8> <i8 1>'
+body: |
+  bb.0:
+    ; Test that we no longer have hash collisions between two different consts:
+    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
+    ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
+    %vreg0:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    %vreg1:gpr64common = ADRP target-flags(aarch64-page) %const.1
+...