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[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 

This is a (last big?) part of the patch series to make SimplifyCFG
preserve DomTree. Currently, it still does not actually preserve it,
even thought it is pretty much fully updated to preserve it.

Once the default is flipped, a valid DomTree must be passed into
simplifyCFG, which means that whatever pass calls simplifyCFG,
should also be smart about DomTree's.

As far as i can see from `check-llvm` with default flipped,
this is the last LLVM test batch (other than bugpoint tests)
that needed fixes to not break with default flipped.

The changes here are boringly identical to the ones i did
over 42+ times/commits recently already,
so while AMDGPU is outside of my normal ecosystem,
i'm going to go for post-commit review here,
like in all the other 42+ changes.

Note that while the pass is taught to preserve {,Post}DomTree,
it still doesn't do that by default, because simplifycfg
still doesn't do that by default, and flipping default
in this pass will implicitly flip the default for simplifycfg.
That will happen, but not right now.
This commit is contained in:
Roman Lebedev 2021-01-01 23:18:35 +03:00
parent b4429f3cdd
commit 4b80647367
No known key found for this signature in database
GPG Key ID: 083C3EBB4A1689E0
17 changed files with 80 additions and 36 deletions
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54
llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
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@ -25,17 +25,19 @@
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/DomTreeUpdater.h"
#include "llvm/Analysis/LegacyDivergenceAnalysis.h" #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/PostDominators.h"
#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/IR/BasicBlock.h" #include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CFG.h" #include "llvm/IR/CFG.h"
#include "llvm/IR/Constants.h" #include "llvm/IR/Constants.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InstrTypes.h" #include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/InitializePasses.h" #include "llvm/InitializePasses.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
@ -71,17 +73,25 @@ char &llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID;
INITIALIZE_PASS_BEGIN(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE, INITIALIZE_PASS_BEGIN(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
"Unify divergent function exit nodes", false, false) "Unify divergent function exit nodes", false, false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis) INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)
INITIALIZE_PASS_END(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE, INITIALIZE_PASS_END(AMDGPUUnifyDivergentExitNodes, DEBUG_TYPE,
"Unify divergent function exit nodes", false, false) "Unify divergent function exit nodes", false, false)
void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const{ void AMDGPUUnifyDivergentExitNodes::getAnalysisUsage(AnalysisUsage &AU) const{
// TODO: Preserve dominator tree. if (RequireAndPreserveDomTree)
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<PostDominatorTreeWrapperPass>(); AU.addRequired<PostDominatorTreeWrapperPass>();
AU.addRequired<LegacyDivergenceAnalysis>(); AU.addRequired<LegacyDivergenceAnalysis>();
if (RequireAndPreserveDomTree) {
AU.addPreserved<DominatorTreeWrapperPass>();
AU.addPreserved<PostDominatorTreeWrapperPass>();
}
// No divergent values are changed, only blocks and branch edges. // No divergent values are changed, only blocks and branch edges.
AU.addPreserved<LegacyDivergenceAnalysis>(); AU.addPreserved<LegacyDivergenceAnalysis>();
@ -134,7 +144,7 @@ static void removeDoneExport(Function &F) {
} }
} }
static BasicBlock *unifyReturnBlockSet(Function &F, static BasicBlock *unifyReturnBlockSet(Function &F, DomTreeUpdater &DTU,
ArrayRef<BasicBlock *> ReturningBlocks, ArrayRef<BasicBlock *> ReturningBlocks,
bool InsertExport, bool InsertExport,
const TargetTransformInfo &TTI, const TargetTransformInfo &TTI,
@ -175,6 +185,8 @@ static BasicBlock *unifyReturnBlockSet(Function &F,
// Loop over all of the blocks, replacing the return instruction with an // Loop over all of the blocks, replacing the return instruction with an
// unconditional branch. // unconditional branch.
std::vector<DominatorTree::UpdateType> Updates;
Updates.reserve(ReturningBlocks.size());
for (BasicBlock *BB : ReturningBlocks) { for (BasicBlock *BB : ReturningBlocks) {
// Add an incoming element to the PHI node for every return instruction that // Add an incoming element to the PHI node for every return instruction that
// is merging into this new block... // is merging into this new block...
@ -184,11 +196,16 @@ static BasicBlock *unifyReturnBlockSet(Function &F,
// Remove and delete the return inst. // Remove and delete the return inst.
BB->getTerminator()->eraseFromParent(); BB->getTerminator()->eraseFromParent();
BranchInst::Create(NewRetBlock, BB); BranchInst::Create(NewRetBlock, BB);
Updates.push_back({DominatorTree::Insert, BB, NewRetBlock});
} }
if (RequireAndPreserveDomTree)
DTU.applyUpdates(Updates);
Updates.clear();
for (BasicBlock *BB : ReturningBlocks) { for (BasicBlock *BB : ReturningBlocks) {
// Cleanup possible branch to unconditional branch to the return. // Cleanup possible branch to unconditional branch to the return.
simplifyCFG(BB, TTI, /*DTU=*/nullptr, simplifyCFG(BB, TTI, RequireAndPreserveDomTree ? &DTU : nullptr,
SimplifyCFGOptions().bonusInstThreshold(2)); SimplifyCFGOptions().bonusInstThreshold(2));
} }
@ -196,6 +213,10 @@ static BasicBlock *unifyReturnBlockSet(Function &F,
} }
bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) { bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
DominatorTree *DT = nullptr;
if (RequireAndPreserveDomTree)
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
auto &PDT = getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree(); auto &PDT = getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree();
// If there's only one exit, we don't need to do anything, unless this is a // If there's only one exit, we don't need to do anything, unless this is a
@ -218,6 +239,8 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
bool InsertExport = false; bool InsertExport = false;
bool Changed = false; bool Changed = false;
std::vector<DominatorTree::UpdateType> Updates;
for (BasicBlock *BB : PDT.roots()) { for (BasicBlock *BB : PDT.roots()) {
if (isa<ReturnInst>(BB->getTerminator())) { if (isa<ReturnInst>(BB->getTerminator())) {
if (!isUniformlyReached(DA, *BB)) if (!isUniformlyReached(DA, *BB))
@ -274,14 +297,28 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
BI->eraseFromParent(); // Delete the unconditional branch. BI->eraseFromParent(); // Delete the unconditional branch.
// Add a new conditional branch with a dummy edge to the return block. // Add a new conditional branch with a dummy edge to the return block.
BranchInst::Create(LoopHeaderBB, DummyReturnBB, BoolTrue, BB); BranchInst::Create(LoopHeaderBB, DummyReturnBB, BoolTrue, BB);
Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
} else { // Conditional branch. } else { // Conditional branch.
SmallVector<BasicBlock *, 2> Successors(succ_begin(BB), succ_end(BB));
// Create a new transition block to hold the conditional branch. // Create a new transition block to hold the conditional branch.
BasicBlock *TransitionBB = BB->splitBasicBlock(BI, "TransitionBlock"); BasicBlock *TransitionBB = BB->splitBasicBlock(BI, "TransitionBlock");
Updates.reserve(Updates.size() + 2 * Successors.size() + 2);
// 'Successors' become successors of TransitionBB instead of BB,
// and TransitionBB becomes a single successor of BB.
Updates.push_back({DominatorTree::Insert, BB, TransitionBB});
for (BasicBlock *Successor : Successors) {
Updates.push_back({DominatorTree::Insert, TransitionBB, Successor});
Updates.push_back({DominatorTree::Delete, BB, Successor});
}
// Create a branch that will always branch to the transition block and // Create a branch that will always branch to the transition block and
// references DummyReturnBB. // references DummyReturnBB.
BB->getTerminator()->eraseFromParent(); BB->getTerminator()->eraseFromParent();
BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB); BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB);
Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
} }
Changed = true; Changed = true;
} }
@ -297,10 +334,12 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
"UnifiedUnreachableBlock", &F); "UnifiedUnreachableBlock", &F);
new UnreachableInst(F.getContext(), UnreachableBlock); new UnreachableInst(F.getContext(), UnreachableBlock);
Updates.reserve(Updates.size() + UnreachableBlocks.size());
for (BasicBlock *BB : UnreachableBlocks) { for (BasicBlock *BB : UnreachableBlocks) {
// Remove and delete the unreachable inst. // Remove and delete the unreachable inst.
BB->getTerminator()->eraseFromParent(); BB->getTerminator()->eraseFromParent();
BranchInst::Create(UnreachableBlock, BB); BranchInst::Create(UnreachableBlock, BB);
Updates.push_back({DominatorTree::Insert, BB, UnreachableBlock});
} }
Changed = true; Changed = true;
} }
@ -330,6 +369,11 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
} }
} }
DomTreeUpdater DTU(DT, &PDT, DomTreeUpdater::UpdateStrategy::Eager);
if (RequireAndPreserveDomTree)
DTU.applyUpdates(Updates);
Updates.clear();
// Now handle return blocks. // Now handle return blocks.
if (ReturningBlocks.empty()) if (ReturningBlocks.empty())
return Changed; // No blocks return return Changed; // No blocks return
@ -351,7 +395,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
UniformlyReachedRetBlocks.end()); UniformlyReachedRetBlocks.end());
} }
unifyReturnBlockSet(F, BlocksToUnify, InsertExport, TTI, unifyReturnBlockSet(F, DTU, BlocksToUnify, InsertExport, TTI,
"UnifiedReturnBlock"); "UnifiedReturnBlock");
return true; return true;
} }

10
llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
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@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-- -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX7 %s ; RUN: llc -mtriple=amdgcn-- -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s
declare i1 @llvm.amdgcn.wqm.vote(i1) declare i1 @llvm.amdgcn.wqm.vote(i1)
declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32 immarg) declare i32 @llvm.amdgcn.raw.buffer.atomic.add(i32, <4 x i32>, i32, i32, i32 immarg)

4
llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; This used to crash because during intermediate control flow lowering, there ; This used to crash because during intermediate control flow lowering, there
; was a sequence ; was a sequence

4
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
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@ -1,9 +1,9 @@
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; FIXME: We should use llvm-mc for this, but we can't even parse our own output. ; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
; See PR33579. ; See PR33579.
; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=0 %s ; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=1 %s
; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
; OBJ: Relocations [ ; OBJ: Relocations [

4
llvm/test/CodeGen/AMDGPU/infinite-loop.ll
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@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=0 %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop: ; SI-LABEL: infinite_loop:

2
llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -enable-var-scope %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s
; Although it's modeled without any control flow in order to get better code ; Although it's modeled without any control flow in order to get better code
; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls ; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls

2
llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
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@ -1,4 +1,4 @@
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX10 %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; GCN-LABEL: _amdgpu_hs_main: ; GCN-LABEL: _amdgpu_hs_main:

4
llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
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@ -1,5 +1,5 @@
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=0 %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; Add an extra verifier runs. There were some cases where invalid IR ; Add an extra verifier runs. There were some cases where invalid IR
; was produced but happened to be fixed by the later passes. ; was produced but happened to be fixed by the later passes.

4
llvm/test/CodeGen/AMDGPU/ret_jump.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; This should end with an no-op sequence of exec mask manipulations ; This should end with an no-op sequence of exec mask manipulations
; Mask should be in original state after executed unreachable block ; Mask should be in original state after executed unreachable block

4
llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
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@ -1,5 +1,5 @@
; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=0 %s | FileCheck -check-prefix=OPT %s ; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=OPT %s
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; OPT-LABEL: @annotate_unreachable_noloop( ; OPT-LABEL: @annotate_unreachable_noloop(

2
llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
; GCN: v_cmp_eq_u32 ; GCN: v_cmp_eq_u32

2
llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos:
; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: ; %bb.0:

2
llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
; ;
; This test used to crash with the following assertion: ; This test used to crash with the following assertion:
; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed. ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.

4
llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
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@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amdhsa -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn-amdhsa -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: opt -S -si-annotate-control-flow -mtriple=amdgcn-amdhsa -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=SI-OPT %s ; RUN: opt -S -si-annotate-control-flow -mtriple=amdgcn-amdhsa -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI-OPT %s
define hidden void @widget() { define hidden void @widget() {
; GCN-LABEL: widget: ; GCN-LABEL: widget:

2
llvm/test/CodeGen/AMDGPU/update-phi.ll
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@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=0 %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
; Make sure that the phi in n28 is updated when the block is split by unify ; Make sure that the phi in n28 is updated when the block is split by unify
; divergent exit nodes. ; divergent exit nodes.

2
llvm/test/CodeGen/AMDGPU/valu-i1.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone

10
llvm/test/CodeGen/AMDGPU/wave32.ll
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@ -1,8 +1,8 @@
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=0 < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s
; GCN-LABEL: {{^}}test_vopc_i32: ; GCN-LABEL: {{^}}test_vopc_i32:
; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}} ; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}}