forked from OSchip/llvm-project
[WebAssembly] Prototype i8x16 to i32x4 widening instructions
As proposed in https://github.com/WebAssembly/simd/pull/395 and matching the opcodes used in V8: https://chromium-review.googlesource.com/c/v8/v8/+/2617385/4/src/wasm/wasm-opcodes.h Differential Revision: https://reviews.llvm.org/D95557
This commit is contained in:
Thomas Lively
parent
acaf85f700
commit
4b68b64dcc
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@ -206,6 +206,9 @@ TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd1
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TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_widen_s_i8x16_i32x4, "V4iV16ScIi", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_widen_u_i8x16_i32x4, "V4UiV16UcIi", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
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@ -17220,6 +17220,24 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
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Function *Callee = CGM.getIntrinsic(IntNo);
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return Builder.CreateCall(Callee, Vec);
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}
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case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
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case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4: {
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Value *Vec = EmitScalarExpr(E->getArg(0));
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llvm::APSInt SubVecConst =
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*E->getArg(1)->getIntegerConstantExpr(getContext());
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Value *SubVec = llvm::ConstantInt::get(getLLVMContext(), SubVecConst);
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unsigned IntNo;
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switch (BuiltinID) {
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case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
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IntNo = Intrinsic::wasm_widen_signed;
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break;
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case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4:
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IntNo = Intrinsic::wasm_widen_unsigned;
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break;
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}
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Function *Callee = CGM.getIntrinsic(IntNo);
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return Builder.CreateCall(Callee, {Vec, SubVec});
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}
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case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
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case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
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Value *Vec = EmitScalarExpr(E->getArg(0));
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@ -976,6 +976,18 @@ u64x2 widen_high_u_i32x4_i64x2(u32x4 x) {
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// WEBASSEMBLY: ret
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}
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i32x4 widen_s_i8x16_i32x4(i8x16 x) {
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return __builtin_wasm_widen_s_i8x16_i32x4(x, 3);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 3)
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// WEBASSEMBLY: ret
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}
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u32x4 widen_u_i8x16_i32x4(u8x16 x) {
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return __builtin_wasm_widen_u_i8x16_i32x4(x, 3);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 3)
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// WEBASSEMBLY: ret
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}
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f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
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return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
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// WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
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@ -348,6 +348,14 @@ def int_wasm_promote_low :
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Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Remove these if possible if they are merged to the spec.
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def int_wasm_widen_signed :
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Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
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def int_wasm_widen_unsigned :
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Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
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//===----------------------------------------------------------------------===//
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// Thread-local storage intrinsics
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//===----------------------------------------------------------------------===//
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@ -1256,7 +1256,6 @@ defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed,
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defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
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"extadd_pairwise_i16x8_u", 0xa6>;
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// Prototype f64x2 conversions
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defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
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"convert_low_i32x4_s", 0x53>;
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@ -1271,6 +1270,25 @@ defm "" : SIMDConvert<F32x4, F64x2, int_wasm_demote_zero,
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defm "" : SIMDConvert<F64x2, F32x4, int_wasm_promote_low,
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"promote_low_f32x4", 0x69>;
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// Prototype i8x16 to i32x4 widening
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defm WIDEN_I8x16_TO_I32x4_S :
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SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
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(outs), (ins vec_i8imm_op:$idx),
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[(set (I32x4.vt V128:$dst),
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(I32x4.vt (int_wasm_widen_signed
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(I8x16.vt V128:$vec), (i32 timm:$idx))))],
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"i32x4.widen_i8x16_s\t$dst, $vec, $idx",
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"i32x4.widen_i8x16_s\t$idx", 0x67>;
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defm WIDEN_I8x16_TO_I32x4_U :
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SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
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(outs), (ins vec_i8imm_op:$idx),
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[(set (I32x4.vt V128:$dst),
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(I32x4.vt (int_wasm_widen_unsigned
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(I8x16.vt V128:$vec), (i32 timm:$idx))))],
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"i32x4.widen_i8x16_u\t$dst, $vec, $idx",
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"i32x4.widen_i8x16_u\t$idx", 0x68>;
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//===----------------------------------------------------------------------===//
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// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
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//===----------------------------------------------------------------------===//
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@ -586,6 +586,27 @@ define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
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ret <4 x i32> %v
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}
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; CHECK-LABEL: widen_signed_v4i32:
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; SIMD128-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <4 x i32> @llvm.wasm.widen.signed(<16 x i8>, i32 immarg)
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define <4 x i32> @widen_signed_v4i32(<16 x i8> %x) {
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%v = call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 1)
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ret <4 x i32> %v
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}
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; CHECK-LABEL: widen_unsigned_v4i32:
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; SIMD128-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8>, i32 immarg)
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define <4 x i32> @widen_unsigned_v4i32(<16 x i8> %x) {
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%v = call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 1)
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ret <4 x i32> %v
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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@ -760,4 +760,10 @@ main:
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# CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x69]
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f64x2.promote_low_f32x4
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# CHECK: i32x4.widen_i8x16_s 3 # encoding: [0xfd,0x67,0x03]
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i32x4.widen_i8x16_s 3
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# CHECK: i32x4.widen_i8x16_u 3 # encoding: [0xfd,0x68,0x03]
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i32x4.widen_i8x16_u 3
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end_function
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