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AMDGPU: Remove custom getSubReg 

This was kind of confusing, the subregister
class shouldn't really be necessary.

llvm-svn: 278362
This commit is contained in:
Matt Arsenault 2016-08-11 17:15:32 +00:00
parent 69fd2c1179
commit 4b5fc093d0
2 changed files with 10 additions and 78 deletions
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82
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -461,9 +461,8 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
}
for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
unsigned SubReg = NumSubRegs > 1 ?
getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
Value;
unsigned SubReg = NumSubRegs == 1 ?
Value : getSubReg(Value, getSubRegFromChannel(i));
unsigned SOffsetRegState = 0;
unsigned SrcDstRegState = getDefRegState(!IsStore);
@ -522,8 +521,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// SubReg carries the "Kill" flag when SubReg == SuperReg.
unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned SubReg = getPhysRegSubReg(SuperReg,
&AMDGPU::SGPR_32RegClass, i);
unsigned SubReg = NumSubRegs == 1 ?
SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);
@ -585,12 +584,14 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_S32_RESTORE: {
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SuperReg = MI->getOperand(0).getReg();
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
&AMDGPU::SGPR_32RegClass, i);
struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);
unsigned SubReg = NumSubRegs == 1 ?
SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
SIMachineFunctionInfo::SpilledReg Spill
= MFI->getSpilledReg(MF, Index, i);
if (Spill.hasReg()) {
BuildMI(*MBB, MI, DL,
@ -828,69 +829,6 @@ bool SIRegisterInfo::shouldRewriteCopySrc(
return getCommonSubClass(DefRC, SrcRC) != nullptr;
}
unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
const TargetRegisterClass *SubRC,
unsigned Channel) const {
switch (Reg) {
case AMDGPU::VCC:
switch(Channel) {
case 0: return AMDGPU::VCC_LO;
case 1: return AMDGPU::VCC_HI;
default: llvm_unreachable("Invalid SubIdx for VCC"); break;
}
case AMDGPU::TBA:
switch(Channel) {
case 0: return AMDGPU::TBA_LO;
case 1: return AMDGPU::TBA_HI;
default: llvm_unreachable("Invalid SubIdx for TBA"); break;
}
case AMDGPU::TMA:
switch(Channel) {
case 0: return AMDGPU::TMA_LO;
case 1: return AMDGPU::TMA_HI;
default: llvm_unreachable("Invalid SubIdx for TMA"); break;
}
case AMDGPU::FLAT_SCR:
switch (Channel) {
case 0:
return AMDGPU::FLAT_SCR_LO;
case 1:
return AMDGPU::FLAT_SCR_HI;
default:
llvm_unreachable("Invalid SubIdx for FLAT_SCR");
}
break;
case AMDGPU::EXEC:
switch (Channel) {
case 0:
return AMDGPU::EXEC_LO;
case 1:
return AMDGPU::EXEC_HI;
default:
llvm_unreachable("Invalid SubIdx for EXEC");
}
break;
}
const TargetRegisterClass *RC = getPhysRegClass(Reg);
// 32-bit registers don't have sub-registers, so we can just return the
// Reg. We need to have this check here, because the calculation below
// using getHWRegIndex() will fail with special 32-bit registers like
// VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
if (RC->getSize() == 4) {
assert(Channel == 0);
return Reg;
}
unsigned Index = getHWRegIndex(Reg);
return SubRC->getRegister(Index + Channel);
}
bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
return OpType == AMDGPU::OPERAND_REG_IMM32;
}

6
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
View File

@ -137,12 +137,6 @@ public:
const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const override;
/// \p Channel This is the register channel (e.g. a value from 0-16), not the
/// SubReg index.
/// \returns The sub-register of Reg that is in Channel.
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
unsigned Channel) const;
/// \returns True if operands defined with this operand type can accept
/// a literal constant (i.e. any 32-bit immediate).
bool opCanUseLiteralConstant(unsigned OpType) const;