forked from OSchip/llvm-project
[MIPS GlobalISel] Select floating point to integer conversions
Select G_FPTOSI and G_FPTOUI for MIPS32. Differential Revision: https://reviews.llvm.org/D63541 llvm-svn: 363911
This commit is contained in:
Petar Avramovic
parent
0de98ebd00
commit
4b4dae1c76
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@ -420,10 +420,11 @@ LegalizerHelper::libcall(MachineInstr &MI) {
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// FIXME: Support other types
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unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
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if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
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return UnableToLegalize;
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LegalizeResult Status = conversionLibcall(
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MI, MIRBuilder, Type::getInt32Ty(Ctx),
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MI, MIRBuilder,
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ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
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FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
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if (Status != Legalized)
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return Status;
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@ -367,6 +367,34 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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.add(I.getOperand(1));
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break;
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}
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case G_FPTOSI: {
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unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
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unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
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assert((ToSize == 32) && "Unsupported integer size for G_FPTOSI");
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assert((FromSize == 32 || FromSize == 64) &&
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"Unsupported floating point size for G_FPTOSI");
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unsigned Opcode;
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if (FromSize == 32)
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Opcode = Mips::TRUNC_W_S;
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else
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Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
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unsigned ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
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MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
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.addDef(ResultInFPR)
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.addUse(I.getOperand(1).getReg());
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if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
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return false;
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MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
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.addDef(I.getOperand(0).getReg())
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.addUse(ResultInFPR);
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if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_GLOBAL_VALUE: {
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const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
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if (MF.getTarget().isPositionIndependent()) {
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@ -110,6 +110,16 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_FPTRUNC)
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.legalFor({{s32, s64}});
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// FP to int conversion instructions
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getActionDefinitionsBuilder(G_FPTOSI)
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.legalForCartesianProduct({s32}, {s64, s32})
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.libcallForCartesianProduct({s64}, {s64, s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_FPTOUI)
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.libcallForCartesianProduct({s64}, {s64, s32})
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.minScalar(0, s32);
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computeTables();
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verify(*ST.getInstrInfo());
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}
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@ -170,6 +170,18 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
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&Mips::ValueMappings[Mips::DPRIdx]});
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break;
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case G_FPTOSI: {
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unsigned SizeInt = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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assert((SizeInt == 32) && "Unsupported integer size");
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assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
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OperandsMapping = getOperandsMapping({
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&Mips::ValueMappings[Mips::GPRIdx],
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SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
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: &Mips::ValueMappings[Mips::DPRIdx],
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});
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break;
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}
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_GLOBAL_VALUE:
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@ -0,0 +1,69 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @f32toi32() {entry: ret void}
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define void @f64toi32() {entry: ret void}
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...
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---
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name: f32toi32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: f32toi32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
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; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
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; FP32: $v0 = COPY [[MFC1_]]
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; FP32: RetRA implicit $v0
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; FP64-LABEL: name: f32toi32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
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; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
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; FP64: $v0 = COPY [[MFC1_]]
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; FP64: RetRA implicit $v0
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%0:fprb(s32) = COPY $f12
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%1:gprb(s32) = G_FPTOSI %0(s32)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: f64toi32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: f64toi32
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[TRUNC_W_D32_:%[0-9]+]]:fgr32 = TRUNC_W_D32 [[COPY]]
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; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D32_]]
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; FP32: $v0 = COPY [[MFC1_]]
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; FP32: RetRA implicit $v0
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; FP64-LABEL: name: f64toi32
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[TRUNC_W_D64_:%[0-9]+]]:fgr32 = TRUNC_W_D64 [[COPY]]
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; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D64_]]
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; FP64: $v0 = COPY [[MFC1_]]
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; FP64: RetRA implicit $v0
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%0:fprb(s64) = COPY $d6
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%1:gprb(s32) = G_FPTOSI %0(s64)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,369 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @f32toi64() {entry: ret void}
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define void @f32toi32() {entry: ret void}
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define void @f32toi16() {entry: ret void}
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define void @f32toi8() {entry: ret void}
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define void @f64toi64() {entry: ret void}
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define void @f64toi32() {entry: ret void}
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define void @f64toi16() {entry: ret void}
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define void @f64toi8() {entry: ret void}
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define void @f32tou64() {entry: ret void}
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define void @f64tou64() {entry: ret void}
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...
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---
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name: f32toi64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: f32toi64
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP32: $f12 = COPY [[COPY]](s32)
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; FP32: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
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; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
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; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP32: $v0 = COPY [[COPY1]](s32)
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; FP32: $v1 = COPY [[COPY2]](s32)
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; FP32: RetRA implicit $v0, implicit $v1
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; FP64-LABEL: name: f32toi64
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP64: $f12 = COPY [[COPY]](s32)
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; FP64: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
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; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
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; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP64: $v0 = COPY [[COPY1]](s32)
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; FP64: $v1 = COPY [[COPY2]](s32)
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; FP64: RetRA implicit $v0, implicit $v1
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%0:_(s32) = COPY $f12
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%1:_(s64) = G_FPTOSI %0(s32)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: f32toi32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: f32toi32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP32: $v0 = COPY [[FPTOSI]](s32)
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; FP32: RetRA implicit $v0
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; FP64-LABEL: name: f32toi32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP64: $v0 = COPY [[FPTOSI]](s32)
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; FP64: RetRA implicit $v0
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%0:_(s32) = COPY $f12
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%1:_(s32) = G_FPTOSI %0(s32)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: f32toi16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: f32toi16
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; FP32: $v0 = COPY [[ASHR]](s32)
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; FP32: RetRA implicit $v0
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; FP64-LABEL: name: f32toi16
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; FP64: $v0 = COPY [[ASHR]](s32)
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; FP64: RetRA implicit $v0
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%0:_(s32) = COPY $f12
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%1:_(s16) = G_FPTOSI %0(s32)
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%2:_(s32) = G_SEXT %1(s16)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: f32toi8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: f32toi8
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; FP32: $v0 = COPY [[ASHR]](s32)
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; FP32: RetRA implicit $v0
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; FP64-LABEL: name: f32toi8
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; FP64: $v0 = COPY [[ASHR]](s32)
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; FP64: RetRA implicit $v0
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%0:_(s32) = COPY $f12
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%1:_(s8) = G_FPTOSI %0(s32)
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%2:_(s32) = G_SEXT %1(s8)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: f64toi64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: f64toi64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP32: $d6 = COPY [[COPY]](s64)
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; FP32: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
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; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
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; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP32: $v0 = COPY [[COPY1]](s32)
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; FP32: $v1 = COPY [[COPY2]](s32)
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; FP32: RetRA implicit $v0, implicit $v1
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; FP64-LABEL: name: f64toi64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; FP64: $d12_64 = COPY [[COPY]](s64)
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; FP64: JAL &__fixdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
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; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
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; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; FP64: $v0 = COPY [[COPY1]](s32)
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; FP64: $v1 = COPY [[COPY2]](s32)
|
||||
; FP64: RetRA implicit $v0, implicit $v1
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = G_FPTOSI %0(s64)
|
||||
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
|
||||
$v0 = COPY %2(s32)
|
||||
$v1 = COPY %3(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
---
|
||||
name: f64toi32
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6
|
||||
|
||||
; FP32-LABEL: name: f64toi32
|
||||
; FP32: liveins: $d6
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP32: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP32: RetRA implicit $v0
|
||||
; FP64-LABEL: name: f64toi32
|
||||
; FP64: liveins: $d6
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP64: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP64: RetRA implicit $v0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s32) = G_FPTOSI %0(s64)
|
||||
$v0 = COPY %1(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: f64toi16
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6
|
||||
|
||||
; FP32-LABEL: name: f64toi16
|
||||
; FP32: liveins: $d6
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
|
||||
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
|
||||
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; FP32: $v0 = COPY [[ASHR]](s32)
|
||||
; FP32: RetRA implicit $v0
|
||||
; FP64-LABEL: name: f64toi16
|
||||
; FP64: liveins: $d6
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
|
||||
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
|
||||
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; FP64: $v0 = COPY [[ASHR]](s32)
|
||||
; FP64: RetRA implicit $v0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s16) = G_FPTOSI %0(s64)
|
||||
%2:_(s32) = G_SEXT %1(s16)
|
||||
$v0 = COPY %2(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: f64toi8
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6
|
||||
|
||||
; FP32-LABEL: name: f64toi8
|
||||
; FP32: liveins: $d6
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
|
||||
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
|
||||
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; FP32: $v0 = COPY [[ASHR]](s32)
|
||||
; FP32: RetRA implicit $v0
|
||||
; FP64-LABEL: name: f64toi8
|
||||
; FP64: liveins: $d6
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
|
||||
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
|
||||
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; FP64: $v0 = COPY [[ASHR]](s32)
|
||||
; FP64: RetRA implicit $v0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s8) = G_FPTOSI %0(s64)
|
||||
%2:_(s32) = G_SEXT %1(s8)
|
||||
$v0 = COPY %2(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: f32tou64
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; FP32-LABEL: name: f32tou64
|
||||
; FP32: liveins: $f12
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $f12 = COPY [[COPY]](s32)
|
||||
; FP32: JAL &__fixunssfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
|
||||
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
|
||||
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $v0 = COPY [[COPY1]](s32)
|
||||
; FP32: $v1 = COPY [[COPY2]](s32)
|
||||
; FP32: RetRA implicit $v0, implicit $v1
|
||||
; FP64-LABEL: name: f32tou64
|
||||
; FP64: liveins: $f12
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
|
||||
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $f12 = COPY [[COPY]](s32)
|
||||
; FP64: JAL &__fixunssfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
|
||||
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
|
||||
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $v0 = COPY [[COPY1]](s32)
|
||||
; FP64: $v1 = COPY [[COPY2]](s32)
|
||||
; FP64: RetRA implicit $v0, implicit $v1
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s64) = G_FPTOUI %0(s32)
|
||||
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
|
||||
$v0 = COPY %2(s32)
|
||||
$v1 = COPY %3(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
---
|
||||
name: f64tou64
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6
|
||||
|
||||
; FP32-LABEL: name: f64tou64
|
||||
; FP32: liveins: $d6
|
||||
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $d6 = COPY [[COPY]](s64)
|
||||
; FP32: JAL &__fixunsdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
|
||||
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
|
||||
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
|
||||
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP32: $v0 = COPY [[COPY1]](s32)
|
||||
; FP32: $v1 = COPY [[COPY2]](s32)
|
||||
; FP32: RetRA implicit $v0, implicit $v1
|
||||
; FP64-LABEL: name: f64tou64
|
||||
; FP64: liveins: $d6
|
||||
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
|
||||
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $d12_64 = COPY [[COPY]](s64)
|
||||
; FP64: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
|
||||
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
|
||||
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
|
||||
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||||
; FP64: $v0 = COPY [[COPY1]](s32)
|
||||
; FP64: $v1 = COPY [[COPY2]](s32)
|
||||
; FP64: RetRA implicit $v0, implicit $v1
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s64) = G_FPTOUI %0(s64)
|
||||
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
|
||||
$v0 = COPY %2(s32)
|
||||
$v1 = COPY %3(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
|
||||
|
||||
define i64 @f32toi64(float %a) {
|
||||
; MIPS32-LABEL: f32toi64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: .cfi_offset 31, -4
|
||||
; MIPS32-NEXT: jal __fixsfdi
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi float %a to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
define i32 @f32toi32(float %a) {
|
||||
; MIPS32-LABEL: f32toi32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.s $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $2, $f0
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi float %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define signext i16 @f32toi16(float %a) {
|
||||
; MIPS32-LABEL: f32toi16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.s $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $1, $f0
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi float %a to i16
|
||||
ret i16 %conv
|
||||
}
|
||||
|
||||
define signext i8 @f32toi8(float %a) {
|
||||
; MIPS32-LABEL: f32toi8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.s $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $1, $f0
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi float %a to i8
|
||||
ret i8 %conv
|
||||
}
|
||||
|
||||
define i64 @f64toi64(double %a) {
|
||||
; MIPS32-LABEL: f64toi64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: .cfi_offset 31, -4
|
||||
; MIPS32-NEXT: jal __fixdfdi
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi double %a to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
define i32 @f64toi32(double %a) {
|
||||
; MIPS32-LABEL: f64toi32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.d $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $2, $f0
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi double %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define signext i16 @f64toi16(double %a) {
|
||||
; MIPS32-LABEL: f64toi16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.d $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $1, $f0
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi double %a to i16
|
||||
ret i16 %conv
|
||||
}
|
||||
|
||||
define signext i8 @f64toi8(double %a) {
|
||||
; MIPS32-LABEL: f64toi8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: trunc.w.d $f0, $f12
|
||||
; MIPS32-NEXT: mfc1 $1, $f0
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptosi double %a to i8
|
||||
ret i8 %conv
|
||||
}
|
||||
|
||||
define i64 @f32tou64(float %a) {
|
||||
; MIPS32-LABEL: f32tou64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: .cfi_offset 31, -4
|
||||
; MIPS32-NEXT: jal __fixunssfdi
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptoui float %a to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
||||
define i64 @f64tou64(double %a) {
|
||||
; MIPS32-LABEL: f64tou64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: .cfi_offset 31, -4
|
||||
; MIPS32-NEXT: jal __fixunsdfdi
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%conv = fptoui double %a to i64
|
||||
ret i64 %conv
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
|
||||
--- |
|
||||
|
||||
define void @f32toi32() {entry: ret void}
|
||||
define void @f64toi32() {entry: ret void}
|
||||
|
||||
...
|
||||
---
|
||||
name: f32toi32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $f12
|
||||
|
||||
; FP32-LABEL: name: f32toi32
|
||||
; FP32: liveins: $f12
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
|
||||
; FP32: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP32: RetRA implicit $v0
|
||||
; FP64-LABEL: name: f32toi32
|
||||
; FP64: liveins: $f12
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
|
||||
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
|
||||
; FP64: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP64: RetRA implicit $v0
|
||||
%0:_(s32) = COPY $f12
|
||||
%1:_(s32) = G_FPTOSI %0(s32)
|
||||
$v0 = COPY %1(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: f64toi32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $d6
|
||||
|
||||
; FP32-LABEL: name: f64toi32
|
||||
; FP32: liveins: $d6
|
||||
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP32: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP32: RetRA implicit $v0
|
||||
; FP64-LABEL: name: f64toi32
|
||||
; FP64: liveins: $d6
|
||||
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
|
||||
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
|
||||
; FP64: $v0 = COPY [[FPTOSI]](s32)
|
||||
; FP64: RetRA implicit $v0
|
||||
%0:_(s64) = COPY $d6
|
||||
%1:_(s32) = G_FPTOSI %0(s64)
|
||||
$v0 = COPY %1(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue