forked from OSchip/llvm-project
[AMDGPU][GlobalISel] Handle G_PTR_ADD when looking for constant offset
Look throught G_PTRTOINT and G_PTR_ADD nodes when looking for constant offset for buffer stores. This also helps with merging of these instructions later on. Differential Revision: https://reviews.llvm.org/D95242
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@ -41,6 +41,20 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
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return std::make_pair(Def->getOperand(1).getReg(), Offset);
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}
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// Handle G_PTRTOINT (G_PTR_ADD base, const) case
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if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
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MachineInstr *Base;
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if (mi_match(Def->getOperand(1).getReg(), MRI,
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m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
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// If Base was int converted to pointer, simply return int and offset.
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if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
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return std::make_pair(Base->getOperand(1).getReg(), Offset);
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// Register returned here will be of pointer type.
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return std::make_pair(Base->getOperand(0).getReg(), Offset);
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}
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}
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return std::make_pair(Reg, 0);
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}
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@ -3518,12 +3518,17 @@ AMDGPULegalizerInfo::splitBufferOffsets(MachineIRBuilder &B,
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Register BaseReg;
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unsigned TotalConstOffset;
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const LLT S32 = LLT::scalar(32);
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MachineRegisterInfo &MRI = *B.getMRI();
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std::tie(BaseReg, TotalConstOffset) =
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AMDGPU::getBaseWithConstantOffset(*B.getMRI(), OrigOffset);
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AMDGPU::getBaseWithConstantOffset(MRI, OrigOffset);
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unsigned ImmOffset = TotalConstOffset;
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// If BaseReg is a pointer, convert it to int.
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if (MRI.getType(BaseReg).isPointer())
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BaseReg = B.buildPtrToInt(MRI.getType(OrigOffset), BaseReg).getReg(0);
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// If the immediate value is too big for the immoffset field, put the value
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// and -4096 into the immoffset field so that the value that is copied/added
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// for the voffset field is a multiple of 4096, and it stands more chance
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@ -0,0 +1,75 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -o - %s | FileCheck %s
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define amdgpu_cs void @test1(i32 %arg1, <4 x i32> inreg %arg2, i32, i32 addrspace(6)* inreg %arg3) {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0: ; %.entry
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; CHECK-NEXT: v_and_b32_e32 v3, 0x3ffffffc, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, 11
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; CHECK-NEXT: v_mov_b32_e32 v1, 22
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; CHECK-NEXT: v_mov_b32_e32 v2, 33
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; CHECK-NEXT: v_lshlrev_b32_e32 v3, 2, v3
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; CHECK-NEXT: v_add_i32_e32 v4, vcc, s4, v3
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; CHECK-NEXT: v_mov_b32_e32 v3, 44
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; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
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; CHECK-NEXT: s_endpgm
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.entry:
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%bs1 = and i32 %arg1, 1073741820
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%ep1 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs1
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%ad1 = ptrtoint i32 addrspace(6)* %ep1 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 11, <4 x i32> %arg2, i32 %ad1, i32 0, i32 0)
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%bs2 = or i32 %bs1, 1
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%ep2 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs2
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%ad2 = ptrtoint i32 addrspace(6)* %ep2 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 22, <4 x i32> %arg2, i32 %ad2, i32 0, i32 0)
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%bs3 = or i32 %bs1, 2
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%ep3 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs3
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%ad3 = ptrtoint i32 addrspace(6)* %ep3 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 33, <4 x i32> %arg2, i32 %ad3, i32 0, i32 0)
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%bs4 = or i32 %bs1, 3
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%ep4 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs4
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%ad4 = ptrtoint i32 addrspace(6)* %ep4 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 44, <4 x i32> %arg2, i32 %ad4, i32 0, i32 0)
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ret void
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}
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define amdgpu_cs void @test2(i32 %arg1, <4 x i32> inreg %arg2) {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0: ; %.entry
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; CHECK-NEXT: v_and_b32_e32 v3, 0x3ffffffc, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, 11
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; CHECK-NEXT: v_mov_b32_e32 v1, 22
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; CHECK-NEXT: v_mov_b32_e32 v2, 33
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; CHECK-NEXT: v_lshlrev_b32_e32 v4, 2, v3
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; CHECK-NEXT: v_mov_b32_e32 v3, 44
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; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
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; CHECK-NEXT: s_endpgm
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.entry:
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%bs1 = and i32 %arg1, 1073741820
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%ep1 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs1
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%ad1 = ptrtoint i32 addrspace(6)* %ep1 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 11, <4 x i32> %arg2, i32 %ad1, i32 0, i32 0)
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%bs2 = or i32 %bs1, 1
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%ep2 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs2
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%ad2 = ptrtoint i32 addrspace(6)* %ep2 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 22, <4 x i32> %arg2, i32 %ad2, i32 0, i32 0)
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%bs3 = or i32 %bs1, 2
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%ep3 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs3
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%ad3 = ptrtoint i32 addrspace(6)* %ep3 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 33, <4 x i32> %arg2, i32 %ad3, i32 0, i32 0)
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%bs4 = or i32 %bs1, 3
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%ep4 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs4
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%ad4 = ptrtoint i32 addrspace(6)* %ep4 to i32
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 44, <4 x i32> %arg2, i32 %ad4, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg)
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