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[InstCombine] add/move tests for opposite direction shifts; NFC

This commit is contained in:
Sanjay Patel 2022-06-06 11:13:17 -04:00
parent 79ec1e8fd6
commit 4b2681ffa8
2 changed files with 80 additions and 39 deletions
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39
llvm/test/Transforms/InstCombine/and.ll
View File

@ -1635,45 +1635,6 @@ define i16 @shl_lshr_pow2_const_case1(i16 %x) {
ret i16 %r
}
define i16 @shl_lshr_pow2_const_case2(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_case2(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 4, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[SHL]], 6
; CHECK-NEXT: [[R:%.*]] = or i16 [[LSHR]], -9
; CHECK-NEXT: ret i16 [[R]]
;
%shl = shl i16 4, %x
%lshr = lshr i16 %shl, 6
%r = or i16 %lshr, 65527 ; ~8
ret i16 %r
}
define i16 @shl_lshr_pow2_const_case3(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_case3(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 16, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = or i16 [[LSHR]], -9
; CHECK-NEXT: ret i16 [[R]]
;
%shl = shl i16 16, %x
%lshr = lshr i16 %shl, 3
%r = or i16 %lshr, 65527 ; ~8
ret i16 %r
}
define i13 @shl_lshr_pow2_const_case4(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_case4(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 16, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = trunc i16 [[LSHR]] to i13
; CHECK-NEXT: ret i13 [[R]]
;
%shl = shl i16 16, %x
%lshr = lshr i16 %shl, 3
%r = trunc i16 %lshr to i13
ret i13 %r
}
define i16 @shl_lshr_pow2_const_negative_oneuse(i16 %x) {
; CHECK-LABEL: @shl_lshr_pow2_const_negative_oneuse(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 4, [[X:%.*]]

80
llvm/test/Transforms/InstCombine/shift-shift.ll
View File

@ -420,3 +420,83 @@ define i32 @shl_lshr_constants(i32 %x) {
%r = lshr i32 %s, 3
ret i32 %r
}
define i8 @shl_lshr_demand1(i8 %x) {
; CHECK-LABEL: @shl_lshr_demand1(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 40, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i8 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = or i8 [[LSHR]], -32
; CHECK-NEXT: ret i8 [[R]]
;
%shl = shl i8 40, %x ; 0b0010_1000
%lshr = lshr i8 %shl, 3
%r = or i8 %lshr, 224 ; 0b1110_0000
ret i8 %r
}
define i8 @shl_ashr_demand2(i8 %x) {
; CHECK-LABEL: @shl_ashr_demand2(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 40, [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[SHL]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i8 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = or i8 [[TMP1]], -32
; CHECK-NEXT: ret i8 [[R]]
;
%shl = shl i8 40, %x ; 0b0010_1000
call void @use8(i8 %shl)
%lshr = ashr i8 %shl, 3
%r = or i8 %lshr, 224 ; 0b1110_0000
ret i8 %r
}
define i8 @shl_lshr_demand3(i8 %x) {
; CHECK-LABEL: @shl_lshr_demand3(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 40, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i8 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = or i8 [[LSHR]], -64
; CHECK-NEXT: ret i8 [[R]]
;
%shl = shl i8 40, %x ; 0b0010_1000
%lshr = lshr i8 %shl, 3
%r = or i8 %lshr, 192 ; 0b1100_0000
ret i8 %r
}
define i8 @shl_lshr_demand4(i8 %x) {
; CHECK-LABEL: @shl_lshr_demand4(
; CHECK-NEXT: [[SHL:%.*]] = shl i8 44, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr i8 [[SHL]], 3
; CHECK-NEXT: [[R:%.*]] = or i8 [[LSHR]], -32
; CHECK-NEXT: ret i8 [[R]]
;
%shl = shl i8 44, %x ; 0b0010_1100
%lshr = lshr i8 %shl, 3
%r = or i8 %lshr, 224 ; 0b1110_0000
ret i8 %r
}
define <2 x i6> @shl_lshr_demand5(<2 x i8> %x) {
; CHECK-LABEL: @shl_lshr_demand5(
; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> <i8 -108, i8 -108>, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact <2 x i8> [[SHL]], <i8 2, i8 2>
; CHECK-NEXT: [[R:%.*]] = trunc <2 x i8> [[LSHR]] to <2 x i6>
; CHECK-NEXT: ret <2 x i6> [[R]]
;
%shl = shl <2 x i8> <i8 148, i8 148>, %x ; 0b1001_0100
%lshr = lshr <2 x i8> %shl, <i8 2, i8 2>
%r = trunc <2 x i8> %lshr to <2 x i6>
ret <2 x i6> %r
}
define i16 @shl_lshr_demand6(i16 %x) {
; CHECK-LABEL: @shl_lshr_demand6(
; CHECK-NEXT: [[SHL:%.*]] = shl i16 -32624, [[X:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[SHL]], 4
; CHECK-NEXT: [[R:%.*]] = and i16 [[LSHR]], 4094
; CHECK-NEXT: ret i16 [[R]]
;
%shl = shl i16 32912, %x ; 0b1000_0000_1001_0000
%lshr = lshr i16 %shl, 4
%r = and i16 %lshr, 4094 ; 0b0000_1111_1111_1110
ret i16 %r
}