diff --git a/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp b/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp index 525425bd0f0c..b8fb80b6cc26 100644 --- a/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp +++ b/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp @@ -14,6 +14,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/DivergenceAnalysis.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/RegionInfo.h" #include "llvm/Analysis/RegionIterator.h" #include "llvm/Analysis/RegionPass.h" @@ -176,8 +177,9 @@ class StructurizeCFG : public RegionPass { Region *ParentRegion; DominatorTree *DT; + LoopInfo *LI; - std::deque Order; + SmallVector Order; BBSet Visited; BBPhiMap DeletedPhis; @@ -202,7 +204,7 @@ class StructurizeCFG : public RegionPass { void gatherPredicates(RegionNode *N); - void analyzeNode(RegionNode *N); + void collectInfos(); void insertConditions(bool Loops); @@ -256,6 +258,7 @@ public: AU.addRequired(); AU.addRequiredID(LowerSwitchID); AU.addRequired(); + AU.addRequired(); AU.addPreserved(); RegionPass::getAnalysisUsage(AU); @@ -289,17 +292,55 @@ bool StructurizeCFG::doInitialization(Region *R, RGPassManager &RGM) { /// \brief Build up the general order of nodes void StructurizeCFG::orderNodes() { - assert(Visited.empty()); - assert(Predicates.empty()); - assert(Loops.empty()); - assert(LoopPreds.empty()); + ReversePostOrderTraversal RPOT(ParentRegion); + SmallDenseMap LoopBlocks; - // This must be RPO order for the back edge detection to work - for (RegionNode *RN : ReversePostOrderTraversal(ParentRegion)) { - // FIXME: Is there a better order to use for structurization? - Order.push_back(RN); - analyzeNode(RN); + // The reverse post-order traversal of the list gives us an ordering close + // to what we want. The only problem with it is that sometimes backedges + // for outer loops will be visited before backedges for inner loops. + for (RegionNode *RN : RPOT) { + BasicBlock *BB = RN->getEntry(); + Loop *Loop = LI->getLoopFor(BB); + ++LoopBlocks[Loop]; } + + unsigned CurrentLoopDepth = 0; + Loop *CurrentLoop = nullptr; + for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { + BasicBlock *BB = (*I)->getEntry(); + unsigned LoopDepth = LI->getLoopDepth(BB); + + if (is_contained(Order, *I)) + continue; + + if (LoopDepth < CurrentLoopDepth) { + // Make sure we have visited all blocks in this loop before moving back to + // the outer loop. + + auto LoopI = I; + while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) { + LoopI++; + BasicBlock *LoopBB = (*LoopI)->getEntry(); + if (LI->getLoopFor(LoopBB) == CurrentLoop) { + --BlockCount; + Order.push_back(*LoopI); + } + } + } + + CurrentLoop = LI->getLoopFor(BB); + if (CurrentLoop) + LoopBlocks[CurrentLoop]--; + + CurrentLoopDepth = LoopDepth; + Order.push_back(*I); + } + + // This pass originally used a post-order traversal and then operated on + // the list in reverse. Now that we are using a reverse post-order traversal + // rather than re-working the whole pass to operate on the list in order, + // we just reverse the list and continue to operate on it in reverse. + std::reverse(Order.begin(), Order.end()); } /// \brief Determine the end of the loops @@ -425,19 +466,32 @@ void StructurizeCFG::gatherPredicates(RegionNode *N) { } /// \brief Collect various loop and predicate infos -void StructurizeCFG::analyzeNode(RegionNode *RN) { - DEBUG(dbgs() << "Visiting: " - << (RN->isSubRegion() ? "SubRegion with entry: " : "") - << RN->getEntry()->getName() << '\n'); +void StructurizeCFG::collectInfos() { + // Reset predicate + Predicates.clear(); - // Analyze all the conditions leading to a node - gatherPredicates(RN); + // and loop infos + Loops.clear(); + LoopPreds.clear(); - // Remember that we've seen this node - Visited.insert(RN->getEntry()); + // Reset the visited nodes + Visited.clear(); - // Find the last back edges - analyzeLoops(RN); + for (RegionNode *RN : reverse(Order)) { + DEBUG(dbgs() << "Visiting: " + << (RN->isSubRegion() ? "SubRegion with entry: " : "") + << RN->getEntry()->getName() << " Loop Depth: " + << LI->getLoopDepth(RN->getEntry()) << "\n"); + + // Analyze all the conditions leading to a node + gatherPredicates(RN); + + // Remember that we've seen this node + Visited.insert(RN->getEntry()); + + // Find the last back edges + analyzeLoops(RN); + } } /// \brief Insert the missing branch conditions @@ -610,7 +664,7 @@ void StructurizeCFG::changeExit(RegionNode *Node, BasicBlock *NewExit, BasicBlock *StructurizeCFG::getNextFlow(BasicBlock *Dominator) { LLVMContext &Context = Func->getContext(); BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : - Order.front()->getEntry(); + Order.back()->getEntry(); BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName, Func, Insert); DT->addNewBlock(Flow, Dominator); @@ -690,8 +744,7 @@ bool StructurizeCFG::isPredictableTrue(RegionNode *Node) { /// Take one node from the order vector and wire it up void StructurizeCFG::wireFlow(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); - Order.pop_front(); + RegionNode *Node = Order.pop_back_val(); Visited.insert(Node->getEntry()); if (isPredictableTrue(Node)) { @@ -715,7 +768,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, PrevNode = Node; while (!Order.empty() && !Visited.count(LoopEnd) && - dominatesPredicates(Entry, Order.front())) { + dominatesPredicates(Entry, Order.back())) { handleLoops(false, LoopEnd); } @@ -726,7 +779,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, void StructurizeCFG::handleLoops(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); + RegionNode *Node = Order.back(); BasicBlock *LoopStart = Node->getEntry(); if (!Loops.count(LoopStart)) { @@ -871,9 +924,10 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassManager &RGM) { ParentRegion = R; DT = &getAnalysis().getDomTree(); + LI = &getAnalysis().getLoopInfo(); orderNodes(); - + collectInfos(); createFlow(); insertConditions(false); insertConditions(true); diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll index 5b556f12f0d6..8cc02d497098 100644 --- a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll +++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll @@ -66,10 +66,9 @@ ENDIF: ; preds = %LOOP ; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop( ; OPT: llvm.amdgcn.break -; OPT: llvm.amdgcn.break -; OPT: llvm.amdgcn.if.break -; OPT: llvm.amdgcn.if.break ; OPT: llvm.amdgcn.loop +; OPT: llvm.amdgcn.if.break +; OPT: llvm.amdgcn.if.break ; OPT: llvm.amdgcn.end.cf ; GCN-LABEL: {{^}}multi_if_break_loop: diff --git a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll index ce2e86827ad0..51eb24cd658c 100644 --- a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll +++ b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll @@ -123,100 +123,55 @@ bb23: ; preds = %bb10 ; Earlier version of above, before a run of the structurizer. ; IR-LABEL: @nested_loop_conditions( -; IR: %tmp1235 = icmp slt i32 %tmp1134, 9 -; IR: br i1 %tmp1235, label %bb14.lr.ph, label %Flow - -; IR: bb14.lr.ph: -; IR: br label %bb14 - -; IR: Flow3: -; IR: call void @llvm.amdgcn.end.cf(i64 %18) -; IR: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %17) -; IR: %1 = extractvalue { i1, i64 } %0, 0 -; IR: %2 = extractvalue { i1, i64 } %0, 1 -; IR: br i1 %1, label %bb4.bb13_crit_edge, label %Flow4 - -; IR: bb4.bb13_crit_edge: -; IR: br label %Flow4 - -; IR: Flow4: -; IR: %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ] -; IR: call void @llvm.amdgcn.end.cf(i64 %2) -; IR: br label %Flow - -; IR: bb13: -; IR: br label %bb31 - -; IR: Flow: -; IR: %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ] -; IR: %5 = call { i1, i64 } @llvm.amdgcn.if(i1 %4) -; IR: %6 = extractvalue { i1, i64 } %5, 0 -; IR: %7 = extractvalue { i1, i64 } %5, 1 -; IR: br i1 %6, label %bb13, label %bb31 - -; IR: bb14: -; IR: %phi.broken = phi i64 [ %18, %Flow2 ], [ 0, %bb14.lr.ph ] -; IR: %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %16, %Flow2 ] -; IR: %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %15, %Flow2 ] -; IR: %tmp15 = icmp eq i32 %tmp1037, 1 -; IR: %8 = xor i1 %tmp15, true -; IR: %9 = call { i1, i64 } @llvm.amdgcn.if(i1 %8) -; IR: %10 = extractvalue { i1, i64 } %9, 0 -; IR: %11 = extractvalue { i1, i64 } %9, 1 -; IR: br i1 %10, label %bb31.loopexit, label %Flow1 +; IR: Flow7: +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %17) +; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15) +; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0 +; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1 +; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8 ; IR: Flow1: -; IR: %12 = call { i1, i64 } @llvm.amdgcn.else(i64 %11) -; IR: %13 = extractvalue { i1, i64 } %12, 0 -; IR: %14 = extractvalue { i1, i64 } %12, 1 -; IR: br i1 %13, label %bb16, label %Flow2 - -; IR: bb16: -; IR: %tmp17 = bitcast i64 %tmp3 to <2 x i32> -; IR: br label %bb18 +; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ] +; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ] +; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ] +; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ] +; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ] +; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi) +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %11) +; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17) +; IR-NEXT: br i1 %18, label %Flow7, label %bb14 ; IR: Flow2: -; IR: %loop.phi = phi i64 [ %21, %bb21 ], [ %phi.broken, %Flow1 ] -; IR: %15 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %Flow1 ] -; IR: %16 = phi i32 [ %tmp10, %bb21 ], [ undef, %Flow1 ] -; IR: %17 = phi i1 [ %20, %bb21 ], [ false, %Flow1 ] -; IR: %18 = call i64 @llvm.amdgcn.else.break(i64 %14, i64 %loop.phi) -; IR: call void @llvm.amdgcn.end.cf(i64 %14) -; IR: %19 = call i1 @llvm.amdgcn.loop(i64 %18) -; IR: br i1 %19, label %Flow3, label %bb14 - -; IR: bb18: -; IR: %tmp19 = load volatile i32, i32 addrspace(1)* undef -; IR: %tmp20 = icmp slt i32 %tmp19, 9 -; IR: br i1 %tmp20, label %bb21, label %bb18 +; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ] +; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ] +; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ] +; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ] +; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ] +; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ] +; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23) +; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0 +; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1 +; IR-NEXT: br i1 %25, label %bb21, label %Flow3 ; IR: bb21: -; IR: %tmp22 = extractelement <2 x i32> %tmp17, i64 1 -; IR: %tmp23 = lshr i32 %tmp22, 16 -; IR: %tmp24 = select i1 undef, i32 undef, i32 %tmp23 -; IR: %tmp25 = uitofp i32 %tmp24 to float -; IR: %tmp26 = fmul float %tmp25, 0x3EF0001000000000 -; IR: %tmp27 = fsub float %tmp26, undef -; IR: %tmp28 = fcmp olt float %tmp27, 5.000000e-01 -; IR: %tmp29 = select i1 %tmp28, i64 1, i64 2 -; IR: %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29 -; IR: %tmp7 = zext i32 %tmp30 to i64 -; IR: %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7 -; IR: %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16 -; IR: %tmp10 = extractelement <4 x i32> %tmp9, i64 0 -; IR: %tmp11 = load volatile i32, i32 addrspace(1)* undef -; IR: %tmp12 = icmp slt i32 %tmp11, 9 -; IR: %20 = xor i1 %tmp12, true -; IR: %21 = call i64 @llvm.amdgcn.if.break(i1 %20, i64 %phi.broken) -; IR: br label %Flow2 +; IR: %tmp12 = icmp slt i32 %tmp11, 9 +; IR-NEXT: %27 = xor i1 %tmp12, true +; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken) +; IR-NEXT: br label %Flow3 -; IR: bb31.loopexit: -; IR: br label %Flow1 +; IR: Flow3: +; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ] +; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ] +; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ] +; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ] +; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ] +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %26) +; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4 ; IR: bb31: -; IR: call void @llvm.amdgcn.end.cf(i64 %7) -; IR: store volatile i32 0, i32 addrspace(1)* undef -; IR: ret void +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %7) +; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef +; IR-NEXT: ret void ; GCN-LABEL: {{^}}nested_loop_conditions: diff --git a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll index 9cddffdd1795..5b5ea676baec 100644 --- a/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll +++ b/llvm/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s diff --git a/llvm/test/Transforms/StructurizeCFG/bug36015.ll b/llvm/test/Transforms/StructurizeCFG/bug36015.ll new file mode 100644 index 000000000000..24b9c9cdde2d --- /dev/null +++ b/llvm/test/Transforms/StructurizeCFG/bug36015.ll @@ -0,0 +1,53 @@ +; RUN: opt -S -structurizecfg %s | FileCheck %s + +; r321751 introduced a bug where control flow branching from if to exit was +; not handled properly and instead ended up in an infinite loop. +define void @bug36015(i32 %cmp0, i32 %count) { +entry: + br label %loop.outer + +loop.outer: + %ctr.loop.outer = phi i32 [ 0, %entry ], [ %ctr.else, %else ] + call void @foo(i32 0) + br label %loop.inner + +loop.inner: + %ctr.loop.inner = phi i32 [ %ctr.loop.outer, %loop.outer ], [ %ctr.if, %if ] + call void @foo(i32 1) + %cond.inner = icmp eq i32 %cmp0, %ctr.loop.inner + br i1 %cond.inner, label %if, label %else + +; CHECK: if: +; CHECK: %0 = xor i1 %cond.if, true +; CHECK: br label %Flow +if: + %ctr.if = add i32 %ctr.loop.inner, 1 + call void @foo(i32 2) + %cond.if = icmp slt i32 %ctr.if, %count + br i1 %cond.if, label %loop.inner, label %exit + +; CHECK: Flow: +; CHECK: %2 = phi i1 [ %0, %if ], [ true, %loop.inner ] +; CHECK: %3 = phi i1 [ false, %if ], [ true, %loop.inner ] +; CHECK: br i1 %2, label %Flow1, label %loop.inner + +; CHECK: Flow1: +; CHECK: br i1 %3, label %else, label %Flow2 + +; CHECK: else: +; CHECK: br label %Flow2 +else: + %ctr.else = add i32 %ctr.loop.inner, 1 + call void @foo(i32 3) + %cond.else = icmp slt i32 %ctr.else, %count + br i1 %cond.else, label %loop.outer, label %exit + +; CHECK: Flow2: +; CHECK: %6 = phi i1 [ %4, %else ], [ true, %Flow1 ] +; CHECK: br i1 %6, label %exit, label %loop.outer + +exit: + ret void +} + +declare void @foo(i32) diff --git a/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll b/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll index 7b5bd5acb629..58634d0d37db 100644 --- a/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll +++ b/llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll @@ -1,76 +1,32 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -structurizecfg %s -o - | FileCheck %s define void @main(float addrspace(1)* %out) { -; CHECK-LABEL: @main( -; CHECK-NEXT: main_body: -; CHECK-NEXT: br label [[LOOP_OUTER:%.*]] -; CHECK: LOOP.outer: -; CHECK-NEXT: [[TEMP8_0_PH:%.*]] = phi float [ 0.000000e+00, [[MAIN_BODY:%.*]] ], [ [[TMP13:%.*]], [[FLOW3:%.*]] ] -; CHECK-NEXT: [[TEMP4_0_PH:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP12:%.*]], [[FLOW3]] ] -; CHECK-NEXT: br label [[LOOP:%.*]] -; CHECK: LOOP: -; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP12]], [[FLOW:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = phi float [ undef, [[LOOP_OUTER]] ], [ [[TMP13]], [[FLOW]] ] -; CHECK-NEXT: [[TEMP4_0:%.*]] = phi i32 [ [[TEMP4_0_PH]], [[LOOP_OUTER]] ], [ [[TMP15:%.*]], [[FLOW]] ] -; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TEMP4_0]], 1 -; CHECK-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], 3 -; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP22]], true -; CHECK-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]] -; CHECK: Flow2: -; CHECK-NEXT: [[TMP3:%.*]] = phi float [ [[TEMP8_0_PH]], [[IF29:%.*]] ], [ [[TMP9:%.*]], [[FLOW1:%.*]] ] -; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP20]], [[IF29]] ], [ undef, [[FLOW1]] ] -; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP32:%.*]], [[IF29]] ], [ true, [[FLOW1]] ] -; CHECK-NEXT: br label [[FLOW]] -; CHECK: Flow3: -; CHECK-NEXT: br i1 [[TMP16:%.*]], label [[ENDLOOP:%.*]], label [[LOOP_OUTER]] -; CHECK: ENDLOOP: -; CHECK-NEXT: [[TEMP8_1:%.*]] = phi float [ [[TMP14:%.*]], [[FLOW3]] ] -; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP20]], 3 -; CHECK-NEXT: [[DOT45:%.*]] = select i1 [[TMP23]], float 0.000000e+00, float 1.000000e+00 -; CHECK-NEXT: store float [[DOT45]], float addrspace(1)* [[OUT:%.*]] -; CHECK-NEXT: ret void -; CHECK: ENDIF: -; CHECK-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP20]], 1 -; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP31]], true -; CHECK-NEXT: br i1 [[TMP6]], label [[ENDIF28:%.*]], label [[FLOW1]] -; CHECK: Flow1: -; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP20]], [[ENDIF28]] ], [ [[TMP0]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP8:%.*]] = phi float [ [[TMP35:%.*]], [[ENDIF28]] ], [ [[TMP1]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP9]] = phi float [ [[TMP35]], [[ENDIF28]] ], [ [[TEMP8_0_PH]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[TMP36:%.*]], [[ENDIF28]] ], [ true, [[ENDIF]] ] -; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[ENDIF28]] ], [ true, [[ENDIF]] ] -; CHECK-NEXT: br i1 [[TMP11]], label [[IF29]], label [[FLOW2:%.*]] -; CHECK: IF29: -; CHECK-NEXT: [[TMP32]] = icmp sgt i32 [[TMP20]], 2 -; CHECK-NEXT: br label [[FLOW2]] -; CHECK: Flow: -; CHECK-NEXT: [[TMP12]] = phi i32 [ [[TMP7]], [[FLOW2]] ], [ [[TMP0]], [[LOOP]] ] -; CHECK-NEXT: [[TMP13]] = phi float [ [[TMP8]], [[FLOW2]] ], [ [[TMP1]], [[LOOP]] ] -; CHECK-NEXT: [[TMP14]] = phi float [ [[TMP3]], [[FLOW2]] ], [ [[TEMP8_0_PH]], [[LOOP]] ] -; CHECK-NEXT: [[TMP15]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP]] ] -; CHECK-NEXT: [[TMP16]] = phi i1 [ [[TMP10]], [[FLOW2]] ], [ true, [[LOOP]] ] -; CHECK-NEXT: [[TMP17:%.*]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ true, [[LOOP]] ] -; CHECK-NEXT: br i1 [[TMP17]], label [[FLOW3]], label [[LOOP]] -; CHECK: ENDIF28: -; CHECK-NEXT: [[TMP35]] = fadd float [[TEMP8_0_PH]], 1.000000e+00 -; CHECK-NEXT: [[TMP36]] = icmp sgt i32 [[TMP20]], 2 -; CHECK-NEXT: br label [[FLOW1]] -; + +; CHECK: main_body: +; CHECK: br label %LOOP.outer main_body: br label %LOOP.outer +; CHECK: LOOP.outer: +; CHECK: br label %LOOP LOOP.outer: ; preds = %ENDIF28, %main_body %temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ] %temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ] br label %LOOP +; CHECK: LOOP: +; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow LOOP: ; preds = %IF29, %LOOP.outer %temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ] %tmp20 = add i32 %temp4.0, 1 %tmp22 = icmp sgt i32 %tmp20, 3 br i1 %tmp22, label %ENDLOOP, label %ENDIF +; CHECK: Flow3 +; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer + +; CHECK: ENDLOOP: +; CHECK: ret void ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP %temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ] %tmp23 = icmp eq i32 %tmp20, 3 @@ -78,14 +34,29 @@ ENDLOOP: ; preds = %ENDIF28, %IF29, %LO store float %.45, float addrspace(1)* %out ret void +; CHECK: ENDIF: +; CHECK: br i1 %tmp31, label %IF29, label %Flow1 ENDIF: ; preds = %LOOP %tmp31 = icmp sgt i32 %tmp20, 1 br i1 %tmp31, label %IF29, label %ENDIF28 +; CHECK: Flow: +; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP + +; CHECK: IF29: +; CHECK: br label %Flow1 IF29: ; preds = %ENDIF %tmp32 = icmp sgt i32 %tmp20, 2 br i1 %tmp32, label %ENDLOOP, label %LOOP +; CHECK: Flow1: +; CHECK: br label %Flow + +; CHECK: Flow2: +; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3 + +; CHECK: ENDIF28: +; CHECK: br label %Flow3 ENDIF28: ; preds = %ENDIF %tmp35 = fadd float %temp8.0.ph, 1.0 %tmp36 = icmp sgt i32 %tmp20, 2