forked from OSchip/llvm-project
Revert r321751, "StructurizeCFG: Fix broken backedge detection"
It causes regressions in various OpenGL test suites. Keep the test cases introduced by r321751 as XFAIL, and add a test case for the regression. Change-Id: I90b4cc354f68cebe5fcef1f2422dc8fe1c6d3514 Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36015 llvm-svn: 323355
This commit is contained in:
Nicolai Haehnle
parent
665784f170
commit
4afb64e4c6
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@ -14,6 +14,7 @@
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/RegionInfo.h"
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#include "llvm/Analysis/RegionIterator.h"
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#include "llvm/Analysis/RegionPass.h"
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@ -176,8 +177,9 @@ class StructurizeCFG : public RegionPass {
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Region *ParentRegion;
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DominatorTree *DT;
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LoopInfo *LI;
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std::deque<RegionNode *> Order;
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SmallVector<RegionNode *, 8> Order;
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BBSet Visited;
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BBPhiMap DeletedPhis;
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@ -202,7 +204,7 @@ class StructurizeCFG : public RegionPass {
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void gatherPredicates(RegionNode *N);
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void analyzeNode(RegionNode *N);
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void collectInfos();
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void insertConditions(bool Loops);
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@ -256,6 +258,7 @@ public:
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AU.addRequired<DivergenceAnalysis>();
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AU.addRequiredID(LowerSwitchID);
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.addRequired<LoopInfoWrapperPass>();
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AU.addPreserved<DominatorTreeWrapperPass>();
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RegionPass::getAnalysisUsage(AU);
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@ -289,17 +292,55 @@ bool StructurizeCFG::doInitialization(Region *R, RGPassManager &RGM) {
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/// \brief Build up the general order of nodes
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void StructurizeCFG::orderNodes() {
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assert(Visited.empty());
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assert(Predicates.empty());
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assert(Loops.empty());
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assert(LoopPreds.empty());
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ReversePostOrderTraversal<Region*> RPOT(ParentRegion);
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SmallDenseMap<Loop*, unsigned, 8> LoopBlocks;
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// This must be RPO order for the back edge detection to work
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for (RegionNode *RN : ReversePostOrderTraversal<Region*>(ParentRegion)) {
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// FIXME: Is there a better order to use for structurization?
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Order.push_back(RN);
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analyzeNode(RN);
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// The reverse post-order traversal of the list gives us an ordering close
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// to what we want. The only problem with it is that sometimes backedges
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// for outer loops will be visited before backedges for inner loops.
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for (RegionNode *RN : RPOT) {
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BasicBlock *BB = RN->getEntry();
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Loop *Loop = LI->getLoopFor(BB);
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++LoopBlocks[Loop];
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}
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unsigned CurrentLoopDepth = 0;
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Loop *CurrentLoop = nullptr;
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for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
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BasicBlock *BB = (*I)->getEntry();
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unsigned LoopDepth = LI->getLoopDepth(BB);
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if (is_contained(Order, *I))
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continue;
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if (LoopDepth < CurrentLoopDepth) {
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// Make sure we have visited all blocks in this loop before moving back to
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// the outer loop.
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auto LoopI = I;
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while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) {
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LoopI++;
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BasicBlock *LoopBB = (*LoopI)->getEntry();
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if (LI->getLoopFor(LoopBB) == CurrentLoop) {
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--BlockCount;
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Order.push_back(*LoopI);
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}
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}
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}
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CurrentLoop = LI->getLoopFor(BB);
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if (CurrentLoop)
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LoopBlocks[CurrentLoop]--;
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CurrentLoopDepth = LoopDepth;
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Order.push_back(*I);
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}
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// This pass originally used a post-order traversal and then operated on
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// the list in reverse. Now that we are using a reverse post-order traversal
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// rather than re-working the whole pass to operate on the list in order,
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// we just reverse the list and continue to operate on it in reverse.
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std::reverse(Order.begin(), Order.end());
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}
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/// \brief Determine the end of the loops
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@ -425,19 +466,32 @@ void StructurizeCFG::gatherPredicates(RegionNode *N) {
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}
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/// \brief Collect various loop and predicate infos
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void StructurizeCFG::analyzeNode(RegionNode *RN) {
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DEBUG(dbgs() << "Visiting: "
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<< (RN->isSubRegion() ? "SubRegion with entry: " : "")
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<< RN->getEntry()->getName() << '\n');
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void StructurizeCFG::collectInfos() {
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// Reset predicate
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Predicates.clear();
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// Analyze all the conditions leading to a node
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gatherPredicates(RN);
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// and loop infos
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Loops.clear();
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LoopPreds.clear();
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// Remember that we've seen this node
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Visited.insert(RN->getEntry());
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// Reset the visited nodes
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Visited.clear();
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// Find the last back edges
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analyzeLoops(RN);
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for (RegionNode *RN : reverse(Order)) {
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DEBUG(dbgs() << "Visiting: "
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<< (RN->isSubRegion() ? "SubRegion with entry: " : "")
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<< RN->getEntry()->getName() << " Loop Depth: "
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<< LI->getLoopDepth(RN->getEntry()) << "\n");
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// Analyze all the conditions leading to a node
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gatherPredicates(RN);
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// Remember that we've seen this node
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Visited.insert(RN->getEntry());
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// Find the last back edges
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analyzeLoops(RN);
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}
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}
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/// \brief Insert the missing branch conditions
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@ -610,7 +664,7 @@ void StructurizeCFG::changeExit(RegionNode *Node, BasicBlock *NewExit,
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BasicBlock *StructurizeCFG::getNextFlow(BasicBlock *Dominator) {
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LLVMContext &Context = Func->getContext();
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BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
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Order.front()->getEntry();
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Order.back()->getEntry();
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BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName,
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Func, Insert);
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DT->addNewBlock(Flow, Dominator);
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@ -690,8 +744,7 @@ bool StructurizeCFG::isPredictableTrue(RegionNode *Node) {
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/// Take one node from the order vector and wire it up
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void StructurizeCFG::wireFlow(bool ExitUseAllowed,
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BasicBlock *LoopEnd) {
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RegionNode *Node = Order.front();
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Order.pop_front();
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RegionNode *Node = Order.pop_back_val();
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Visited.insert(Node->getEntry());
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if (isPredictableTrue(Node)) {
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@ -715,7 +768,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed,
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PrevNode = Node;
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while (!Order.empty() && !Visited.count(LoopEnd) &&
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dominatesPredicates(Entry, Order.front())) {
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dominatesPredicates(Entry, Order.back())) {
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handleLoops(false, LoopEnd);
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}
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@ -726,7 +779,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed,
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void StructurizeCFG::handleLoops(bool ExitUseAllowed,
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BasicBlock *LoopEnd) {
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RegionNode *Node = Order.front();
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RegionNode *Node = Order.back();
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BasicBlock *LoopStart = Node->getEntry();
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if (!Loops.count(LoopStart)) {
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@ -871,9 +924,10 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassManager &RGM) {
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ParentRegion = R;
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DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
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orderNodes();
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collectInfos();
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createFlow();
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insertConditions(false);
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insertConditions(true);
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@ -66,10 +66,9 @@ ENDIF: ; preds = %LOOP
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; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(
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; OPT: llvm.amdgcn.break
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; OPT: llvm.amdgcn.break
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.loop
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.end.cf
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; GCN-LABEL: {{^}}multi_if_break_loop:
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@ -123,100 +123,55 @@ bb23: ; preds = %bb10
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; Earlier version of above, before a run of the structurizer.
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; IR-LABEL: @nested_loop_conditions(
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; IR: %tmp1235 = icmp slt i32 %tmp1134, 9
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; IR: br i1 %tmp1235, label %bb14.lr.ph, label %Flow
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; IR: bb14.lr.ph:
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; IR: br label %bb14
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; IR: Flow3:
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; IR: call void @llvm.amdgcn.end.cf(i64 %18)
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; IR: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %17)
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; IR: %1 = extractvalue { i1, i64 } %0, 0
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; IR: %2 = extractvalue { i1, i64 } %0, 1
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; IR: br i1 %1, label %bb4.bb13_crit_edge, label %Flow4
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; IR: bb4.bb13_crit_edge:
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; IR: br label %Flow4
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; IR: Flow4:
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; IR: %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ]
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; IR: call void @llvm.amdgcn.end.cf(i64 %2)
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; IR: br label %Flow
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; IR: bb13:
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; IR: br label %bb31
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; IR: Flow:
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; IR: %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ]
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; IR: %5 = call { i1, i64 } @llvm.amdgcn.if(i1 %4)
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; IR: %6 = extractvalue { i1, i64 } %5, 0
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; IR: %7 = extractvalue { i1, i64 } %5, 1
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; IR: br i1 %6, label %bb13, label %bb31
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; IR: bb14:
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; IR: %phi.broken = phi i64 [ %18, %Flow2 ], [ 0, %bb14.lr.ph ]
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; IR: %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %16, %Flow2 ]
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; IR: %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %15, %Flow2 ]
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; IR: %tmp15 = icmp eq i32 %tmp1037, 1
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; IR: %8 = xor i1 %tmp15, true
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; IR: %9 = call { i1, i64 } @llvm.amdgcn.if(i1 %8)
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; IR: %10 = extractvalue { i1, i64 } %9, 0
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; IR: %11 = extractvalue { i1, i64 } %9, 1
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; IR: br i1 %10, label %bb31.loopexit, label %Flow1
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; IR: Flow7:
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; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %17)
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; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15)
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; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
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; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
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; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8
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; IR: Flow1:
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; IR: %12 = call { i1, i64 } @llvm.amdgcn.else(i64 %11)
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; IR: %13 = extractvalue { i1, i64 } %12, 0
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; IR: %14 = extractvalue { i1, i64 } %12, 1
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; IR: br i1 %13, label %bb16, label %Flow2
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; IR: bb16:
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; IR: %tmp17 = bitcast i64 %tmp3 to <2 x i32>
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; IR: br label %bb18
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; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ]
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; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ]
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; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ]
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; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ]
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; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ]
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; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi)
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; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %11)
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; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17)
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; IR-NEXT: br i1 %18, label %Flow7, label %bb14
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; IR: Flow2:
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; IR: %loop.phi = phi i64 [ %21, %bb21 ], [ %phi.broken, %Flow1 ]
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; IR: %15 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %Flow1 ]
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; IR: %16 = phi i32 [ %tmp10, %bb21 ], [ undef, %Flow1 ]
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; IR: %17 = phi i1 [ %20, %bb21 ], [ false, %Flow1 ]
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; IR: %18 = call i64 @llvm.amdgcn.else.break(i64 %14, i64 %loop.phi)
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; IR: call void @llvm.amdgcn.end.cf(i64 %14)
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; IR: %19 = call i1 @llvm.amdgcn.loop(i64 %18)
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; IR: br i1 %19, label %Flow3, label %bb14
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; IR: bb18:
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; IR: %tmp19 = load volatile i32, i32 addrspace(1)* undef
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; IR: %tmp20 = icmp slt i32 %tmp19, 9
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; IR: br i1 %tmp20, label %bb21, label %bb18
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; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ]
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; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ]
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; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ]
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; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ]
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; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ]
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; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ]
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; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23)
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; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0
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; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1
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; IR-NEXT: br i1 %25, label %bb21, label %Flow3
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; IR: bb21:
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; IR: %tmp22 = extractelement <2 x i32> %tmp17, i64 1
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; IR: %tmp23 = lshr i32 %tmp22, 16
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; IR: %tmp24 = select i1 undef, i32 undef, i32 %tmp23
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; IR: %tmp25 = uitofp i32 %tmp24 to float
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; IR: %tmp26 = fmul float %tmp25, 0x3EF0001000000000
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; IR: %tmp27 = fsub float %tmp26, undef
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; IR: %tmp28 = fcmp olt float %tmp27, 5.000000e-01
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; IR: %tmp29 = select i1 %tmp28, i64 1, i64 2
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; IR: %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29
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; IR: %tmp7 = zext i32 %tmp30 to i64
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; IR: %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7
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; IR: %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
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; IR: %tmp10 = extractelement <4 x i32> %tmp9, i64 0
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; IR: %tmp11 = load volatile i32, i32 addrspace(1)* undef
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; IR: %tmp12 = icmp slt i32 %tmp11, 9
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; IR: %20 = xor i1 %tmp12, true
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; IR: %21 = call i64 @llvm.amdgcn.if.break(i1 %20, i64 %phi.broken)
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; IR: br label %Flow2
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; IR: %tmp12 = icmp slt i32 %tmp11, 9
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; IR-NEXT: %27 = xor i1 %tmp12, true
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; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken)
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; IR-NEXT: br label %Flow3
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; IR: bb31.loopexit:
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; IR: br label %Flow1
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; IR: Flow3:
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; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ]
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; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ]
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; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ]
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; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ]
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; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ]
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; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %26)
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; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4
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; IR: bb31:
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; IR: call void @llvm.amdgcn.end.cf(i64 %7)
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; IR: store volatile i32 0, i32 addrspace(1)* undef
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; IR: ret void
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; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %7)
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; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef
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; IR-NEXT: ret void
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; GCN-LABEL: {{^}}nested_loop_conditions:
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@ -1,3 +1,4 @@
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; XFAIL: *
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s
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@ -0,0 +1,53 @@
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; RUN: opt -S -structurizecfg %s | FileCheck %s
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; r321751 introduced a bug where control flow branching from if to exit was
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; not handled properly and instead ended up in an infinite loop.
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define void @bug36015(i32 %cmp0, i32 %count) {
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entry:
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br label %loop.outer
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loop.outer:
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%ctr.loop.outer = phi i32 [ 0, %entry ], [ %ctr.else, %else ]
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call void @foo(i32 0)
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br label %loop.inner
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loop.inner:
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%ctr.loop.inner = phi i32 [ %ctr.loop.outer, %loop.outer ], [ %ctr.if, %if ]
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call void @foo(i32 1)
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%cond.inner = icmp eq i32 %cmp0, %ctr.loop.inner
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br i1 %cond.inner, label %if, label %else
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; CHECK: if:
|
||||
; CHECK: %0 = xor i1 %cond.if, true
|
||||
; CHECK: br label %Flow
|
||||
if:
|
||||
%ctr.if = add i32 %ctr.loop.inner, 1
|
||||
call void @foo(i32 2)
|
||||
%cond.if = icmp slt i32 %ctr.if, %count
|
||||
br i1 %cond.if, label %loop.inner, label %exit
|
||||
|
||||
; CHECK: Flow:
|
||||
; CHECK: %2 = phi i1 [ %0, %if ], [ true, %loop.inner ]
|
||||
; CHECK: %3 = phi i1 [ false, %if ], [ true, %loop.inner ]
|
||||
; CHECK: br i1 %2, label %Flow1, label %loop.inner
|
||||
|
||||
; CHECK: Flow1:
|
||||
; CHECK: br i1 %3, label %else, label %Flow2
|
||||
|
||||
; CHECK: else:
|
||||
; CHECK: br label %Flow2
|
||||
else:
|
||||
%ctr.else = add i32 %ctr.loop.inner, 1
|
||||
call void @foo(i32 3)
|
||||
%cond.else = icmp slt i32 %ctr.else, %count
|
||||
br i1 %cond.else, label %loop.outer, label %exit
|
||||
|
||||
; CHECK: Flow2:
|
||||
; CHECK: %6 = phi i1 [ %4, %else ], [ true, %Flow1 ]
|
||||
; CHECK: br i1 %6, label %exit, label %loop.outer
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo(i32)
|
||||
|
|
@ -1,76 +1,32 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
|
||||
|
||||
define void @main(float addrspace(1)* %out) {
|
||||
; CHECK-LABEL: @main(
|
||||
; CHECK-NEXT: main_body:
|
||||
; CHECK-NEXT: br label [[LOOP_OUTER:%.*]]
|
||||
; CHECK: LOOP.outer:
|
||||
; CHECK-NEXT: [[TEMP8_0_PH:%.*]] = phi float [ 0.000000e+00, [[MAIN_BODY:%.*]] ], [ [[TMP13:%.*]], [[FLOW3:%.*]] ]
|
||||
; CHECK-NEXT: [[TEMP4_0_PH:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP12:%.*]], [[FLOW3]] ]
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: LOOP:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP12]], [[FLOW:%.*]] ]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = phi float [ undef, [[LOOP_OUTER]] ], [ [[TMP13]], [[FLOW]] ]
|
||||
; CHECK-NEXT: [[TEMP4_0:%.*]] = phi i32 [ [[TEMP4_0_PH]], [[LOOP_OUTER]] ], [ [[TMP15:%.*]], [[FLOW]] ]
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TEMP4_0]], 1
|
||||
; CHECK-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], 3
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP22]], true
|
||||
; CHECK-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]]
|
||||
; CHECK: Flow2:
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = phi float [ [[TEMP8_0_PH]], [[IF29:%.*]] ], [ [[TMP9:%.*]], [[FLOW1:%.*]] ]
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP20]], [[IF29]] ], [ undef, [[FLOW1]] ]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP32:%.*]], [[IF29]] ], [ true, [[FLOW1]] ]
|
||||
; CHECK-NEXT: br label [[FLOW]]
|
||||
; CHECK: Flow3:
|
||||
; CHECK-NEXT: br i1 [[TMP16:%.*]], label [[ENDLOOP:%.*]], label [[LOOP_OUTER]]
|
||||
; CHECK: ENDLOOP:
|
||||
; CHECK-NEXT: [[TEMP8_1:%.*]] = phi float [ [[TMP14:%.*]], [[FLOW3]] ]
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP20]], 3
|
||||
; CHECK-NEXT: [[DOT45:%.*]] = select i1 [[TMP23]], float 0.000000e+00, float 1.000000e+00
|
||||
; CHECK-NEXT: store float [[DOT45]], float addrspace(1)* [[OUT:%.*]]
|
||||
; CHECK-NEXT: ret void
|
||||
; CHECK: ENDIF:
|
||||
; CHECK-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP20]], 1
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP31]], true
|
||||
; CHECK-NEXT: br i1 [[TMP6]], label [[ENDIF28:%.*]], label [[FLOW1]]
|
||||
; CHECK: Flow1:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP20]], [[ENDIF28]] ], [ [[TMP0]], [[ENDIF]] ]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = phi float [ [[TMP35:%.*]], [[ENDIF28]] ], [ [[TMP1]], [[ENDIF]] ]
|
||||
; CHECK-NEXT: [[TMP9]] = phi float [ [[TMP35]], [[ENDIF28]] ], [ [[TEMP8_0_PH]], [[ENDIF]] ]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[TMP36:%.*]], [[ENDIF28]] ], [ true, [[ENDIF]] ]
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[ENDIF28]] ], [ true, [[ENDIF]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP11]], label [[IF29]], label [[FLOW2:%.*]]
|
||||
; CHECK: IF29:
|
||||
; CHECK-NEXT: [[TMP32]] = icmp sgt i32 [[TMP20]], 2
|
||||
; CHECK-NEXT: br label [[FLOW2]]
|
||||
; CHECK: Flow:
|
||||
; CHECK-NEXT: [[TMP12]] = phi i32 [ [[TMP7]], [[FLOW2]] ], [ [[TMP0]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[TMP13]] = phi float [ [[TMP8]], [[FLOW2]] ], [ [[TMP1]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[TMP14]] = phi float [ [[TMP3]], [[FLOW2]] ], [ [[TEMP8_0_PH]], [[LOOP]] ]
|
||||
; CHECK-NEXT: [[TMP15]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP]] ]
|
||||
; CHECK-NEXT: [[TMP16]] = phi i1 [ [[TMP10]], [[FLOW2]] ], [ true, [[LOOP]] ]
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ true, [[LOOP]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP17]], label [[FLOW3]], label [[LOOP]]
|
||||
; CHECK: ENDIF28:
|
||||
; CHECK-NEXT: [[TMP35]] = fadd float [[TEMP8_0_PH]], 1.000000e+00
|
||||
; CHECK-NEXT: [[TMP36]] = icmp sgt i32 [[TMP20]], 2
|
||||
; CHECK-NEXT: br label [[FLOW1]]
|
||||
;
|
||||
|
||||
; CHECK: main_body:
|
||||
; CHECK: br label %LOOP.outer
|
||||
main_body:
|
||||
br label %LOOP.outer
|
||||
|
||||
; CHECK: LOOP.outer:
|
||||
; CHECK: br label %LOOP
|
||||
LOOP.outer: ; preds = %ENDIF28, %main_body
|
||||
%temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ]
|
||||
%temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]
|
||||
br label %LOOP
|
||||
|
||||
; CHECK: LOOP:
|
||||
; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow
|
||||
LOOP: ; preds = %IF29, %LOOP.outer
|
||||
%temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ]
|
||||
%tmp20 = add i32 %temp4.0, 1
|
||||
%tmp22 = icmp sgt i32 %tmp20, 3
|
||||
br i1 %tmp22, label %ENDLOOP, label %ENDIF
|
||||
|
||||
; CHECK: Flow3
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer
|
||||
|
||||
; CHECK: ENDLOOP:
|
||||
; CHECK: ret void
|
||||
ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP
|
||||
%temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ]
|
||||
%tmp23 = icmp eq i32 %tmp20, 3
|
||||
|
|
@ -78,14 +34,29 @@ ENDLOOP: ; preds = %ENDIF28, %IF29, %LO
|
|||
store float %.45, float addrspace(1)* %out
|
||||
ret void
|
||||
|
||||
; CHECK: ENDIF:
|
||||
; CHECK: br i1 %tmp31, label %IF29, label %Flow1
|
||||
ENDIF: ; preds = %LOOP
|
||||
%tmp31 = icmp sgt i32 %tmp20, 1
|
||||
br i1 %tmp31, label %IF29, label %ENDIF28
|
||||
|
||||
; CHECK: Flow:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP
|
||||
|
||||
; CHECK: IF29:
|
||||
; CHECK: br label %Flow1
|
||||
IF29: ; preds = %ENDIF
|
||||
%tmp32 = icmp sgt i32 %tmp20, 2
|
||||
br i1 %tmp32, label %ENDLOOP, label %LOOP
|
||||
|
||||
; CHECK: Flow1:
|
||||
; CHECK: br label %Flow
|
||||
|
||||
; CHECK: Flow2:
|
||||
; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3
|
||||
|
||||
; CHECK: ENDIF28:
|
||||
; CHECK: br label %Flow3
|
||||
ENDIF28: ; preds = %ENDIF
|
||||
%tmp35 = fadd float %temp8.0.ph, 1.0
|
||||
%tmp36 = icmp sgt i32 %tmp20, 2
|
||||
|
|
|
|||
Loading…
Reference in New Issue