forked from OSchip/llvm-project
[GlobalISel] Fold or of shifts to funnel shift.
This change folds a basic funnel shift idiom: - (or (shl x, amt), (lshr y, sub(bw, amt))) -> fshl(x, y, amt) - (or (shl x, sub(bw, amt)), (lshr y, amt)) -> fshr(x, y, amt) This also helps in folding to rotate shift if x and y are equal since we already have a funnel shift to rotate combine. Differential Revision: https://reviews.llvm.org/D114499
This commit is contained in:
Abinav Puthan Purayil
parent
e20391fc5d
commit
4af45f10cc
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@ -564,6 +564,7 @@ public:
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/// This variant does not erase \p MI after calling the build function.
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void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo);
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bool matchOrShiftToFunnelShift(MachineInstr &MI, BuildFnTy &MatchInfo);
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bool matchFunnelShiftToRotate(MachineInstr &MI);
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void applyFunnelShiftToRotate(MachineInstr &MI);
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bool matchRotateOutOfRange(MachineInstr &MI);
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@ -645,6 +645,13 @@ def extract_vec_elt_combines : GICombineGroup<[
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extract_vec_elt_build_vec,
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extract_all_elts_from_build_vector]>;
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def funnel_shift_from_or_shift : GICombineRule<
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(defs root:$root, build_fn_matchinfo:$info),
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(match (wip_match_opcode G_OR):$root,
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[{ return Helper.matchOrShiftToFunnelShift(*${root}, ${info}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])
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>;
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def funnel_shift_to_rotate : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FSHL, G_FSHR):$root,
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@ -683,7 +690,8 @@ def bitfield_extract_from_and : GICombineRule<
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[{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
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def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>;
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def funnel_shift_combines : GICombineGroup<[funnel_shift_from_or_shift,
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funnel_shift_to_rotate]>;
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def bitfield_extract_from_sext_inreg : GICombineRule<
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(defs root:$root, build_fn_matchinfo:$info),
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@ -3866,6 +3866,51 @@ void CombinerHelper::applyBuildFnNoErase(
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MatchInfo(Builder);
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}
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bool CombinerHelper::matchOrShiftToFunnelShift(MachineInstr &MI,
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BuildFnTy &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_OR);
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Register Dst = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Dst);
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unsigned BitWidth = Ty.getScalarSizeInBits();
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Register ShlSrc, ShlAmt, LShrSrc, LShrAmt;
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unsigned FshOpc = 0;
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// TODO: Handle vector types.
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// Match (or (shl x, amt), (lshr y, sub(bw, amt))).
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if (mi_match(Dst, MRI,
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// m_GOr() handles the commuted version as well.
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m_GOr(m_GShl(m_Reg(ShlSrc), m_Reg(ShlAmt)),
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m_GLShr(m_Reg(LShrSrc), m_GSub(m_SpecificICst(BitWidth),
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m_Reg(LShrAmt)))))) {
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FshOpc = TargetOpcode::G_FSHL;
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// Match (or (shl x, sub(bw, amt)), (lshr y, amt)).
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} else if (mi_match(
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Dst, MRI,
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m_GOr(m_GLShr(m_Reg(LShrSrc), m_Reg(LShrAmt)),
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m_GShl(m_Reg(ShlSrc), m_GSub(m_SpecificICst(BitWidth),
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m_Reg(ShlAmt)))))) {
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FshOpc = TargetOpcode::G_FSHR;
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} else {
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return false;
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}
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if (ShlAmt != LShrAmt)
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return false;
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LLT AmtTy = MRI.getType(ShlAmt);
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if (!isLegalOrBeforeLegalizer({FshOpc, {Ty, AmtTy}}))
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return false;
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MatchInfo = [=](MachineIRBuilder &B) {
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B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, ShlAmt});
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};
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return true;
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}
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/// Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
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bool CombinerHelper::matchFunnelShiftToRotate(MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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@ -0,0 +1,142 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fshl_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: fshl_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)
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; CHECK-NEXT: $vgpr3 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%b:_(s32) = COPY $vgpr1
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%amt:_(s32) = COPY $vgpr2
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%bw:_(s32) = G_CONSTANT i32 32
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr3 = COPY %or
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...
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---
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name: fshl_commute_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: fshl_commute_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)
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; CHECK-NEXT: $vgpr3 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%b:_(s32) = COPY $vgpr1
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%amt:_(s32) = COPY $vgpr2
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%bw:_(s32) = G_CONSTANT i32 32
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
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%or:_(s32) = G_OR %lshr:_, %shl:_
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$vgpr3 = COPY %or
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...
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---
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name: fshr_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: fshr_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %or:_(s32) = G_FSHR %a, %b, %amt(s32)
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; CHECK-NEXT: $vgpr3 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%b:_(s32) = COPY $vgpr1
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%amt:_(s32) = COPY $vgpr2
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%bw:_(s32) = G_CONSTANT i32 32
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%lshr:_(s32) = G_LSHR %b:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%shl:_(s32) = G_SHL %a:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr3 = COPY %or
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...
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---
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name: fshl_i32_bad_const
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: fshl_i32_bad_const
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
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; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
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; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)
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; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
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; CHECK-NEXT: $vgpr3 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%b:_(s32) = COPY $vgpr1
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%amt:_(s32) = COPY $vgpr2
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%bw:_(s32) = G_CONSTANT i32 31
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr3 = COPY %or
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...
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---
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name: fshl_i32_bad_amt_reg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
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; CHECK-LABEL: name: fshl_i32_bad_amt_reg
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %b:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr3
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; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
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; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
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; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
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; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)
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; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
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; CHECK-NEXT: $vgpr4 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%b:_(s32) = COPY $vgpr1
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%amt:_(s32) = COPY $vgpr2
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%amt1:_(s32) = COPY $vgpr3
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%bw:_(s32) = G_CONSTANT i32 32
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt1:_
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%lshr:_(s32) = G_LSHR %b:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr4 = COPY %or
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...
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@ -0,0 +1,131 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: rotl_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: rotl_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
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; CHECK-NEXT: $vgpr2 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%amt:_(s32) = COPY $vgpr1
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%bw:_(s32) = G_CONSTANT i32 32
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr2 = COPY %or
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...
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---
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name: rotl_commute_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: rotl_commute_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %or:_(s32) = G_ROTL %a, %amt(s32)
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; CHECK-NEXT: $vgpr2 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%amt:_(s32) = COPY $vgpr1
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%bw:_(s32) = G_CONSTANT i32 32
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
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%or:_(s32) = G_OR %lshr:_, %shl:_
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$vgpr2 = COPY %or
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...
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---
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name: rotr_i32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: rotr_i32
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %or:_(s32) = G_ROTR %a, %amt(s32)
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; CHECK-NEXT: $vgpr2 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%amt:_(s32) = COPY $vgpr1
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%bw:_(s32) = G_CONSTANT i32 32
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%lshr:_(s32) = G_LSHR %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%shl:_(s32) = G_SHL %a:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr2 = COPY %or
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...
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---
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name: rotl_i32_bad_const
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: rotl_i32_bad_const
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
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; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt
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; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
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; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
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; CHECK-NEXT: $vgpr2 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
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%amt:_(s32) = COPY $vgpr1
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%bw:_(s32) = G_CONSTANT i32 31
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%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
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%sub:_(s32) = G_SUB %bw:_, %amt:_
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%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
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%or:_(s32) = G_OR %shl:_, %lshr:_
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$vgpr2 = COPY %or
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...
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---
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name: rotl_i32_bad_amt_reg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: rotl_i32_bad_amt_reg
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %a:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %amt:_(s32) = COPY $vgpr1
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; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr2
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; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32
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; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)
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; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1
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; CHECK-NEXT: %lshr:_(s32) = G_LSHR %a, %sub(s32)
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; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr
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; CHECK-NEXT: $vgpr3 = COPY %or(s32)
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%a:_(s32) = COPY $vgpr0
|
||||
%amt:_(s32) = COPY $vgpr1
|
||||
%amt1:_(s32) = COPY $vgpr2
|
||||
%bw:_(s32) = G_CONSTANT i32 32
|
||||
%shl:_(s32) = G_SHL %a:_, %amt:_(s32)
|
||||
%sub:_(s32) = G_SUB %bw:_, %amt1:_
|
||||
%lshr:_(s32) = G_LSHR %a:_, %sub:_(s32)
|
||||
%or:_(s32) = G_OR %shl:_, %lshr:_
|
||||
$vgpr3 = COPY %or
|
||||
...
|
||||
Loading…
Reference in New Issue