forked from OSchip/llvm-project
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
allowing redundant and's to be eliminated by the dag combiner. llvm-svn: 25800
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@ -57,6 +57,14 @@ namespace {
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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/// be zero. Op is expected to be a target specific node. Used by DAG
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/// combiner.
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virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask,
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MVIZFnPtr MVIZ) const;
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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@ -191,6 +199,24 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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/// be zero. Op is expected to be a target specific node. Used by DAG
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/// combiner.
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bool SparcV8TargetLowering::
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isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
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MVIZFnPtr MVIZ) const {
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switch (Op.getOpcode()) {
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default: return false;
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case V8ISD::SELECT_ICC:
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case V8ISD::SELECT_FCC:
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assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
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// These operations are masked zero if both the left and the right are zero.
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return MVIZ(Op.getOperand(0), Mask, *this) &&
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MVIZ(Op.getOperand(1), Mask, *this);
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}
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}
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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