[AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE.

Also use this opportunity start to clean up the mess of vector type lists we
have in the LegalizerInfo. Unfortunately since the legalizer rule builders require
std::initializer_list objects as parameters we can't programmatically generate the
type lists.
This commit is contained in:
Amara Emerson 2020-09-30 17:20:57 -07:00
parent e24f0ac7a3
commit 4ab45cc226
3 changed files with 57 additions and 52 deletions

View File

@ -54,6 +54,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT v2s64 = LLT::vector(2, 64);
const LLT v2p0 = LLT::vector(2, p0);
const auto PackedVectorAllTypeList = {/* Begin 128bit types */
v16s8, v8s16, v4s32, v2s64, v2p0,
/* End 128bit types */
/* Begin 64bit types */
v8s8, v4s16, v2s32};
const TargetMachine &TM = ST.getTargetLowering()->getTargetMachine();
// FIXME: support subtargets which have neon/fp-armv8 disabled.
@ -63,7 +69,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
}
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
.legalFor({p0, s1, s8, s16, s32, s64, v2s32, v4s32, v2s64, v16s8, v8s16})
.legalFor({p0, s1, s8, s16, s32, s64})
.legalFor(PackedVectorAllTypeList)
.clampScalar(0, s1, s64)
.widenScalarToNextPow2(0, 8)
.fewerElementsIf(
@ -79,8 +86,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
return std::make_pair(0, EltTy);
});
getActionDefinitionsBuilder(G_PHI)
.legalFor({p0, s16, s32, s64, v2s32, v4s32, v2s64})
getActionDefinitionsBuilder(G_PHI).legalFor({p0, s16, s32, s64})
.legalFor(PackedVectorAllTypeList)
.clampScalar(0, s16, s64)
.widenScalarToNextPow2(0);

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@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer -O0 %s -o - | FileCheck %s
# RUN: llc -march=aarch64 -run-pass=legalizer -global-isel-abort=1 -O0 %s -o - | FileCheck %s
---
name: test_freeze_s64
body: |
@ -67,3 +67,21 @@ body: |
$w0 = COPY %1
$w1 = COPY %2
...
---
name: test_freeze_v8s8
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_freeze_v8s8
; CHECK: %d0:_(<8 x s8>) = COPY $d0
; CHECK: [[FREEZE:%[0-9]+]]:_(<8 x s8>) = G_FREEZE %d0
; CHECK: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x s8>)
; CHECK: $w0 = COPY [[UV]](<4 x s8>)
; CHECK: $w1 = COPY [[UV1]](<4 x s8>)
%d0:_(<8 x s8>) = COPY $d0
%0:_(<8 x s8>) = G_FREEZE %d0
%1:_(<4 x s8>), %2:_(<4 x s8>) = G_UNMERGE_VALUES %0
$w0 = COPY %1
$w1 = COPY %2
...

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@ -1,51 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
--- |
; ModuleID = '/tmp/test.ll'
source_filename = "/tmp/test.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-unknown"
define i32 @legalize_phi(i32 %argc) {
entry:
ret i32 0
}
define i64* @legalize_phi_ptr(i64* %a, i64* %b, i1 %cond) {
entry:
ret i64* null
}
define i32 @legalize_phi_empty(i32 %argc) {
entry:
ret i32 0
}
define i32 @legalize_phi_loop(i32 %argc) {
entry:
ret i32 0
}
define i32 @legalize_phi_cycle(i32 %argc) {
entry:
ret i32 0
}
define i32 @legalize_phi_same_bb(i32 %argc) {
entry:
ret i32 0
}
define i32 @legalize_phi_diff_bb(i32 %argc, i32 %argc2) {
entry:
ret i32 0
}
define i32 @legalize_phi_check_insertpt(i64 %a) {
entry:
ret i32 0
}
...
# RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -global-isel-abort=1 -run-pass=legalizer %s -o - | FileCheck %s
---
name: legalize_phi
alignment: 4
@ -610,7 +564,6 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
body: |
; Check that the G_MERGE here gets inserted after all the PHIs.
; CHECK-LABEL: name: legalize_phi_check_insertpt
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
@ -627,6 +580,7 @@ body: |
; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16)
; CHECK: G_STORE [[PHI2]](s64), [[COPY1]](p0) :: (store 8)
; CHECK: RET_ReallyLR
; Check that the G_MERGE here gets inserted after all the PHIs.
bb.0:
successors: %bb.1(0x40000000)
liveins: $x0, $x1
@ -644,3 +598,29 @@ body: |
RET_ReallyLR
...
---
name: legalize_phi_vector
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: legalize_phi_vector
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: [[PHI:%[0-9]+]]:_(<16 x s8>) = G_PHI [[COPY]](<16 x s8>), %bb.0
; CHECK: $q0 = COPY [[PHI]](<16 x s8>)
; CHECK: RET_ReallyLR
bb.0:
successors: %bb.1
liveins: $q0, $x1
%0:_(<16 x s8>) = COPY $q0
G_BR %bb.1
bb.1:
%3:_(<16 x s8>) = G_PHI %0(<16 x s8>), %bb.0
$q0 = COPY %3(<16 x s8>)
RET_ReallyLR
...