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[PowerPC] Fix ADDE, SUBE do not know how to promote operator 

Summary:
This patch is created to fix the Bugzilla bug 39815:
https://bugs.llvm.org/show_bug.cgi?id=39815 

This patch is to support promotion integer result for the instruction ADDE, SUBE.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D56119

llvm-svn: 350161
This commit is contained in:
Kang Zhang 2018-12-30 07:48:09 +00:00
parent 2e8bbb9c00
commit 4aa6453767
2 changed files with 36 additions and 0 deletions
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5
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -140,6 +140,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::SMULO:
case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
case ISD::ADDE:
case ISD::SUBE:
case ISD::ADDCARRY:
case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
@ -865,6 +867,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
// the third operand of ADDE/SUBE nodes is carry flag, which differs from
// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
if (ResNo == 1)
return PromoteIntRes_Overflow(N);

31
llvm/test/CodeGen/PowerPC/pr39815.ll Normal file
View File

@ -0,0 +1,31 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs | FileCheck %s
@b = common dso_local local_unnamed_addr global i64* null, align 8
@a = common dso_local local_unnamed_addr global i8 0, align 1
define void @testADDEPromoteResult() {
entry:
%0 = load i64*, i64** @b, align 8
%1 = load i64, i64* %0, align 8
%cmp = icmp ne i64* %0, null
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %1, %conv1
%2 = trunc i64 %add to i8
%conv2 = and i8 %2, 5
store i8 %conv2, i8* @a, align 1
ret void
; CHECK-LABEL: @testADDEPromoteResult
; CHECK: # %bb.0:
; CHECK-DAG: addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK-DAG: ld [[REG3:[0-9]+]], [[VAR1]]@toc@l([[REG1]])
; CHECK-DAG: lbz [[REG4:[0-9]+]], 0([[REG3]])
; CHECK-DAG: addic [[REG5:[0-9]+]], [[REG3]], -1
; CHECK-DAG: extsb [[REG6:[0-9]+]], [[REG4]]
; CHECK-DAG: addze [[REG7:[0-9]+]], [[REG6]]
; CHECK-DAG: addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK-DAG: andi. [[REG9:[0-9]+]], [[REG7]], 5
; CHECK-DAG: stb [[REG9]], [[VAR2]]@toc@l([[REG8]])
; CHECK: blr
}