forked from OSchip/llvm-project
Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. llvm-svn: 188676
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@ -4087,7 +4087,8 @@ def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
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// Aliases for ADD without the ".w" optional width specifier.
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
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(t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
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(t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
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cc_out:$s)>;
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def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
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(t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
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@ -80,6 +80,7 @@ _func:
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adds r2, r2, #56
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adds r2, #56
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add r1, r7, #0xcbcbcbcb
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add sp, sp, #0x1fe0000
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adds.w r2, #-16
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adds.w r2, r2, #-16
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@ -103,6 +104,7 @@ _func:
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@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
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@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
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@ CHECK: add.w r1, r7, #3419130827 @ encoding: [0x07,0xf1,0xcb,0x31]
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@ CHECK: add.w sp, sp, #33423360 @ encoding: [0x0d,0xf1,0xff,0x7d]
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@ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02]
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@ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02]
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