From 4a9c0bb147667fd2028e3831d3baa03a60a06968 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 17 Feb 2007 06:44:03 +0000 Subject: [PATCH] Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to: _test: lis r2, 743 li r3, 0 stw r3, 32751(r2) blr instead of: _test: li r2, 0 stw r2, 32751(48693248) blr Implement support for ppc64 as well, allowing it to produce better code. llvm-svn: 34371 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 88815a7c5adf..56f5d11f9559 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -743,14 +743,18 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); return true; } - - // FIXME: Handle small sext constant offsets in PPC64 mode also! - if (CN->getValueType(0) == MVT::i32) { + + // Handle 32-bit sext immediates with LIS + addr mode. + if (CN->getValueType(0) == MVT::i32 || + (int64_t)CN->getValue() == (int)CN->getValue()) { int Addr = (int)CN->getValue(); // Otherwise, break this down into an LIS + disp. - Disp = DAG.getTargetConstant((short)Addr, MVT::i32); - Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32); + Disp = DAG.getTargetConstant((short)Addr, MVT::i32); + + Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); + unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; + Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); return true; } }