forked from OSchip/llvm-project
[X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN pattern matching and remove the X86 implementation
Follow up to D10947 - D9746 added general SMAX/SMIN/UMAX/UMIN pattern matching to SelectionDAGBuilder::visitSelect. This patch removes the X86 implementation and improves the AVX1/AVX2 support to correctly lower 256-bit integer vectors. Differential Revision: http://reviews.llvm.org/D12006 llvm-svn: 244949
This commit is contained in:
Simon Pilgrim
parent
361231ecd5
commit
4a8d6b3b9e
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@ -1198,6 +1198,19 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::MUL, MVT::v8i32, Custom);
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setOperationAction(ISD::MUL, MVT::v16i16, Custom);
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setOperationAction(ISD::MUL, MVT::v32i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
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setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
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setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
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setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
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setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
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setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
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setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
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setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
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setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
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setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
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setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
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setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
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}
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// In the customized shift lowering, the legal cases in AVX2 will be
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@ -16881,6 +16894,13 @@ static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
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return Lower256IntArith(Op, DAG);
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}
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static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getSimpleValueType().is256BitVector() &&
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Op.getSimpleValueType().isInteger() &&
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"Only handle AVX 256-bit vector integer operation");
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return Lower256IntArith(Op, DAG);
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}
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static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDLoc dl(Op);
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@ -18772,6 +18792,10 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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case ISD::ADD: return LowerADD(Op, DAG);
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case ISD::SUB: return LowerSUB(Op, DAG);
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case ISD::SMAX:
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case ISD::SMIN:
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case ISD::UMAX:
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case ISD::UMIN: return LowerMINMAX(Op, DAG);
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case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
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case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
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case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
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@ -22365,96 +22389,6 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
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static std::pair<unsigned, bool>
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matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
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SelectionDAG &DAG, const X86Subtarget *Subtarget) {
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if (!VT.isVector())
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return std::make_pair(0, false);
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bool NeedSplit = false;
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switch (VT.getSimpleVT().SimpleTy) {
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default: return std::make_pair(0, false);
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case MVT::v4i64:
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case MVT::v2i64:
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if (!Subtarget->hasVLX())
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return std::make_pair(0, false);
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break;
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case MVT::v64i8:
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case MVT::v32i16:
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if (!Subtarget->hasBWI())
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return std::make_pair(0, false);
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break;
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case MVT::v16i32:
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case MVT::v8i64:
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if (!Subtarget->hasAVX512())
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return std::make_pair(0, false);
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break;
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case MVT::v32i8:
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case MVT::v16i16:
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case MVT::v8i32:
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if (!Subtarget->hasAVX2())
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NeedSplit = true;
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if (!Subtarget->hasAVX())
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return std::make_pair(0, false);
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break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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if (!Subtarget->hasSSE2())
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return std::make_pair(0, false);
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}
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// SSE2 has only a small subset of the operations.
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bool hasUnsigned = Subtarget->hasSSE41() ||
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(Subtarget->hasSSE2() && VT == MVT::v16i8);
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bool hasSigned = Subtarget->hasSSE41() ||
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(Subtarget->hasSSE2() && VT == MVT::v8i16);
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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unsigned Opc = 0;
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// Check for x CC y ? x : y.
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if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
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DAG.isEqualTo(RHS, Cond.getOperand(1))) {
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switch (CC) {
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default: break;
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case ISD::SETULT:
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case ISD::SETULE:
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Opc = hasUnsigned ? ISD::UMIN : 0; break;
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case ISD::SETUGT:
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case ISD::SETUGE:
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Opc = hasUnsigned ? ISD::UMAX : 0; break;
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case ISD::SETLT:
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case ISD::SETLE:
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Opc = hasSigned ? ISD::SMIN : 0; break;
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case ISD::SETGT:
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case ISD::SETGE:
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Opc = hasSigned ? ISD::SMAX : 0; break;
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}
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// Check for x CC y ? y : x -- a min/max with reversed arms.
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} else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
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DAG.isEqualTo(RHS, Cond.getOperand(0))) {
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switch (CC) {
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default: break;
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case ISD::SETULT:
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case ISD::SETULE:
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Opc = hasUnsigned ? ISD::UMAX : 0; break;
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case ISD::SETUGT:
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case ISD::SETUGE:
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Opc = hasUnsigned ? ISD::UMIN : 0; break;
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case ISD::SETLT:
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case ISD::SETLE:
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Opc = hasSigned ? ISD::SMAX : 0; break;
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case ISD::SETGT:
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case ISD::SETGE:
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Opc = hasSigned ? ISD::SMIN : 0; break;
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}
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}
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return std::make_pair(Opc, NeedSplit);
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}
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static SDValue
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transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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@ -22864,32 +22798,6 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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// Try to match a min/max vector operation.
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if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
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std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
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unsigned Opc = ret.first;
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bool NeedSplit = ret.second;
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if (Opc && NeedSplit) {
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unsigned NumElems = VT.getVectorNumElements();
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// Extract the LHS vectors
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SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
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SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
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// Extract the RHS vectors
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SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
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SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
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// Create min/max for each subvector
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LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
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RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
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// Merge the result
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
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} else if (Opc)
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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// Simplify vector selection if condition value type matches vselect
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// operand type
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if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
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