forked from OSchip/llvm-project
[InstCombine] fold adds of constants separated by sext/zext
This is part of a transform that may be done in the backend: D13757 ...but it should always be beneficial to fold this sooner in IR for all targets. https://rise4fun.com/Alive/vaiW Name: sext add nsw %add = add nsw i8 %i, C0 %ext = sext i8 %add to i32 %r = add i32 %ext, C1 => %s = sext i8 %i to i32 %r = add i32 %s, sext(C0)+C1 Name: zext add nuw %add = add nuw i8 %i, C0 %ext = zext i8 %add to i16 %r = add i16 %ext, C1 => %s = zext i8 %i to i16 %r = add i16 %s, zext(C0)+C1 llvm-svn: 355118
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@ -822,6 +822,47 @@ static Value *checkForNegativeOperand(BinaryOperator &I,
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return nullptr;
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}
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/// Wrapping flags may allow combining constants separated by an extend.
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static Instruction *foldNoWrapAdd(BinaryOperator &Add,
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InstCombiner::BuilderTy &Builder) {
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Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1);
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Type *Ty = Add.getType();
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Constant *Op1C;
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if (!match(Op1, m_Constant(Op1C)))
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return nullptr;
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// Try this match first because it results in an add in the narrow type.
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// (zext (X +nuw C2)) + C1 --> zext (X + (C2 + trunc(C1)))
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Value *X;
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const APInt *C1, *C2;
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if (match(Op1, m_APInt(C1)) &&
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match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_APInt(C2))))) &&
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C1->isNegative() && C1->sge(-C2->sext(C1->getBitWidth()))) {
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Constant *NewC =
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ConstantInt::get(X->getType(), *C2 + C1->trunc(C2->getBitWidth()));
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return new ZExtInst(Builder.CreateNUWAdd(X, NewC), Ty);
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}
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// More general combining of constants in the wide type.
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// (sext (X +nsw NarrowC)) + C --> (sext X) + (sext(NarrowC) + C)
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Constant *NarrowC;
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if (match(Op0, m_OneUse(m_SExt(m_NSWAdd(m_Value(X), m_Constant(NarrowC)))))) {
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Constant *WideC = ConstantExpr::getSExt(NarrowC, Ty);
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Constant *NewC = ConstantExpr::getAdd(WideC, Op1C);
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Value *WideX = Builder.CreateSExt(X, Ty);
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return BinaryOperator::CreateAdd(WideX, NewC);
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}
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// (zext (X +nuw NarrowC)) + C --> (zext X) + (zext(NarrowC) + C)
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if (match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_Constant(NarrowC)))))) {
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Constant *WideC = ConstantExpr::getZExt(NarrowC, Ty);
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Constant *NewC = ConstantExpr::getAdd(WideC, Op1C);
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Value *WideX = Builder.CreateZExt(X, Ty);
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return BinaryOperator::CreateAdd(WideX, NewC);
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}
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return nullptr;
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}
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Instruction *InstCombiner::foldAddWithConstant(BinaryOperator &Add) {
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Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1);
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Constant *Op1C;
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@ -870,14 +911,6 @@ Instruction *InstCombiner::foldAddWithConstant(BinaryOperator &Add) {
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C2->isMinSignedValue() && C2->sext(Ty->getScalarSizeInBits()) == *C)
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return CastInst::Create(Instruction::SExt, X, Ty);
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// (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C))
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if (match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_APInt(C2))))) &&
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C->isNegative() && C->sge(-C2->sext(C->getBitWidth()))) {
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Constant *NewC =
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ConstantInt::get(X->getType(), *C2 + C->trunc(C2->getBitWidth()));
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return new ZExtInst(Builder.CreateNUWAdd(X, NewC), Ty);
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}
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if (C->isOneValue() && Op0->hasOneUse()) {
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// add (sext i1 X), 1 --> zext (not X)
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// TODO: The smallest IR representation is (select X, 0, 1), and that would
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@ -1050,6 +1083,9 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
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if (Instruction *X = foldAddWithConstant(I))
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return X;
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if (Instruction *X = foldNoWrapAdd(I, Builder))
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return X;
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// FIXME: This should be moved into the above helper function to allow these
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// transforms for general constant or constant splat vectors.
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Value *LHS = I.getOperand(0), *RHS = I.getOperand(1);
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@ -396,9 +396,8 @@ define i8 @add_nuw_signbit(i8 %x) {
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define i32 @add_nsw_sext_add(i8 %x) {
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; CHECK-LABEL: @add_nsw_sext_add(
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[X:%.*]], 42
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; CHECK-NEXT: [[EXT:%.*]] = sext i8 [[ADD]] to i32
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; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[EXT]], 356
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; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[TMP1]], 398
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; CHECK-NEXT: ret i32 [[R]]
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;
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%add = add nsw i8 %x, 42
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@ -407,6 +406,8 @@ define i32 @add_nsw_sext_add(i8 %x) {
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ret i32 %r
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}
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; Negative test - extra use of the sext means increase of instructions.
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define i32 @add_nsw_sext_add_extra_use_1(i8 %x, i32* %p) {
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; CHECK-LABEL: @add_nsw_sext_add_extra_use_1(
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[X:%.*]], 42
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@ -426,8 +427,8 @@ define <2 x i32> @add_nsw_sext_add_vec_extra_use_2(<2 x i8> %x, <2 x i8>* %p) {
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; CHECK-LABEL: @add_nsw_sext_add_vec_extra_use_2(
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i8> [[X:%.*]], <i8 42, i8 -5>
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; CHECK-NEXT: store <2 x i8> [[ADD]], <2 x i8>* [[P:%.*]], align 2
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; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i8> [[ADD]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[EXT]], <i32 356, i32 12>
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; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i8> [[X]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[TMP1]], <i32 398, i32 7>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%add = add nsw <2 x i8> %x, <i8 42, i8 -5>
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@ -439,9 +440,8 @@ define <2 x i32> @add_nsw_sext_add_vec_extra_use_2(<2 x i8> %x, <2 x i8>* %p) {
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define <2 x i32> @add_nuw_zext_add_vec(<2 x i16> %x) {
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; CHECK-LABEL: @add_nuw_zext_add_vec(
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; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i16> [[X:%.*]], <i16 -42, i16 5>
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; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i16> [[ADD]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[EXT]], <i32 356, i32 -12>
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; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[TMP1]], <i32 65850, i32 -7>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%add = add nuw <2 x i16> %x, <i16 -42, i16 5>
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@ -450,6 +450,8 @@ define <2 x i32> @add_nuw_zext_add_vec(<2 x i16> %x) {
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ret <2 x i32> %r
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}
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; Negative test - extra use of the zext means increase of instructions.
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define i64 @add_nuw_zext_add_extra_use_1(i8 %x, i64* %p) {
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; CHECK-LABEL: @add_nuw_zext_add_extra_use_1(
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; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[X:%.*]], 42
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@ -469,8 +471,8 @@ define i64 @add_nuw_zext_add_extra_use_2(i8 %x, i8* %p) {
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; CHECK-LABEL: @add_nuw_zext_add_extra_use_2(
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; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[X:%.*]], 42
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; CHECK-NEXT: store i8 [[ADD]], i8* [[P:%.*]], align 1
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; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[ADD]] to i64
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; CHECK-NEXT: [[R:%.*]] = add nuw nsw i64 [[EXT]], -356
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X]] to i64
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; CHECK-NEXT: [[R:%.*]] = add nuw nsw i64 [[TMP1]], -314
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; CHECK-NEXT: ret i64 [[R]]
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;
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%add = add nuw i8 %x, 42
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