From 4a3760d2ba3026d45f44fe127ac2909371d5ee19 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Wed, 5 Feb 2020 00:12:36 +0100 Subject: [PATCH] [SystemZ] Improve handling of inline asm constraints. The "{=v0}" constraint did not result in the expected error message in the abscence of the vector facility, because 'v0' matches as a string into the AnyRegBitRegClass in common code. This patch adds checks for vector support in case of "{v" and soft-float in case of "{f" to remedy this. Review: Ulrich Weigand. --- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 8 +++++++- llvm/test/CodeGen/SystemZ/soft-float-inline-asm-04.ll | 10 ++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/SystemZ/soft-float-inline-asm-04.ll diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index f2518bb63819..19a1b790e473 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -1163,7 +1163,10 @@ SystemZTargetLowering::getRegForInlineAsmConstraint( return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass, SystemZMC::GR64Regs, 16); } - if (Constraint[1] == 'f' && !useSoftFloat()) { + if (Constraint[1] == 'f') { + if (useSoftFloat()) + return std::make_pair( + 0u, static_cast(nullptr)); if (VT == MVT::f32) return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass, SystemZMC::FP32Regs, 16); @@ -1174,6 +1177,9 @@ SystemZTargetLowering::getRegForInlineAsmConstraint( SystemZMC::FP64Regs, 16); } if (Constraint[1] == 'v') { + if (!Subtarget.hasVector()) + return std::make_pair( + 0u, static_cast(nullptr)); if (VT == MVT::f32) return parseRegisterNumber(Constraint, &SystemZ::VR32BitRegClass, SystemZMC::VR32Regs, 32); diff --git a/llvm/test/CodeGen/SystemZ/soft-float-inline-asm-04.ll b/llvm/test/CodeGen/SystemZ/soft-float-inline-asm-04.ll new file mode 100644 index 000000000000..b11ee8772290 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/soft-float-inline-asm-04.ll @@ -0,0 +1,10 @@ +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=soft-float -O3 2>&1 | FileCheck %s +; +; Verify that inline asms cannot use fp/vector registers with soft-float. + +define <2 x i64> @f1() { + %ret = call <2 x i64> asm "", "={v0}" () + ret <2 x i64> %ret +} + +; CHECK: error: couldn't allocate output register for constraint '{v0}'