forked from OSchip/llvm-project
[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
This is a preliminary patch for fast instruction selection on PowerPC. Code generation can differ between DAG isel and fast isel. Existing tests that specify -O0 were written to expect DAG isel. Make this explicit by adding -fast-isel=false to the tests. In some cases specifying -fast-isel=false produces different code even when there isn't a fast instruction selector specified. This is because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel object exists. Thus disabling fast isel can actually produce less conservative code. Because of this, some of the expected code generation in the -O0 tests needs to be adjusted. In particular, handling of function arguments is less conservative with -fast-isel=false (see isOnlyUsedInEntryBlock() in SelectionDAGBuilder.cpp). This results in fewer stack accesses and, in some cases, reduced stack size as uselessly loaded values are no longer stored back to spill locations in the stack. No functional change with this patch; test case adjustments only. llvm-svn: 183939
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@ -1,4 +1,4 @@
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; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
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; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s
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@ -22,8 +22,8 @@ unequal:
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; CHECK: func1:
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; CHECK: cmpld {{[0-9]+}}, 4, 5
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; CHECK: std 4, -[[OFFSET1:[0-9]+]]
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; CHECK: std 5, -[[OFFSET2:[0-9]+]]
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; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET1]](1)
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; CHECK: ld 3, -[[OFFSET2]](1)
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@ -65,8 +65,8 @@ unequal:
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; CHECK: addi [[REG1:[0-9]+]], 1, 64
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; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
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; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
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; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]]
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; CHECK: std 4, -[[OFFSET2:[0-9]+]]
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; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
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; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
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; CHECK: ld 3, -[[OFFSET2]](1)
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; CHECK: ld 3, -[[OFFSET1]](1)
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
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; This tests correct handling of empty aggregate parameters and return values.
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; An empty parameter passed by value does not consume a protocol register or
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@ -27,7 +27,6 @@ entry:
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; CHECK: callee:
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; CHECK: std 4,
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; CHECK: std 3,
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; CHECK-NOT: std 5,
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; CHECK-NOT: std 6,
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; CHECK: blr
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@ -45,7 +44,6 @@ entry:
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; CHECK: caller:
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; CHECK: addi 4,
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; CHECK: std 3,
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; CHECK-NOT: std 5,
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; CHECK-NOT: std 6,
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; CHECK: bl callee
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@ -1,4 +1,4 @@
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; This verifies that single-precision floating point values that can't
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; be passed in registers are stored in the rightmost word of the parameter
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
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; This tests receiving and re-passing parameters consisting of structures
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; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
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ret void
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}
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; CHECK: std 6, 216(1)
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; CHECK: std 5, 208(1)
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; CHECK: std 4, 200(1)
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; CHECK: std 3, 192(1)
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; CHECK: lbz {{[0-9]+}}, 199(1)
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; CHECK: lhz {{[0-9]+}}, 197(1)
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; CHECK: std 6, 184(1)
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; CHECK: std 5, 176(1)
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; CHECK: std 4, 168(1)
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; CHECK: std 3, 160(1)
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; CHECK: lbz {{[0-9]+}}, 167(1)
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; CHECK: lhz {{[0-9]+}}, 165(1)
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; CHECK: stb {{[0-9]+}}, 55(1)
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; CHECK: sth {{[0-9]+}}, 53(1)
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; CHECK: lbz {{[0-9]+}}, 207(1)
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; CHECK: lwz {{[0-9]+}}, 203(1)
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; CHECK: lbz {{[0-9]+}}, 175(1)
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; CHECK: lwz {{[0-9]+}}, 171(1)
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; CHECK: stb {{[0-9]+}}, 63(1)
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; CHECK: stw {{[0-9]+}}, 59(1)
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; CHECK: lhz {{[0-9]+}}, 214(1)
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; CHECK: lwz {{[0-9]+}}, 210(1)
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; CHECK: lhz {{[0-9]+}}, 182(1)
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; CHECK: lwz {{[0-9]+}}, 178(1)
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; CHECK: sth {{[0-9]+}}, 70(1)
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; CHECK: stw {{[0-9]+}}, 66(1)
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; CHECK: lbz {{[0-9]+}}, 223(1)
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; CHECK: lhz {{[0-9]+}}, 221(1)
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; CHECK: lwz {{[0-9]+}}, 217(1)
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; CHECK: lbz {{[0-9]+}}, 191(1)
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; CHECK: lhz {{[0-9]+}}, 189(1)
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; CHECK: lwz {{[0-9]+}}, 185(1)
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; CHECK: stb {{[0-9]+}}, 79(1)
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; CHECK: sth {{[0-9]+}}, 77(1)
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; CHECK: stw {{[0-9]+}}, 73(1)
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@ -1,5 +1,5 @@
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; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
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; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
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; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
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; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
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; Test correct code generation for medium and large code model
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; for loading a value from the constant pool (TOC-relative).
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@ -1,6 +1,6 @@
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; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
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; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
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; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
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; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
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; FIXME: When asm-parse is available, could make this an assembly test.
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
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; Verify internal alignment of long double in a struct. The double
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; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,5 +1,5 @@
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; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
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; This verifies that we generate correct spill/reload code for vector regs.
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ret void
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}
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; CHECK: stvx 2, 1,
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; CHECK: lvx 2, 1,
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; CHECK: stvx 2,
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declare void @foo(i32*)
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