forked from OSchip/llvm-project
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 295773
This commit is contained in:
Eugene Zelenko
parent
f9e8034c9c
commit
49e2fc4f5f
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@ -49,54 +49,59 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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namespace llvm {
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class InstrItineraryData;
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class AnalysisUsage;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineLoop;
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class MachineLoopInfo;
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class MachineRegisterInfo;
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struct MCSchedClassDesc;
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class raw_ostream;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class raw_ostream;
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class MachineTraceMetrics : public MachineFunctionPass {
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const MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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const MachineLoopInfo *Loops;
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const MachineFunction *MF = nullptr;
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const TargetInstrInfo *TII = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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const MachineRegisterInfo *MRI = nullptr;
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const MachineLoopInfo *Loops = nullptr;
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TargetSchedModel SchedModel;
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public:
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friend class Ensemble;
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friend class Trace;
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class Ensemble;
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class Trace;
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static char ID;
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MachineTraceMetrics();
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void getAnalysisUsage(AnalysisUsage&) const override;
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bool runOnMachineFunction(MachineFunction&) override;
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void releaseMemory() override;
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void verifyAnalysis() const override;
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friend class Ensemble;
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friend class Trace;
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/// Per-basic block information that doesn't depend on the trace through the
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/// block.
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struct FixedBlockInfo {
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/// The number of non-trivial instructions in the block.
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/// Doesn't count PHI and COPY instructions that are likely to be removed.
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unsigned InstrCount;
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unsigned InstrCount = ~0u;
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/// True when the block contains calls.
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bool HasCalls;
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bool HasCalls = false;
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FixedBlockInfo() : InstrCount(~0u), HasCalls(false) {}
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FixedBlockInfo() = default;
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/// Returns true when resource information for this block has been computed.
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bool hasResources() const { return InstrCount != ~0u; }
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@ -134,11 +139,11 @@ public:
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struct TraceBlockInfo {
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/// Trace predecessor, or NULL for the first block in the trace.
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/// Valid when hasValidDepth().
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const MachineBasicBlock *Pred;
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const MachineBasicBlock *Pred = nullptr;
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/// Trace successor, or NULL for the last block in the trace.
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/// Valid when hasValidHeight().
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const MachineBasicBlock *Succ;
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const MachineBasicBlock *Succ = nullptr;
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/// The block number of the head of the trace. (When hasValidDepth()).
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unsigned Head;
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@ -148,16 +153,13 @@ public:
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/// Accumulated number of instructions in the trace above this block.
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/// Does not include instructions in this block.
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unsigned InstrDepth;
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unsigned InstrDepth = ~0u;
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/// Accumulated number of instructions in the trace below this block.
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/// Includes instructions in this block.
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unsigned InstrHeight;
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unsigned InstrHeight = ~0u;
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TraceBlockInfo() :
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Pred(nullptr), Succ(nullptr),
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InstrDepth(~0u), InstrHeight(~0u),
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HasValidInstrDepths(false), HasValidInstrHeights(false) {}
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TraceBlockInfo() = default;
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/// Returns true if the depth resources have been computed from the trace
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/// above this block.
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@ -199,10 +201,10 @@ public:
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// itinerary data.
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/// Instruction depths have been computed. This implies hasValidDepth().
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bool HasValidInstrDepths;
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bool HasValidInstrDepths = false;
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/// Instruction heights have been computed. This implies hasValidHeight().
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bool HasValidInstrHeights;
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bool HasValidInstrHeights = false;
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/// Critical path length. This is the number of cycles in the longest data
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/// dependency chain through the trace. This is only valid when both
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@ -242,6 +244,7 @@ public:
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public:
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explicit Trace(Ensemble &te, TraceBlockInfo &tbi) : TE(te), TBI(tbi) {}
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void print(raw_ostream&) const;
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/// Compute the total number of instructions in the trace.
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@ -300,11 +303,12 @@ public:
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/// strategy, for example 'minimum resource height'. There is one trace for
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/// every block in the function.
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class Ensemble {
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friend class Trace;
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SmallVector<TraceBlockInfo, 4> BlockInfo;
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DenseMap<const MachineInstr*, InstrCycles> Cycles;
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SmallVector<unsigned, 0> ProcResourceDepths;
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SmallVector<unsigned, 0> ProcResourceHeights;
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friend class Trace;
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void computeTrace(const MachineBasicBlock*);
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void computeDepthResources(const MachineBasicBlock*);
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@ -317,9 +321,11 @@ public:
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protected:
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MachineTraceMetrics &MTM;
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explicit Ensemble(MachineTraceMetrics*);
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virtual const MachineBasicBlock *pickTracePred(const MachineBasicBlock*) =0;
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virtual const MachineBasicBlock *pickTraceSucc(const MachineBasicBlock*) =0;
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explicit Ensemble(MachineTraceMetrics*);
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const MachineLoop *getLoopFor(const MachineBasicBlock*) const;
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const TraceBlockInfo *getDepthResources(const MachineBasicBlock*) const;
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const TraceBlockInfo *getHeightResources(const MachineBasicBlock*) const;
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@ -328,7 +334,8 @@ public:
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public:
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virtual ~Ensemble();
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virtual const char *getName() const =0;
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virtual const char *getName() const = 0;
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void print(raw_ostream&) const;
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void invalidate(const MachineBasicBlock *MBB);
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void verify() const;
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@ -394,6 +401,7 @@ inline raw_ostream &operator<<(raw_ostream &OS,
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En.print(OS);
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return OS;
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}
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} // end namespace llvm
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#endif
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#endif // LLVM_CODEGEN_MACHINETRACEMETRICS_H
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@ -1,4 +1,4 @@
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//===-- RegAllocPBQP.h ------------------------------------------*- C++ -*-===//
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//===- RegAllocPBQP.h -------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -16,15 +16,28 @@
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#ifndef LLVM_CODEGEN_REGALLOCPBQP_H
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#define LLVM_CODEGEN_REGALLOCPBQP_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Hashing.h"
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#include "llvm/CodeGen/PBQP/CostAllocator.h"
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#include "llvm/CodeGen/PBQP/Graph.h"
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#include "llvm/CodeGen/PBQP/Math.h"
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#include "llvm/CodeGen/PBQP/ReductionRules.h"
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#include "llvm/CodeGen/PBQPRAConstraint.h"
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#include "llvm/CodeGen/PBQP/Solution.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <algorithm>
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#include <cassert>
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#include <cstddef>
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#include <limits>
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#include <memory>
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#include <set>
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#include <vector>
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namespace llvm {
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class FunctionPass;
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class LiveIntervals;
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class MachineBlockFrequencyInfo;
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class MachineFunction;
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class raw_ostream;
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namespace PBQP {
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@ -37,15 +50,10 @@ inline unsigned getSpillOptionIdx() { return 0; }
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///
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/// Keeps track of the number of infinities in each row and column.
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class MatrixMetadata {
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private:
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MatrixMetadata(const MatrixMetadata&);
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void operator=(const MatrixMetadata&);
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public:
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MatrixMetadata(const Matrix& M)
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: WorstRow(0), WorstCol(0),
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UnsafeRows(new bool[M.getRows() - 1]()),
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: UnsafeRows(new bool[M.getRows() - 1]()),
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UnsafeCols(new bool[M.getCols() - 1]()) {
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unsigned* ColCounts = new unsigned[M.getCols() - 1]();
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for (unsigned i = 1; i < M.getRows(); ++i) {
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@ -66,13 +74,17 @@ public:
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delete[] ColCounts;
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}
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MatrixMetadata(const MatrixMetadata &) = delete;
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MatrixMetadata &operator=(const MatrixMetadata &) = delete;
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unsigned getWorstRow() const { return WorstRow; }
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unsigned getWorstCol() const { return WorstCol; }
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const bool* getUnsafeRows() const { return UnsafeRows.get(); }
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const bool* getUnsafeCols() const { return UnsafeCols.get(); }
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private:
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unsigned WorstRow, WorstCol;
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unsigned WorstRow = 0;
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unsigned WorstCol = 0;
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std::unique_ptr<bool[]> UnsafeRows;
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std::unique_ptr<bool[]> UnsafeCols;
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};
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@ -80,17 +92,16 @@ private:
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/// \brief Holds a vector of the allowed physical regs for a vreg.
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class AllowedRegVector {
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friend hash_code hash_value(const AllowedRegVector &);
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public:
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AllowedRegVector() : NumOpts(0), Opts(nullptr) {}
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public:
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AllowedRegVector() = default;
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AllowedRegVector(AllowedRegVector &&) = default;
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AllowedRegVector(const std::vector<unsigned> &OptVec)
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: NumOpts(OptVec.size()), Opts(new unsigned[NumOpts]) {
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std::copy(OptVec.begin(), OptVec.end(), Opts.get());
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}
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AllowedRegVector(AllowedRegVector &&) = default;
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unsigned size() const { return NumOpts; }
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unsigned operator[](size_t I) const { return Opts[I]; }
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@ -105,7 +116,7 @@ public:
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}
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private:
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unsigned NumOpts;
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unsigned NumOpts = 0;
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std::unique_ptr<unsigned[]> Opts;
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};
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class GraphMetadata {
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private:
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typedef ValuePool<AllowedRegVector> AllowedRegVecPool;
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public:
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public:
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typedef AllowedRegVecPool::PoolRef AllowedRegVecRef;
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GraphMetadata(MachineFunction &MF,
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@ -168,13 +179,7 @@ public:
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OptimallyReducible
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} ReductionState;
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NodeMetadata()
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: RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr),
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VReg(0)
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#ifndef NDEBUG
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, everConservativelyAllocatable(false)
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#endif
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{}
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NodeMetadata() = default;
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NodeMetadata(const NodeMetadata &Other)
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: RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
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@ -190,9 +195,8 @@ public:
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}
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}
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NodeMetadata(NodeMetadata &&Other) = default;
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NodeMetadata& operator=(NodeMetadata &&Other) = default;
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NodeMetadata(NodeMetadata &&) = default;
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NodeMetadata& operator=(NodeMetadata &&) = default;
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void setVReg(unsigned VReg) { this->VReg = VReg; }
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unsigned getVReg() const { return VReg; }
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@ -249,21 +253,22 @@ public:
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#endif
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private:
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ReductionState RS;
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unsigned NumOpts;
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unsigned DeniedOpts;
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ReductionState RS = Unprocessed;
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unsigned NumOpts = 0;
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unsigned DeniedOpts = 0;
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std::unique_ptr<unsigned[]> OptUnsafeEdges;
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unsigned VReg;
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unsigned VReg = 0;
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GraphMetadata::AllowedRegVecRef AllowedRegs;
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#ifndef NDEBUG
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bool everConservativelyAllocatable;
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bool everConservativelyAllocatable = false;
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#endif
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};
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class RegAllocSolverImpl {
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private:
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typedef MDMatrix<MatrixMetadata> RAMatrix;
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public:
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typedef PBQP::Vector RawVector;
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typedef PBQP::Matrix RawMatrix;
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@ -296,6 +301,7 @@ public:
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"PBQP Graph should not contain single or zero-option nodes");
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G.getNodeMetadata(NId).setup(G.getNodeCosts(NId));
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}
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void handleRemoveNode(NodeId NId) {}
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void handleSetNodeCosts(NodeId NId, const Vector& newCosts) {}
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@ -342,7 +348,6 @@ public:
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}
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private:
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void promote(NodeId NId, NodeMetadata& NMd) {
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if (G.getNodeDegree(NId) == 3) {
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// This node is becoming optimally reducible.
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@ -474,6 +479,7 @@ private:
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class SpillCostComparator {
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public:
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SpillCostComparator(const Graph& G) : G(G) {}
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bool operator()(NodeId N1Id, NodeId N2Id) {
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PBQPNum N1SC = G.getNodeCosts(N1Id)[0];
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PBQPNum N2SC = G.getNodeCosts(N2Id)[0];
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@ -481,6 +487,7 @@ private:
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return G.getNodeDegree(N1Id) < G.getNodeDegree(N2Id);
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return N1SC < N2SC;
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}
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private:
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const Graph& G;
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};
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@ -495,6 +502,7 @@ private:
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class PBQPRAGraph : public PBQP::Graph<RegAllocSolverImpl> {
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private:
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typedef PBQP::Graph<RegAllocSolverImpl> BaseT;
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public:
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PBQPRAGraph(GraphMetadata Metadata) : BaseT(std::move(Metadata)) {}
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@ -517,13 +525,13 @@ inline Solution solve(PBQPRAGraph& G) {
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return RegAllocSolver.solve();
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}
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} // namespace RegAlloc
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} // namespace PBQP
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} // end namespace RegAlloc
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} // end namespace PBQP
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/// @brief Create a PBQP register allocator instance.
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FunctionPass *
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createPBQPRegisterAllocator(char *customPassID = nullptr);
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} // namespace llvm
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} // end namespace llvm
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#endif /* LLVM_CODEGEN_REGALLOCPBQP_H */
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#endif // LLVM_CODEGEN_REGALLOCPBQP_H
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@ -1,4 +1,4 @@
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//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
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//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -19,22 +19,25 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class RegisterClassInfo {
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struct RCInfo {
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unsigned Tag;
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unsigned NumRegs;
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bool ProperSubClass;
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uint8_t MinCost;
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uint16_t LastCostChange;
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unsigned Tag = 0;
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unsigned NumRegs = 0;
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bool ProperSubClass = false;
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uint8_t MinCost = 0;
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uint16_t LastCostChange = 0;
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std::unique_ptr<MCPhysReg[]> Order;
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RCInfo()
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: Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
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LastCostChange(0) {}
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RCInfo() = default;
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operator ArrayRef<MCPhysReg>() const {
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return makeArrayRef(Order.get(), NumRegs);
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@ -46,14 +49,14 @@ class RegisterClassInfo {
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// Tag changes whenever cached information needs to be recomputed. An RCInfo
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// entry is valid when its tag matches.
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unsigned Tag;
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unsigned Tag = 0;
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const MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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const MachineFunction *MF = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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// Callee saved registers of last MF. Assumed to be valid until the next
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// runOnFunction() call.
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const MCPhysReg *CalleeSaved;
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const MCPhysReg *CalleeSaved = nullptr;
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// Map register number to CalleeSaved index + 1;
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SmallVector<uint8_t, 4> CSRNum;
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@ -140,6 +143,7 @@ public:
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protected:
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unsigned computePSetLimit(unsigned Idx) const;
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};
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} // end namespace llvm
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#endif
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#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
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@ -1,4 +1,4 @@
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//===-- RegisterPressure.h - Dynamic Register Pressure -*- C++ -*-------===//
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//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -15,16 +15,25 @@
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#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
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#define LLVM_CODEGEN_REGISTERPRESSURE_H
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#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/SparseSet.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/MC/LaneBitmask.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include <cassert>
|
||||
#include <cstddef>
|
||||
#include <cstdint>
|
||||
#include <cstdlib>
|
||||
#include <limits>
|
||||
#include <vector>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class LiveIntervals;
|
||||
class LiveRange;
|
||||
class RegisterClassInfo;
|
||||
class MachineInstr;
|
||||
class RegisterClassInfo;
|
||||
|
||||
struct RegisterMaskPair {
|
||||
unsigned RegUnit; ///< Virtual register or register unit.
|
||||
|
|
@ -91,12 +100,13 @@ struct RegionPressure : RegisterPressure {
|
|||
/// higher level assert that pressure is consistent within a region. We also
|
||||
/// effectively ignore dead defs which don't affect heuristics much.
|
||||
class PressureChange {
|
||||
uint16_t PSetID; // ID+1. 0=Invalid.
|
||||
int16_t UnitInc;
|
||||
uint16_t PSetID = 0; // ID+1. 0=Invalid.
|
||||
int16_t UnitInc = 0;
|
||||
|
||||
public:
|
||||
PressureChange(): PSetID(0), UnitInc(0) {}
|
||||
PressureChange(unsigned id): PSetID(id+1), UnitInc(0) {
|
||||
assert(id < UINT16_MAX && "PSetID overflow.");
|
||||
PressureChange() = default;
|
||||
PressureChange(unsigned id): PSetID(id + 1) {
|
||||
assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
|
||||
}
|
||||
|
||||
bool isValid() const { return PSetID > 0; }
|
||||
|
|
@ -105,8 +115,11 @@ public:
|
|||
assert(isValid() && "invalid PressureChange");
|
||||
return PSetID - 1;
|
||||
}
|
||||
|
||||
// If PSetID is invalid, return UINT16_MAX to give it lowest priority.
|
||||
unsigned getPSetOrMax() const { return (PSetID - 1) & UINT16_MAX; }
|
||||
unsigned getPSetOrMax() const {
|
||||
return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
|
||||
}
|
||||
|
||||
int getUnitInc() const { return UnitInc; }
|
||||
|
||||
|
|
@ -182,11 +195,12 @@ public:
|
|||
|
||||
/// Array of PressureDiffs.
|
||||
class PressureDiffs {
|
||||
PressureDiff *PDiffArray;
|
||||
unsigned Size;
|
||||
unsigned Max;
|
||||
PressureDiff *PDiffArray = nullptr;
|
||||
unsigned Size = 0;
|
||||
unsigned Max = 0;
|
||||
|
||||
public:
|
||||
PressureDiffs(): PDiffArray(nullptr), Size(0), Max(0) {}
|
||||
PressureDiffs() = default;
|
||||
~PressureDiffs() { free(PDiffArray); }
|
||||
|
||||
void clear() { Size = 0; }
|
||||
|
|
@ -200,6 +214,7 @@ public:
|
|||
const PressureDiff &operator[](unsigned Idx) const {
|
||||
return const_cast<PressureDiffs*>(this)->operator[](Idx);
|
||||
}
|
||||
|
||||
/// \brief Record pressure difference induced by the given operand list to
|
||||
/// node with index \p Idx.
|
||||
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
|
||||
|
|
@ -225,7 +240,7 @@ struct RegPressureDelta {
|
|||
PressureChange CriticalMax;
|
||||
PressureChange CurrentMax;
|
||||
|
||||
RegPressureDelta() {}
|
||||
RegPressureDelta() = default;
|
||||
|
||||
bool operator==(const RegPressureDelta &RHS) const {
|
||||
return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
|
||||
|
|
@ -264,6 +279,7 @@ private:
|
|||
assert(Reg < NumRegUnits);
|
||||
return Reg;
|
||||
}
|
||||
|
||||
unsigned getRegFromSparseIndex(unsigned SparseIndex) const {
|
||||
if (SparseIndex >= NumRegUnits)
|
||||
return TargetRegisterInfo::index2VirtReg(SparseIndex-NumRegUnits);
|
||||
|
|
@ -338,14 +354,14 @@ public:
|
|||
/// tracking. Changing direction has the side effect of closing region, and
|
||||
/// traversing past TopIdx or BottomIdx reopens it.
|
||||
class RegPressureTracker {
|
||||
const MachineFunction *MF;
|
||||
const TargetRegisterInfo *TRI;
|
||||
const RegisterClassInfo *RCI;
|
||||
const MachineFunction *MF = nullptr;
|
||||
const TargetRegisterInfo *TRI = nullptr;
|
||||
const RegisterClassInfo *RCI = nullptr;
|
||||
const MachineRegisterInfo *MRI;
|
||||
const LiveIntervals *LIS;
|
||||
const LiveIntervals *LIS = nullptr;
|
||||
|
||||
/// We currently only allow pressure tracking within a block.
|
||||
const MachineBasicBlock *MBB;
|
||||
const MachineBasicBlock *MBB = nullptr;
|
||||
|
||||
/// Track the max pressure within the region traversed so far.
|
||||
RegisterPressure &P;
|
||||
|
|
@ -355,10 +371,10 @@ class RegPressureTracker {
|
|||
bool RequireIntervals;
|
||||
|
||||
/// True if UntiedDefs will be populated.
|
||||
bool TrackUntiedDefs;
|
||||
bool TrackUntiedDefs = false;
|
||||
|
||||
/// True if lanemasks should be tracked.
|
||||
bool TrackLaneMasks;
|
||||
bool TrackLaneMasks = false;
|
||||
|
||||
/// Register pressure corresponds to liveness before this instruction
|
||||
/// iterator. It may point to the end of the block or a DebugValue rather than
|
||||
|
|
@ -377,13 +393,8 @@ class RegPressureTracker {
|
|||
std::vector<unsigned> LiveThruPressure;
|
||||
|
||||
public:
|
||||
RegPressureTracker(IntervalPressure &rp) :
|
||||
MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
|
||||
RequireIntervals(true), TrackUntiedDefs(false), TrackLaneMasks(false) {}
|
||||
|
||||
RegPressureTracker(RegionPressure &rp) :
|
||||
MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
|
||||
RequireIntervals(false), TrackUntiedDefs(false), TrackLaneMasks(false) {}
|
||||
RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
|
||||
RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
|
||||
|
||||
void reset();
|
||||
|
||||
|
|
@ -555,6 +566,7 @@ protected:
|
|||
|
||||
void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
|
||||
const TargetRegisterInfo *TRI);
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_CODEGEN_REGISTERPRESSURE_H
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- RegisterScavenging.h - Machine register scavenging ------*- C++ -*-===//
|
||||
//===- RegisterScavenging.h - Machine register scavenging -------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -19,41 +19,43 @@
|
|||
#define LLVM_CODEGEN_REGISTERSCAVENGING_H
|
||||
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/LiveRegUnits.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/MC/LaneBitmask.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineRegisterInfo;
|
||||
class TargetRegisterInfo;
|
||||
class MachineInstr;
|
||||
class TargetInstrInfo;
|
||||
class TargetRegisterClass;
|
||||
class TargetRegisterInfo;
|
||||
|
||||
class RegScavenger {
|
||||
const TargetRegisterInfo *TRI;
|
||||
const TargetInstrInfo *TII;
|
||||
MachineRegisterInfo* MRI;
|
||||
MachineBasicBlock *MBB;
|
||||
MachineBasicBlock *MBB = nullptr;
|
||||
MachineBasicBlock::iterator MBBI;
|
||||
unsigned NumRegUnits;
|
||||
unsigned NumRegUnits = 0;
|
||||
|
||||
/// True if RegScavenger is currently tracking the liveness of registers.
|
||||
bool Tracking;
|
||||
bool Tracking = false;
|
||||
|
||||
/// Information on scavenged registers (held in a spill slot).
|
||||
struct ScavengedInfo {
|
||||
ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
|
||||
ScavengedInfo(int FI = -1) : FrameIndex(FI) {}
|
||||
|
||||
/// A spill slot used for scavenging a register post register allocation.
|
||||
int FrameIndex;
|
||||
|
||||
/// If non-zero, the specific register is currently being
|
||||
/// scavenged. That is, it is spilled to this scavenging stack slot.
|
||||
unsigned Reg;
|
||||
unsigned Reg = 0;
|
||||
|
||||
/// The instruction that restores the scavenged register from stack.
|
||||
const MachineInstr *Restore;
|
||||
const MachineInstr *Restore = nullptr;
|
||||
};
|
||||
|
||||
/// A vector of information on scavenged registers.
|
||||
|
|
@ -67,8 +69,7 @@ class RegScavenger {
|
|||
BitVector TmpRegUnits;
|
||||
|
||||
public:
|
||||
RegScavenger()
|
||||
: MBB(nullptr), NumRegUnits(0), Tracking(false) {}
|
||||
RegScavenger() = default;
|
||||
|
||||
/// Start tracking liveness from the begin of basic block \p MBB.
|
||||
void enterBasicBlock(MachineBasicBlock &MBB);
|
||||
|
|
@ -163,6 +164,7 @@ public:
|
|||
|
||||
/// Tell the scavenger a register is used.
|
||||
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
|
||||
|
||||
private:
|
||||
/// Returns true if a register is reserved. It is never "unused".
|
||||
bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
|
||||
|
|
@ -202,6 +204,6 @@ private:
|
|||
void setLiveInsUsed(const MachineBasicBlock &MBB);
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_CODEGEN_REGISTERSCAVENGING_H
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- lib/CodeGen/MachineTraceMetrics.cpp ----------------------*- C++ -*-===//
|
||||
//===- lib/CodeGen/MachineTraceMetrics.cpp --------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -7,21 +7,35 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/CodeGen/MachineTraceMetrics.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/Optional.h"
|
||||
#include "llvm/ADT/PostOrderIterator.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/SparseSet.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/MC/MCSubtargetInfo.h"
|
||||
#include "llvm/CodeGen/MachineTraceMetrics.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <iterator>
|
||||
#include <tuple>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
|
|
@ -37,9 +51,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
|
|||
INITIALIZE_PASS_END(MachineTraceMetrics,
|
||||
"machine-trace-metrics", "Machine Trace Metrics", false, true)
|
||||
|
||||
MachineTraceMetrics::MachineTraceMetrics()
|
||||
: MachineFunctionPass(ID), MF(nullptr), TII(nullptr), TRI(nullptr),
|
||||
MRI(nullptr), Loops(nullptr) {
|
||||
MachineTraceMetrics::MachineTraceMetrics() : MachineFunctionPass(ID) {
|
||||
std::fill(std::begin(Ensembles), std::end(Ensembles), nullptr);
|
||||
}
|
||||
|
||||
|
|
@ -137,7 +149,6 @@ MachineTraceMetrics::getProcResourceCycles(unsigned MBBNum) const {
|
|||
return makeArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Ensemble utility functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -151,7 +162,7 @@ MachineTraceMetrics::Ensemble::Ensemble(MachineTraceMetrics *ct)
|
|||
}
|
||||
|
||||
// Virtual destructor serves as an anchor.
|
||||
MachineTraceMetrics::Ensemble::~Ensemble() {}
|
||||
MachineTraceMetrics::Ensemble::~Ensemble() = default;
|
||||
|
||||
const MachineLoop*
|
||||
MachineTraceMetrics::Ensemble::getLoopFor(const MachineBasicBlock *MBB) const {
|
||||
|
|
@ -297,6 +308,7 @@ static bool isExitingLoop(const MachineLoop *From, const MachineLoop *To) {
|
|||
// MinInstrCountEnsemble - Pick the trace that executes the least number of
|
||||
// instructions.
|
||||
namespace {
|
||||
|
||||
class MinInstrCountEnsemble : public MachineTraceMetrics::Ensemble {
|
||||
const char *getName() const override { return "MinInstr"; }
|
||||
const MachineBasicBlock *pickTracePred(const MachineBasicBlock*) override;
|
||||
|
|
@ -306,7 +318,8 @@ public:
|
|||
MinInstrCountEnsemble(MachineTraceMetrics *mtm)
|
||||
: MachineTraceMetrics::Ensemble(mtm) {}
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
// Select the preferred predecessor for MBB.
|
||||
const MachineBasicBlock*
|
||||
|
|
@ -409,25 +422,30 @@ void MachineTraceMetrics::verifyAnalysis() const {
|
|||
// revisit blocks.
|
||||
|
||||
namespace {
|
||||
|
||||
struct LoopBounds {
|
||||
MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> Blocks;
|
||||
SmallPtrSet<const MachineBasicBlock*, 8> Visited;
|
||||
const MachineLoopInfo *Loops;
|
||||
bool Downward;
|
||||
bool Downward = false;
|
||||
|
||||
LoopBounds(MutableArrayRef<MachineTraceMetrics::TraceBlockInfo> blocks,
|
||||
const MachineLoopInfo *loops)
|
||||
: Blocks(blocks), Loops(loops), Downward(false) {}
|
||||
const MachineLoopInfo *loops) : Blocks(blocks), Loops(loops) {}
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
// Specialize po_iterator_storage in order to prune the post-order traversal so
|
||||
// it is limited to the current loop and doesn't traverse the loop back edges.
|
||||
namespace llvm {
|
||||
|
||||
template<>
|
||||
class po_iterator_storage<LoopBounds, true> {
|
||||
LoopBounds &LB;
|
||||
|
||||
public:
|
||||
po_iterator_storage(LoopBounds &lb) : LB(lb) {}
|
||||
|
||||
void finishPostorder(const MachineBasicBlock*) {}
|
||||
|
||||
bool insertEdge(Optional<const MachineBasicBlock *> From,
|
||||
|
|
@ -452,7 +470,8 @@ public:
|
|||
return LB.Visited.insert(To).second;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
/// Compute the trace through MBB.
|
||||
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
|
||||
|
|
@ -603,6 +622,7 @@ void MachineTraceMetrics::Ensemble::verify() const {
|
|||
// A data dependency is represented as a defining MI and operand numbers on the
|
||||
// defining and using MI.
|
||||
namespace {
|
||||
|
||||
struct DataDep {
|
||||
const MachineInstr *DefMI;
|
||||
unsigned DefOp;
|
||||
|
|
@ -622,7 +642,8 @@ struct DataDep {
|
|||
assert((++DefI).atEnd() && "Register has multiple defs");
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
// Get the input data dependencies that must be ready before UseMI can issue.
|
||||
// Return true if UseMI has any physreg operands.
|
||||
|
|
@ -678,17 +699,19 @@ static void getPHIDeps(const MachineInstr &UseMI,
|
|||
// direction instructions are scanned, it could be the operand that defined the
|
||||
// regunit, or the highest operand to read the regunit.
|
||||
namespace {
|
||||
|
||||
struct LiveRegUnit {
|
||||
unsigned RegUnit;
|
||||
unsigned Cycle;
|
||||
const MachineInstr *MI;
|
||||
unsigned Op;
|
||||
unsigned Cycle = 0;
|
||||
const MachineInstr *MI = nullptr;
|
||||
unsigned Op = 0;
|
||||
|
||||
unsigned getSparseSetIndex() const { return RegUnit; }
|
||||
|
||||
LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
|
||||
LiveRegUnit(unsigned RU) : RegUnit(RU) {}
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
// Identify physreg dependencies for UseMI, and update the live regunit
|
||||
// tracking set when scanning instructions downwards.
|
||||
|
|
@ -922,7 +945,6 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
|
|||
return Height;
|
||||
}
|
||||
|
||||
|
||||
typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
|
||||
|
||||
// Push the height of DefMI upwards if required to match UseMI.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
|
||||
//===- RegAllocPBQP.cpp ---- PBQP Register Allocator ----------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -29,34 +29,61 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/CodeGen/RegAllocPBQP.h"
|
||||
#include "RegisterCoalescer.h"
|
||||
#include "Spiller.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/DenseSet.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/Analysis/AliasAnalysis.h"
|
||||
#include "llvm/CodeGen/CalcSpillWeights.h"
|
||||
#include "llvm/CodeGen/LiveInterval.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/CodeGen/LiveRangeEdit.h"
|
||||
#include "llvm/CodeGen/LiveStackAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
|
||||
#include "llvm/CodeGen/MachineDominators.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/PBQP/Graph.h"
|
||||
#include "llvm/CodeGen/PBQP/Solution.h"
|
||||
#include "llvm/CodeGen/PBQPRAConstraint.h"
|
||||
#include "llvm/CodeGen/RegAllocPBQP.h"
|
||||
#include "llvm/CodeGen/RegAllocRegistry.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/CodeGen/VirtRegMap.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Module.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/FileSystem.h"
|
||||
#include "llvm/Support/Printable.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstddef>
|
||||
#include <limits>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
#include <queue>
|
||||
#include <set>
|
||||
#include <sstream>
|
||||
#include <string>
|
||||
#include <system_error>
|
||||
#include <tuple>
|
||||
#include <vector>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
|
|
@ -86,7 +113,6 @@ namespace {
|
|||
/// Programming problems.
|
||||
class RegAllocPBQP : public MachineFunctionPass {
|
||||
public:
|
||||
|
||||
static char ID;
|
||||
|
||||
/// Construct a PBQP register allocator.
|
||||
|
|
@ -113,7 +139,6 @@ public:
|
|||
}
|
||||
|
||||
private:
|
||||
|
||||
typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
|
||||
typedef std::vector<const LiveInterval*> Node2LIMap;
|
||||
typedef std::vector<unsigned> AllowedSet;
|
||||
|
|
@ -187,7 +212,6 @@ public:
|
|||
/// @brief Add interference edges between overlapping vregs.
|
||||
class Interference : public PBQPRAConstraint {
|
||||
private:
|
||||
|
||||
typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
|
||||
typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
|
||||
typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
|
||||
|
|
@ -276,7 +300,6 @@ private:
|
|||
}
|
||||
|
||||
public:
|
||||
|
||||
void apply(PBQPRAGraph &G) override {
|
||||
// The following is loosely based on the linear scan algorithm introduced in
|
||||
// "Linear Scan Register Allocation" by Poletto and Sarkar. This version
|
||||
|
|
@ -363,7 +386,6 @@ public:
|
|||
}
|
||||
|
||||
private:
|
||||
|
||||
// Create an Interference edge and add it to the graph, unless it is
|
||||
// a null matrix, meaning the nodes' allowed registers do not have any
|
||||
// interference. This case occurs frequently between integer and floating
|
||||
|
|
@ -372,7 +394,6 @@ private:
|
|||
bool createInterferenceEdge(PBQPRAGraph &G,
|
||||
PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
|
||||
IMatrixCache &C) {
|
||||
|
||||
const TargetRegisterInfo &TRI =
|
||||
*G.getMetadata().MF.getSubtarget().getRegisterInfo();
|
||||
const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
|
||||
|
|
@ -409,7 +430,6 @@ private:
|
|||
}
|
||||
};
|
||||
|
||||
|
||||
class Coalescing : public PBQPRAConstraint {
|
||||
public:
|
||||
void apply(PBQPRAGraph &G) override {
|
||||
|
|
@ -421,7 +441,6 @@ public:
|
|||
// gives the Ok.
|
||||
for (const auto &MBB : MF) {
|
||||
for (const auto &MI : MBB) {
|
||||
|
||||
// Skip not-coalescable or already coalesced copies.
|
||||
if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
|
||||
continue;
|
||||
|
|
@ -479,7 +498,6 @@ public:
|
|||
}
|
||||
|
||||
private:
|
||||
|
||||
void addVirtRegCoalesce(
|
||||
PBQPRAGraph::RawMatrix &CostMat,
|
||||
const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
|
||||
|
|
@ -496,14 +514,15 @@ private:
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
} // End anonymous namespace.
|
||||
} // end anonymous namespace
|
||||
|
||||
// Out-of-line destructor/anchor for PBQPRAConstraint.
|
||||
PBQPRAConstraint::~PBQPRAConstraint() {}
|
||||
PBQPRAConstraint::~PBQPRAConstraint() = default;
|
||||
|
||||
void PBQPRAConstraint::anchor() {}
|
||||
|
||||
void PBQPRAConstraintList::anchor() {}
|
||||
|
||||
void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
|
||||
|
|
@ -777,7 +796,6 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
|
|||
|
||||
// If there are non-empty intervals allocate them using pbqp.
|
||||
if (!VRegsToAlloc.empty()) {
|
||||
|
||||
const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
|
||||
std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
|
||||
llvm::make_unique<PBQPRAConstraintList>();
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
|
||||
//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -14,12 +14,21 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/CodeGen/RegisterClassInfo.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/RegisterClassInfo.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
|
|
@ -29,8 +38,7 @@ static cl::opt<unsigned>
|
|||
StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
|
||||
cl::desc("Limit all regclasses to N registers"));
|
||||
|
||||
RegisterClassInfo::RegisterClassInfo()
|
||||
: Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
|
||||
RegisterClassInfo::RegisterClassInfo() = default;
|
||||
|
||||
void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
|
||||
bool Update = false;
|
||||
|
|
@ -114,7 +122,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
|
|||
}
|
||||
}
|
||||
RCI.NumRegs = N + CSRAlias.size();
|
||||
assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
||||
assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
||||
|
||||
// CSR aliases go after the volatile registers, preserve the target's order.
|
||||
for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- RegisterPressure.cpp - Dynamic Register Pressure ------------------===//
|
||||
//===- RegisterPressure.cpp - Dynamic Register Pressure -------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -12,13 +12,37 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/CodeGen/RegisterPressure.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/CodeGen/LiveInterval.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBundle.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/RegisterClassInfo.h"
|
||||
#include "llvm/CodeGen/RegisterPressure.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/MC/LaneBitmask.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <cstdlib>
|
||||
#include <cstring>
|
||||
#include <iterator>
|
||||
#include <limits>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
|
|
@ -267,7 +291,6 @@ bool RegPressureTracker::isBottomClosed() const {
|
|||
MachineBasicBlock::const_iterator());
|
||||
}
|
||||
|
||||
|
||||
SlotIndex RegPressureTracker::getCurrSlot() const {
|
||||
MachineBasicBlock::const_iterator IdxPos =
|
||||
skipDebugInstructionsForward(CurrPos, MBB->end());
|
||||
|
|
@ -331,7 +354,7 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
|
|||
|
||||
static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
|
||||
unsigned RegUnit) {
|
||||
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I == RegUnits.end())
|
||||
|
|
@ -343,7 +366,7 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
|||
RegisterMaskPair Pair) {
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
assert(Pair.LaneMask.any());
|
||||
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I == RegUnits.end()) {
|
||||
|
|
@ -355,7 +378,7 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
|||
|
||||
static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
||||
unsigned RegUnit) {
|
||||
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I == RegUnits.end()) {
|
||||
|
|
@ -369,7 +392,7 @@ static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
|||
RegisterMaskPair Pair) {
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
assert(Pair.LaneMask.any());
|
||||
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I != RegUnits.end()) {
|
||||
|
|
@ -426,6 +449,8 @@ namespace {
|
|||
///
|
||||
/// FIXME: always ignore tied opers
|
||||
class RegisterOperandsCollector {
|
||||
friend class llvm::RegisterOperands;
|
||||
|
||||
RegisterOperands &RegOpers;
|
||||
const TargetRegisterInfo &TRI;
|
||||
const MachineRegisterInfo &MRI;
|
||||
|
|
@ -520,11 +545,9 @@ class RegisterOperandsCollector {
|
|||
addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
|
||||
}
|
||||
}
|
||||
|
||||
friend class llvm::RegisterOperands;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
} // end anonymous namespace
|
||||
|
||||
void RegisterOperands::collect(const MachineInstr &MI,
|
||||
const TargetRegisterInfo &TRI,
|
||||
|
|
@ -677,7 +700,7 @@ void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
|
|||
assert(Pair.LaneMask.any());
|
||||
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
auto I = find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
|
||||
auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
LaneBitmask PrevMask;
|
||||
|
|
@ -775,9 +798,10 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
|
|||
if (!TrackLaneMasks) {
|
||||
addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
|
||||
} else {
|
||||
auto I = find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == Reg;
|
||||
});
|
||||
auto I =
|
||||
llvm::find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == Reg;
|
||||
});
|
||||
bool IsRedef = I != LiveUses->end();
|
||||
if (IsRedef) {
|
||||
// ignore re-defs here...
|
||||
|
|
@ -1157,7 +1181,7 @@ getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
|
|||
|
||||
if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
|
||||
int CritInc = (int)MNew - (int)CriticalPSets[CritIdx].getUnitInc();
|
||||
if (CritInc > 0 && CritInc <= INT16_MAX) {
|
||||
if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
|
||||
Delta.CriticalMax = PressureChange(PSetID);
|
||||
Delta.CriticalMax.setUnitInc(CritInc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
|
||||
//===- RegisterScavenging.cpp - Machine register scavenging ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -15,18 +15,26 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/RegisterScavenging.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
#include <iterator>
|
||||
#include <limits>
|
||||
#include <string>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "reg-scavenging"
|
||||
|
|
@ -390,7 +398,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
|
|||
unsigned NeedSize = RC->getSize();
|
||||
unsigned NeedAlign = RC->getAlignment();
|
||||
|
||||
unsigned SI = Scavenged.size(), Diff = UINT_MAX;
|
||||
unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();
|
||||
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
|
||||
for (unsigned I = 0; I < Scavenged.size(); ++I) {
|
||||
if (Scavenged[I].Reg != 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue