forked from OSchip/llvm-project
parent
af35b76bda
commit
49c74934dd
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@ -4781,7 +4781,7 @@ let Predicates = [UseSSE3] in {
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// SSE3 - Replicate Double FP - MOVDDUP
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//===---------------------------------------------------------------------===//
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// FIXME: Improve MOVDDUP/BROADCAST reg/mem scheduling itineraries.
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// FIXME: Improve MOVDDUP/BROADCAST reg/mem scheduling itineraries.
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let Sched = WriteFShuffle in
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def SSE_MOVDDUP : OpndItins<
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IIC_SSE_MOV_LH, IIC_SSE_MOV_LH
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@ -6172,7 +6172,7 @@ let Predicates = [UseSSE41] in {
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// SSE4.1 - Packed Bit Test
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//===----------------------------------------------------------------------===//
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let Sched = WriteVecLogic in
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let Sched = WriteVecLogic in
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def SSE_PTEST : OpndItins<
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IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
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>;
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@ -8490,7 +8490,7 @@ let Predicates = [HasAVX2, NoVLX] in {
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// FIXME: Improve scheduling of gather instructions.
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multiclass avx2_gather<bits<8> opc, string OpcodeStr, ValueType VTx,
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ValueType VTy, PatFrag GatherNode128,
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ValueType VTy, PatFrag GatherNode128,
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PatFrag GatherNode256, RegisterClass RC256,
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X86MemOperand memop128, X86MemOperand memop256,
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ValueType MTx = VTx, ValueType MTy = VTy> {
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