forked from OSchip/llvm-project
parent
03f4f04b91
commit
498564e6fb
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@ -10507,7 +10507,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
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if (N1CFP && N1CFP->isZero())
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return N1;
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// fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
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// fmul (fmul X, C1), X2 -> fmul X, C1 * C2
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if (N0.getOpcode() == ISD::FMUL) {
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// Fold scalars or any vector constants (not just splats).
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// This fold is done in general by InstCombine, but extra fmul insts
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@ -10531,13 +10531,10 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
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}
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}
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// fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
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// Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
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// during an early run of DAGCombiner can prevent folding with fmuls
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// inserted during lowering.
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if (N0.getOpcode() == ISD::FADD &&
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(N0.getOperand(0) == N0.getOperand(1)) &&
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N0.hasOneUse()) {
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// Match a special-case: we convert X * 2.0 into fadd.
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// fmul (fadd X, X), C -> fmul X, 2.0 * C
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if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
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N0.getOperand(0) == N0.getOperand(1)) {
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const SDValue Two = DAG.getConstantFP(2.0, DL, VT);
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SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1, Flags);
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return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts, Flags);
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