From 495a1bc89378539c8b31d5cc8a91a48c4403b40b Mon Sep 17 00:00:00 2001 From: Craig Topper <craig.topper@intel.com> Date: Sun, 29 Oct 2017 06:51:04 +0000 Subject: [PATCH] [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update patterns that depended on this. If the carry flag is being used, this transformation isn't safe. This does prevent some test cases from using DEC now, but I'll try to look into that separately. Fixes PR35068. llvm-svn: 316860 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 21 -------------------- llvm/lib/Target/X86/X86InstrCompiler.td | 16 +++++++-------- llvm/test/CodeGen/X86/atomic-eflags-reuse.ll | 6 +++--- 3 files changed, 11 insertions(+), 32 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7fdfc32780e7..6fb94700b9f6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36254,26 +36254,6 @@ static SDValue combineVSZext(SDNode *N, SelectionDAG &DAG, return SDValue(); } -/// Canonicalize (LSUB p, 1) -> (LADD p, -1). -static SDValue combineLockSub(SDNode *N, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { - SDValue Chain = N->getOperand(0); - SDValue LHS = N->getOperand(1); - SDValue RHS = N->getOperand(2); - MVT VT = RHS.getSimpleValueType(); - SDLoc DL(N); - - auto *C = dyn_cast<ConstantSDNode>(RHS); - if (!C || C->getZExtValue() != 1) - return SDValue(); - - RHS = DAG.getConstant(-1, DL, VT); - MachineMemOperand *MMO = cast<MemSDNode>(N)->getMemOperand(); - return DAG.getMemIntrinsicNode(X86ISD::LADD, DL, - DAG.getVTList(MVT::i32, MVT::Other), - {Chain, LHS, RHS}, VT, MMO); -} - static SDValue combineTestM(SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget) { SDValue Op0 = N->getOperand(0); @@ -36592,7 +36572,6 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case ISD::FMA: return combineFMA(N, DAG, Subtarget); case ISD::MGATHER: case ISD::MSCATTER: return combineGatherScatter(N, DAG); - case X86ISD::LSUB: return combineLockSub(N, DAG, Subtarget); case X86ISD::TESTM: return combineTestM(N, DAG, Subtarget); case X86ISD::PCMPEQ: case X86ISD::PCMPGT: return combineVectorCompare(N, DAG, Subtarget); diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 6f7a8d3817ce..b2261c4bc4c5 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -593,7 +593,7 @@ def Int_MemBarrier : I<0, Pseudo, (outs), (ins), // ImmOpc8 corresponds to the mi8 version of the instruction // ImmMod corresponds to the instruction format of the mi and mi8 versions multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, - Format ImmMod, SDPatternOperator Op, string mnemonic> { + Format ImmMod, SDNode Op, string mnemonic> { let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { @@ -696,31 +696,31 @@ defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, - int Increment, string mnemonic> { + SDNode Op, string mnemonic> { let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), !strconcat(mnemonic, "{b}\t$dst"), - [(set EFLAGS, (X86lock_add addr:$dst, (i8 Increment)))], + [(set EFLAGS, (Op addr:$dst, (i8 1)))], IIC_UNARY_MEM>, LOCK; def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), !strconcat(mnemonic, "{w}\t$dst"), - [(set EFLAGS, (X86lock_add addr:$dst, (i16 Increment)))], + [(set EFLAGS, (Op addr:$dst, (i16 1)))], IIC_UNARY_MEM>, OpSize16, LOCK; def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), !strconcat(mnemonic, "{l}\t$dst"), - [(set EFLAGS, (X86lock_add addr:$dst, (i32 Increment)))], + [(set EFLAGS, (Op addr:$dst, (i32 1)))], IIC_UNARY_MEM>, OpSize32, LOCK; def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), !strconcat(mnemonic, "{q}\t$dst"), - [(set EFLAGS, (X86lock_add addr:$dst, (i64 Increment)))], + [(set EFLAGS, (Op addr:$dst, (i64 1)))], IIC_UNARY_MEM>, LOCK; } } let Predicates = [UseIncDec] in { -defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, 1, "inc">; -defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, -1, "dec">; +defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, X86lock_add, "inc">; +defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, X86lock_sub, "dec">; } // Atomic compare and swap. diff --git a/llvm/test/CodeGen/X86/atomic-eflags-reuse.ll b/llvm/test/CodeGen/X86/atomic-eflags-reuse.ll index a43b802e866d..a6919358ea37 100644 --- a/llvm/test/CodeGen/X86/atomic-eflags-reuse.ll +++ b/llvm/test/CodeGen/X86/atomic-eflags-reuse.ll @@ -32,7 +32,7 @@ entry: define i32 @test_sub_1_cmov_sle(i64* %p, i32 %a0, i32 %a1) #0 { ; CHECK-LABEL: test_sub_1_cmov_sle: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: lock decq (%rdi) +; CHECK-NEXT: lock addq $-1, (%rdi) ; CHECK-NEXT: cmovgel %edx, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq @@ -46,7 +46,7 @@ entry: define i32 @test_sub_1_cmov_sgt(i64* %p, i32 %a0, i32 %a1) #0 { ; CHECK-LABEL: test_sub_1_cmov_sgt: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: lock decq (%rdi) +; CHECK-NEXT: lock addq $-1, (%rdi) ; CHECK-NEXT: cmovll %edx, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq @@ -76,7 +76,7 @@ entry: define i8 @test_sub_1_setcc_sgt(i64* %p) #0 { ; CHECK-LABEL: test_sub_1_setcc_sgt: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: lock decq (%rdi) +; CHECK-NEXT: lock addq $-1, (%rdi) ; CHECK-NEXT: setge %al ; CHECK-NEXT: retq entry: