forked from OSchip/llvm-project
[GlobalISel][AArch64] Fold G_SUB into G_ICMP when it's safe to do so
Basically porting over the behaviour in AArch64ISelLowering to GISel. See emitComparison for reference. When we have something like this: ``` lhs = G_SUB 0, y ... G_ICMP lhs, rhs ``` We can fold away the G_SUB and produce a cmn instead, given that we produce the same value in NZCV. Add a test showing that the transformation works, and also showing that we don't perform the transformation when it's unsafe. Also factor out the CSet emission into emitCSetForICMP. Differential Revision: https://reviews.llvm.org/D63163 llvm-svn: 363596
This commit is contained in:
Jessica Paquette
parent
f3f968adcd
commit
49537bbf74
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@ -124,6 +124,10 @@ private:
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MachineInstr *emitFMovForFConstant(MachineInstr &MI,
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MachineRegisterInfo &MRI) const;
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/// Emit a CSet for a compare.
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MachineInstr *emitCSetForICMP(unsigned DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder) const;
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ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
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ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,
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@ -173,6 +177,7 @@ private:
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bool tryOptVectorShuffle(MachineInstr &I) const;
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bool tryOptVectorDup(MachineInstr &MI) const;
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bool tryOptSelect(MachineInstr &MI) const;
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bool tryOptCMN(MachineInstr &MI) const;
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const AArch64TargetMachine &TM;
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const AArch64Subtarget &STI;
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@ -1847,6 +1852,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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unsigned CmpOpc = 0;
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unsigned ZReg = 0;
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// Check if this compare can be represented as a cmn, and perform any
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// necessary transformations to do so.
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if (tryOptCMN(I))
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return true;
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LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
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if (CmpTy == LLT::scalar(32)) {
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CmpOpc = AArch64::SUBSWrr;
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@ -1863,13 +1873,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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if (ImmFns)
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CmpOpc = CmpOpc == AArch64::SUBSWrr ? AArch64::SUBSWri : AArch64::SUBSXri;
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// CSINC increments the result by one when the condition code is false.
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// Therefore, we have to invert the predicate to get an increment by 1 when
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// the predicate is true.
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const AArch64CC::CondCode invCC =
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changeICMPPredToAArch64CC(CmpInst::getInversePredicate(
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(CmpInst::Predicate)I.getOperand(1).getPredicate()));
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auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
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.addDef(ZReg)
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.addUse(I.getOperand(2).getReg());
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@ -1882,16 +1885,10 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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CmpMI.addUse(I.getOperand(3).getReg());
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}
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MachineInstr &CSetMI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
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.addDef(I.getOperand(0).getReg())
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.addUse(AArch64::WZR)
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.addUse(AArch64::WZR)
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.addImm(invCC);
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MachineIRBuilder MIRBuilder(I);
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emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
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MIRBuilder);
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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@ -2854,6 +2851,20 @@ MachineInstr *AArch64InstructionSelector::emitFMovForFConstant(
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return &I;
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}
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MachineInstr *
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AArch64InstructionSelector::emitCSetForICMP(unsigned DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder) const {
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// CSINC increments the result when the predicate is false. Invert it.
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const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
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CmpInst::getInversePredicate((CmpInst::Predicate)Pred));
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auto I =
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MIRBuilder
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.buildInstr(AArch64::CSINCWr, {DefReg}, {AArch64::WZR, AArch64::WZR})
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.addImm(InvCC);
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constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
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return &*I;
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}
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bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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MachineIRBuilder MIB(I);
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MachineRegisterInfo &MRI = *MIB.getMRI();
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@ -2938,6 +2949,123 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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return true;
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}
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bool AArch64InstructionSelector::tryOptCMN(MachineInstr &I) const {
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assert(I.getOpcode() == TargetOpcode::G_ICMP && "Expected G_ICMP");
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MachineIRBuilder MIRBuilder(I);
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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// We want to find this sort of thing:
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// x = G_SUB 0, y
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// G_ICMP z, x
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//
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// In this case, we can fold the G_SUB into the G_ICMP using a CMN instead.
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// e.g:
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//
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// cmn z, y
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// Helper lambda to find the def.
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auto FindDef = [&](unsigned VReg) {
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MachineInstr *Def = MRI.getVRegDef(VReg);
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while (Def) {
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if (Def->getOpcode() != TargetOpcode::COPY)
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break;
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// Copies can be from physical registers. If we hit this, we're done.
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if (TargetRegisterInfo::isPhysicalRegister(Def->getOperand(1).getReg()))
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break;
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Def = MRI.getVRegDef(Def->getOperand(1).getReg());
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}
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return Def;
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};
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// Helper lambda to detect the subtract followed by the compare.
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// Takes in the def of the LHS or RHS, and checks if it's a subtract from 0.
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auto IsCMN = [&](MachineInstr *DefMI, const AArch64CC::CondCode &CC) {
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if (!DefMI || DefMI->getOpcode() != TargetOpcode::G_SUB)
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return false;
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// Need to make sure NZCV is the same at the end of the transformation.
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if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
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return false;
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// We want to match against SUBs.
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if (DefMI->getOpcode() != TargetOpcode::G_SUB)
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return false;
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// Make sure that we're getting
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// x = G_SUB 0, y
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auto ValAndVReg =
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getConstantVRegValWithLookThrough(DefMI->getOperand(1).getReg(), MRI);
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if (!ValAndVReg || ValAndVReg->Value != 0)
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return false;
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// This can safely be represented as a CMN.
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return true;
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};
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// Check if the RHS or LHS of the G_ICMP is defined by a SUB
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MachineInstr *LHSDef = FindDef(I.getOperand(2).getReg());
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MachineInstr *RHSDef = FindDef(I.getOperand(3).getReg());
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const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
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(CmpInst::Predicate)I.getOperand(1).getPredicate());
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bool DidFold = false;
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if (IsCMN(LHSDef, CC)) {
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// We're doing this:
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//
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// Given:
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//
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// x = G_SUB 0, y
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// G_ICMP x, z
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//
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// Update the G_ICMP:
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//
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// G_ICMP y, z
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I.getOperand(2).setReg(LHSDef->getOperand(2).getReg());
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DidFold = true;
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} else if (IsCMN(RHSDef, CC)) {
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// Same idea here, but with the RHS of the compare instead:
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//
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// Given:
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//
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// x = G_SUB 0, y
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// G_ICMP z, x
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//
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// Update the G_ICMP:
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//
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// G_ICMP z, y
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I.getOperand(3).setReg(RHSDef->getOperand(2).getReg());
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DidFold = true;
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}
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if (DidFold) {
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// We can fold. Emit a CMN.
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static const unsigned OpcTable[2][2]{{AArch64::ADDSXrr, AArch64::ADDSXri},
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{AArch64::ADDSWrr, AArch64::ADDSWri}};
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bool Is32Bit =
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(MRI.getType(I.getOperand(2).getReg()).getSizeInBits() == 32);
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auto ImmFns = selectArithImmed(I.getOperand(3));
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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unsigned ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
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auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {I.getOperand(2).getReg()});
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(I.getOperand(3).getReg());
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}
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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// Add a CSet after the CMN.
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emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
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MIRBuilder);
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I.eraseFromParent();
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}
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return DidFold;
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}
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bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
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// Try to match a vector splat operation into a dup instruction.
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// We're looking for this pattern:
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@ -0,0 +1,291 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify that we can fold G_SUB into G_ICMP when we have a pattern like this:
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#
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# x = G_SUB 0, y
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# G_ICMP intpred(something_safe) z, x
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#
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# Where "something_safe" is ne or eq.
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#
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# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
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# names start with no_cmn should use SUBS.
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#
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...
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---
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name: cmn_s32_rhs
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: cmn_s32_rhs
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
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; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_CONSTANT i32 0
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%6:gpr(s32) = G_CONSTANT i32 1
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%3:gpr(s32) = G_SUB %2, %1
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%7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
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%4:gpr(s1) = G_TRUNC %7(s32)
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%5:gpr(s32) = G_SELECT %4(s1), %6, %2
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmn_s32_lhs
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: cmn_s32_lhs
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
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; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_CONSTANT i32 0
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%6:gpr(s32) = G_CONSTANT i32 1
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%3:gpr(s32) = G_SUB %2, %0
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%7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
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%4:gpr(s1) = G_TRUNC %7(s32)
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%5:gpr(s32) = G_SELECT %4(s1), %6, %2
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: no_cmn_s32_rhs
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: no_cmn_s32_rhs
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
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; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
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; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_CONSTANT i32 0
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%6:gpr(s32) = G_CONSTANT i32 1
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%3:gpr(s32) = G_SUB %2, %1
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%7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
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%4:gpr(s1) = G_TRUNC %7(s32)
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%5:gpr(s32) = G_SELECT %4(s1), %6, %2
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: no_cmn_s32_lhs
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: no_cmn_s32_lhs
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
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; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
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; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
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; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_CONSTANT i32 0
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%6:gpr(s32) = G_CONSTANT i32 1
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%3:gpr(s32) = G_SUB %2, %0
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%7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
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%4:gpr(s1) = G_TRUNC %7(s32)
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%5:gpr(s32) = G_SELECT %4(s1), %6, %2
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmn_s64_rhs
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: cmn_s64_rhs
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
||||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
%2:gpr(s64) = G_CONSTANT i64 0
|
||||
%6:gpr(s64) = G_CONSTANT i64 1
|
||||
%3:gpr(s64) = G_SUB %2, %1
|
||||
%7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
|
||||
%4:gpr(s1) = G_TRUNC %7(s32)
|
||||
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
|
||||
$x0 = COPY %5(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
name: cmn_s64_lhs
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
|
||||
; CHECK-LABEL: name: cmn_s64_lhs
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
||||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
%2:gpr(s64) = G_CONSTANT i64 0
|
||||
%6:gpr(s64) = G_CONSTANT i64 1
|
||||
%3:gpr(s64) = G_SUB %2, %0
|
||||
%7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
|
||||
%4:gpr(s1) = G_TRUNC %7(s32)
|
||||
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
|
||||
$x0 = COPY %5(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
name: no_cmn_s64_rhs
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
|
||||
; CHECK-LABEL: name: no_cmn_s64_rhs
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
||||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
%2:gpr(s64) = G_CONSTANT i64 0
|
||||
%6:gpr(s64) = G_CONSTANT i64 1
|
||||
%3:gpr(s64) = G_SUB %2, %1
|
||||
%7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
|
||||
%4:gpr(s1) = G_TRUNC %7(s32)
|
||||
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
|
||||
$x0 = COPY %5(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
name: no_cmn_s64_lhs
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
|
||||
; CHECK-LABEL: name: no_cmn_s64_lhs
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
||||
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
|
||||
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
|
||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
|
||||
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
|
||||
; CHECK: $wzr = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
%2:gpr(s64) = G_CONSTANT i64 0
|
||||
%6:gpr(s64) = G_CONSTANT i64 1
|
||||
%3:gpr(s64) = G_SUB %2, %0
|
||||
%7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
|
||||
%4:gpr(s1) = G_TRUNC %7(s32)
|
||||
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
|
||||
$x0 = COPY %5(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue