forked from OSchip/llvm-project
[SDAG] Fix CombineTo ordering in visitZERO_EXTEND and visitSIGN_EXTEND
Reorder CombineTo Calls to prevent references to stale/deleted SDNodes which caused undue assertions. Reviewers: dbabokin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D31625 llvm-svn: 304460
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4952871630
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@ -7227,12 +7227,11 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
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LN0->getBasePtr(), N0.getValueType(),
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LN0->getMemOperand());
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CombineTo(N, ExtLoad);
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
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N0.getValueType(), ExtLoad);
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
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}
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}
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@ -7288,10 +7287,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
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SDLoc(N0.getOperand(0)),
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N0.getOperand(0).getValueType(), ExtLoad);
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CombineTo(N, And);
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CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
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return CombineTo(N, And); // Return N so it doesn't get rechecked!
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}
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}
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}
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@ -7530,12 +7528,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
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N0.getValueType(), ExtLoad);
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), ISD::ZERO_EXTEND);
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CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
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ISD::ZERO_EXTEND);
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CombineTo(N, ExtLoad);
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
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}
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}
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@ -7585,11 +7580,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
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SDLoc(N0.getOperand(0)),
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N0.getOperand(0).getValueType(), ExtLoad);
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CombineTo(N, And);
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::ZERO_EXTEND);
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CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
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ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
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ISD::ZERO_EXTEND);
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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return CombineTo(N, And); // Return N so it doesn't get rechecked!
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}
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}
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}
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@ -1,81 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=skx -O0 | FileCheck %s --check-prefix=X86-O0
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx -O0 | FileCheck %s --check-prefix=X64-O0
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; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,X64
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; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,X64
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; RUN: llc -O0 -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,686
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; RUN: llc -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefixes=CHECK,686
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; REQUIRES: asserts
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@c = external constant i8, align 1
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define void @foo() {
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; X86-LABEL: foo:
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; X86: # BB#0: # %entry
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: .Lcfi0:
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; X86-NEXT: .cfi_def_cfa_offset 12
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; X86-NEXT: movzbl c, %eax
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: testl %eax, %eax
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; X86-NEXT: setne %cl
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; X86-NEXT: testb %al, %al
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; X86-NEXT: setne {{[0-9]+}}(%esp)
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: setle %dl
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; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: retl
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;
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; X86-O0-LABEL: foo:
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; X86-O0: # BB#0: # %entry
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; X86-O0-NEXT: subl $12, %esp
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; X86-O0-NEXT: .Lcfi0:
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; X86-O0-NEXT: .cfi_def_cfa_offset 16
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; X86-O0-NEXT: movb c, %al
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; X86-O0-NEXT: testb %al, %al
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; X86-O0-NEXT: setne {{[0-9]+}}(%esp)
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; X86-O0-NEXT: movzbl c, %ecx
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; X86-O0-NEXT: testl %ecx, %ecx
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; X86-O0-NEXT: setne %al
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; X86-O0-NEXT: movzbl %al, %edx
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; X86-O0-NEXT: subl %ecx, %edx
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; X86-O0-NEXT: setle %al
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; X86-O0-NEXT: andb $1, %al
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; X86-O0-NEXT: movzbl %al, %ecx
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; X86-O0-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-O0-NEXT: movl %edx, (%esp) # 4-byte Spill
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; X86-O0-NEXT: addl $12, %esp
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; X86-O0-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # BB#0: # %entry
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; X64-NEXT: movzbl {{.*}}(%rip), %eax
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; X64-NEXT: testb %al, %al
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; X64-NEXT: setne -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: testl %eax, %eax
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; X64-NEXT: setne %cl
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; X64-NEXT: xorl %edx, %edx
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; X64-NEXT: cmpl %eax, %ecx
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; X64-NEXT: setle %dl
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; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
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; X64-NEXT: retq
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;
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; X64-O0-LABEL: foo:
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; X64-O0: # BB#0: # %entry
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; X64-O0-NEXT: movb {{.*}}(%rip), %al
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; X64-O0-NEXT: testb %al, %al
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; X64-O0-NEXT: setne -{{[0-9]+}}(%rsp)
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; X64-O0-NEXT: movzbl {{.*}}(%rip), %ecx
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; X64-O0-NEXT: testl %ecx, %ecx
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: movzbl %al, %edx
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; X64-O0-NEXT: subl %ecx, %edx
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; X64-O0-NEXT: setle %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %ecx
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; X64-O0-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
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; X64-O0-NEXT: movl %edx, -{{[0-9]+}}(%rsp) # 4-byte Spill
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; X64-O0-NEXT: retq
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; CHECK-LABEL: foo:
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; CHECK: # BB#0: # %entry
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; CHECK-DAG: setne
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; CHECK-DAG: setle
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; CHECK: ret
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entry:
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%a = alloca i8, align 1
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%b = alloca i32, align 4
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@ -100,3 +36,125 @@ entry:
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store i32 %conv8, i32* %b, align 4
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ret void
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}
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@var_5 = external global i32, align 4
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@var_57 = external global i64, align 8
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@_ZN8struct_210member_2_0E = external global i64, align 8
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define void @f1() {
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; CHECK-LABEL: f1:
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; CHECK: # BB#0: # %entry
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; CHECK: sete
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; X64: addq $7093, {{.*}}
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; 686: addl $7093, {{.*}}
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; CHECK: ret
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entry:
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%a = alloca i8, align 1
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%0 = load i32, i32* @var_5, align 4
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%conv = sext i32 %0 to i64
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%add = add nsw i64 %conv, 8381627093
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%tobool = icmp ne i64 %add, 0
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%frombool = zext i1 %tobool to i8
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store i8 %frombool, i8* %a, align 1
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%1 = load i32, i32* @var_5, align 4
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%neg = xor i32 %1, -1
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%tobool1 = icmp ne i32 %neg, 0
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%lnot = xor i1 %tobool1, true
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%conv2 = zext i1 %lnot to i64
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%2 = load i32, i32* @var_5, align 4
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%conv3 = sext i32 %2 to i64
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%add4 = add nsw i64 %conv3, 7093
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%cmp = icmp sgt i64 %conv2, %add4
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%conv5 = zext i1 %cmp to i64
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store i64 %conv5, i64* @var_57, align 8
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%3 = load i32, i32* @var_5, align 4
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%neg6 = xor i32 %3, -1
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%tobool7 = icmp ne i32 %neg6, 0
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%lnot8 = xor i1 %tobool7, true
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%conv9 = zext i1 %lnot8 to i64
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store i64 %conv9, i64* @_ZN8struct_210member_2_0E, align 8
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ret void
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}
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@var_7 = external global i8, align 1
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define void @f2() {
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; CHECK-LABEL: f2:
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; CHECK: # BB#0: # %entry
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; X64: movzbl {{.*}}(%rip), %[[R:[a-z]*]]
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; 686: movzbl {{.*}}, %[[R:[a-z]*]]
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; CHECK: test{{[qlwb]}} %[[R]], %[[R]]
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; CHECK: sete {{.*}}
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; CHECK: ret
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entry:
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%a = alloca i16, align 2
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%0 = load i8, i8* @var_7, align 1
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%conv = zext i8 %0 to i32
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%1 = load i8, i8* @var_7, align 1
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%tobool = icmp ne i8 %1, 0
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%lnot = xor i1 %tobool, true
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%conv1 = zext i1 %lnot to i32
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%xor = xor i32 %conv, %conv1
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%conv2 = trunc i32 %xor to i16
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store i16 %conv2, i16* %a, align 2
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%2 = load i8, i8* @var_7, align 1
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%conv3 = zext i8 %2 to i16
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%tobool4 = icmp ne i16 %conv3, 0
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%lnot5 = xor i1 %tobool4, true
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%conv6 = zext i1 %lnot5 to i32
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%3 = load i8, i8* @var_7, align 1
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%conv7 = zext i8 %3 to i32
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%cmp = icmp eq i32 %conv6, %conv7
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%conv8 = zext i1 %cmp to i32
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%conv9 = trunc i32 %conv8 to i16
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store i16 %conv9, i16* undef, align 2
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ret void
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}
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@var_13 = external global i32, align 4
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@var_16 = external global i32, align 4
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@var_46 = external global i32, align 4
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define void @f3() #0 {
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; CHECK-LABEL: f3:
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; X64-DAG: movl var_13(%rip), {{.*}}
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; X64-DAG: movl var_16(%rip), {{.*}}
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; X64-DAG: movl {{.*}},{{.*}}var_46{{.*}}
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; X64: retq
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; 686-DAG: movl var_13, {{.*}}
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; 686-DAG: movl var_16, {{.*}}
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; 686-DAG: movl {{.*}},{{.*}}var_46{{.*}}
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; 686: retl
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entry:
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%a = alloca i64, align 8
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%0 = load i32, i32* @var_13, align 4
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%neg = xor i32 %0, -1
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%conv = zext i32 %neg to i64
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%1 = load i32, i32* @var_13, align 4
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%tobool = icmp ne i32 %1, 0
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%lnot = xor i1 %tobool, true
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%conv1 = zext i1 %lnot to i64
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%2 = load i32, i32* @var_13, align 4
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%neg2 = xor i32 %2, -1
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%3 = load i32, i32* @var_16, align 4
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%xor = xor i32 %neg2, %3
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%conv3 = zext i32 %xor to i64
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%and = and i64 %conv1, %conv3
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%or = or i64 %conv, %and
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store i64 %or, i64* %a, align 8
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%4 = load i32, i32* @var_13, align 4
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%neg4 = xor i32 %4, -1
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%conv5 = zext i32 %neg4 to i64
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%5 = load i32, i32* @var_13, align 4
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%tobool6 = icmp ne i32 %5, 0
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%lnot7 = xor i1 %tobool6, true
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%conv8 = zext i1 %lnot7 to i64
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%and9 = and i64 %conv8, 0
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%or10 = or i64 %conv5, %and9
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%conv11 = trunc i64 %or10 to i32
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store i32 %conv11, i32* @var_46, align 4
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ret void
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}
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