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Remove dead code. 

llvm-svn: 231883
This commit is contained in:
Eric Christopher 2015-03-10 23:22:04 +00:00
parent b03bc79bed
commit 49338e9fa6
3 changed files with 0 additions and 33 deletions
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8
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -686,14 +686,6 @@ public:
const MachineFunction &MF, const MachineFunction &MF,
const VirtRegMap *VRM = nullptr) const; const VirtRegMap *VRM = nullptr) const;
/// avoidWriteAfterWrite - Return true if the register allocator should avoid
/// writing a register from RC in two consecutive instructions.
/// This can avoid pipeline stalls on certain architectures.
/// It does cause increased register pressure, though.
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
return false;
}
/// updateRegAllocHint - A callback to allow target a chance to update /// updateRegAllocHint - A callback to allow target a chance to update
/// register allocation hints when a register is "changed" (e.g. coalesced) /// register allocation hints when a register is "changed" (e.g. coalesced)
/// to another register. e.g. On ARM, some virtual registers should target /// to another register. e.g. On ARM, some virtual registers should target

23
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -283,29 +283,6 @@ ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
} }
} }
bool
ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
// CortexA9 has a Write-after-write hazard for NEON registers.
if (!STI.isLikeA9())
return false;
switch (RC->getID()) {
case ARM::DPRRegClassID:
case ARM::DPR_8RegClassID:
case ARM::DPR_VFP2RegClassID:
case ARM::QPRRegClassID:
case ARM::QPR_8RegClassID:
case ARM::QPR_VFP2RegClassID:
case ARM::SPRRegClassID:
case ARM::SPR_8RegClassID:
// Avoid reusing S, D, and Q registers.
// Don't increase register pressure for QQ and QQQQ.
return true;
default:
return false;
}
}
bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineFrameInfo *MFI = MF.getFrameInfo();
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();

2
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -138,8 +138,6 @@ public:
void updateRegAllocHint(unsigned Reg, unsigned NewReg, void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const override; MachineFunction &MF) const override;
bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
bool hasBasePointer(const MachineFunction &MF) const; bool hasBasePointer(const MachineFunction &MF) const;
bool canRealignStack(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const;