forked from OSchip/llvm-project
[NFC][VectorCombine] Load widening: add a few more negative tests
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 --data-layout="e-m:e-i64:64-f80:128-n8:16:32:64-S128" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 --data-layout="e-m:e-i64:64-f80:128-n8:16:32:64-S128" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 --data-layout="E-m:e-i64:64-f80:128-n8:16:32:64-S128" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 --data-layout="E-m:e-i64:64-f80:128-n8:16:32:64-S128" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 --data-layout="e" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 --data-layout="e" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 --data-layout="E" | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 --data-layout="E" | FileCheck %s --check-prefixes=CHECK
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;-------------------------------------------------------------------------------
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; Here we know we can load 128 bits as per dereferenceability and alignment.
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@ -222,3 +222,32 @@ define <2 x float> @vec_with_2elts_addressspace(<2 x float> addrspace(2)* align
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%r = load <2 x float>, <2 x float> addrspace(2)* %p, align 16
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ret <2 x float> %r
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}
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;-------------------------------------------------------------------------------
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; Widening these would change the legalized type, so leave them alone.
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define <2 x i1> @vec_with_2elts_128bits_i1(<2 x i1>* align 16 dereferenceable(16) %p) {
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; CHECK-LABEL: @vec_with_2elts_128bits_i1(
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; CHECK-NEXT: [[R:%.*]] = load <2 x i1>, <2 x i1>* [[P:%.*]], align 16
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%r = load <2 x i1>, <2 x i1>* %p, align 16
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ret <2 x i1> %r
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}
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define <2 x i2> @vec_with_2elts_128bits_i2(<2 x i2>* align 16 dereferenceable(16) %p) {
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; CHECK-LABEL: @vec_with_2elts_128bits_i2(
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; CHECK-NEXT: [[R:%.*]] = load <2 x i2>, <2 x i2>* [[P:%.*]], align 16
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; CHECK-NEXT: ret <2 x i2> [[R]]
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;
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%r = load <2 x i2>, <2 x i2>* %p, align 16
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ret <2 x i2> %r
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}
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define <2 x i4> @vec_with_2elts_128bits_i4(<2 x i4>* align 16 dereferenceable(16) %p) {
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; CHECK-LABEL: @vec_with_2elts_128bits_i4(
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; CHECK-NEXT: [[R:%.*]] = load <2 x i4>, <2 x i4>* [[P:%.*]], align 16
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; CHECK-NEXT: ret <2 x i4> [[R]]
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;
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%r = load <2 x i4>, <2 x i4>* %p, align 16
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ret <2 x i4> %r
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}
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