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Revert "[DebugInfo] Add debug locations to constant SD nodes" 

This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870

llvm-svn: 235987
This commit is contained in:
Daniel Jasper 2015-04-28 13:38:35 +00:00
parent 35dc8c0944
commit 48e93f7181
78 changed files with 3705 additions and 4399 deletions
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46
llvm/include/llvm/CodeGen/SelectionDAG.h
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@ -413,40 +413,36 @@ public:
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Node creation methods. // Node creation methods.
// //
SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false, SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false,
bool isOpaque = false); bool isOpaque = false);
SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false, SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false,
bool isOpaque = false); bool isOpaque = false);
SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT, SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false,
bool isTarget = false, bool isOpaque = false); bool isOpaque = false);
SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget = false); SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT, SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque = false) {
bool isOpaque = false) { return getConstant(Val, VT, true, isOpaque);
return getConstant(Val, DL, VT, true, isOpaque);
} }
SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT, SDValue getTargetConstant(const APInt &Val, EVT VT, bool isOpaque = false) {
bool isOpaque = false) { return getConstant(Val, VT, true, isOpaque);
return getConstant(Val, DL, VT, true, isOpaque);
} }
SDValue getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT, SDValue getTargetConstant(const ConstantInt &Val, EVT VT,
bool isOpaque = false) { bool isOpaque = false) {
return getConstant(Val, DL, VT, true, isOpaque); return getConstant(Val, VT, true, isOpaque);
} }
// The forms below that take a double should only be used for simple // The forms below that take a double should only be used for simple
// constants that can be exactly represented in VT. No checks are made. // constants that can be exactly represented in VT. No checks are made.
SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget = false); SDValue getConstantFP(double Val, EVT VT, bool isTarget = false);
SDValue getConstantFP(const APFloat& Val, SDLoc DL, EVT VT, SDValue getConstantFP(const APFloat& Val, EVT VT, bool isTarget = false);
bool isTarget = false); SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false);
SDValue getConstantFP(const ConstantFP &CF, SDLoc DL, EVT VT, SDValue getTargetConstantFP(double Val, EVT VT) {
bool isTarget = false); return getConstantFP(Val, VT, true);
SDValue getTargetConstantFP(double Val, SDLoc DL, EVT VT) {
return getConstantFP(Val, DL, VT, true);
} }
SDValue getTargetConstantFP(const APFloat& Val, SDLoc DL, EVT VT) { SDValue getTargetConstantFP(const APFloat& Val, EVT VT) {
return getConstantFP(Val, DL, VT, true); return getConstantFP(Val, VT, true);
} }
SDValue getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) { SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {
return getConstantFP(Val, DL, VT, true); return getConstantFP(Val, VT, true);
} }
SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
int64_t offset = 0, bool isTargetGA = false, int64_t offset = 0, bool isTargetGA = false,
@ -1121,7 +1117,7 @@ public:
/// either of the specified value types. /// either of the specified value types.
SDValue CreateStackTemporary(EVT VT1, EVT VT2); SDValue CreateStackTemporary(EVT VT1, EVT VT2);
SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT, SDValue FoldConstantArithmetic(unsigned Opcode, EVT VT,
SDNode *Cst1, SDNode *Cst2); SDNode *Cst1, SDNode *Cst2);
/// Constant fold a setcc to true or false. /// Constant fold a setcc to true or false.

2
llvm/include/llvm/CodeGen/SelectionDAGISel.h
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@ -199,7 +199,7 @@ protected:
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it. /// by tblgen. Others should not call it.
void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL); void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
public: public:

5
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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@ -1361,10 +1361,9 @@ public:
class ConstantSDNode : public SDNode { class ConstantSDNode : public SDNode {
const ConstantInt *Value; const ConstantInt *Value;
friend class SelectionDAG; friend class SelectionDAG;
ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
DebugLoc DL, EVT VT)
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
0, DL, getSDVTList(VT)), Value(val) { 0, DebugLoc(), getSDVTList(VT)), Value(val) {
SubclassData |= (uint16_t)isOpaque; SubclassData |= (uint16_t)isOpaque;
} }
public: public:

845
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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File diff suppressed because it is too large Load Diff

317
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -249,7 +249,7 @@ SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
if (!UseCP) { if (!UseCP) {
assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl, return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
(VT == MVT::f64) ? MVT::i64 : MVT::i32); (VT == MVT::f64) ? MVT::i64 : MVT::i32);
} }
@ -331,7 +331,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
SDValue Store = DAG.getTruncStore(Chain, dl, SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, MachinePointerInfo(), Val, StackPtr, MachinePointerInfo(),
StoredVT, false, false, 0); StoredVT, false, false, 0);
SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy(AS)); SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
SmallVector<SDValue, 8> Stores; SmallVector<SDValue, 8> Stores;
unsigned Offset = 0; unsigned Offset = 0;
@ -385,7 +385,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
int IncrementSize = NumBits / 8; int IncrementSize = NumBits / 8;
// Divide the stored value in two parts. // Divide the stored value in two parts.
SDValue ShiftAmount = DAG.getConstant(NumBits, dl, SDValue ShiftAmount = DAG.getConstant(NumBits,
TLI.getShiftAmountTy(Val.getValueType())); TLI.getShiftAmountTy(Val.getValueType()));
SDValue Lo = Val; SDValue Lo = Val;
SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
@ -397,7 +397,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
ST->isVolatile(), ST->isNonTemporal(), Alignment); ST->isVolatile(), ST->isNonTemporal(), Alignment);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, TLI.getPointerTy(AS))); DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
Alignment = MinAlign(Alignment, IncrementSize); Alignment = MinAlign(Alignment, IncrementSize);
Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), ST->getPointerInfo().getWithOffset(IncrementSize),
@ -448,7 +448,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
// Make sure the stack slot is also aligned for the register type. // Make sure the stack slot is also aligned for the register type.
SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy()); SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
SmallVector<SDValue, 8> Stores; SmallVector<SDValue, 8> Stores;
SDValue StackPtr = StackBase; SDValue StackPtr = StackBase;
unsigned Offset = 0; unsigned Offset = 0;
@ -528,7 +528,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
LD->isNonTemporal(), LD->isInvariant(), Alignment, LD->isNonTemporal(), LD->isInvariant(), Alignment,
LD->getAAInfo()); LD->getAAInfo());
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
NewLoadedVT, LD->isVolatile(), NewLoadedVT, LD->isVolatile(),
@ -540,7 +540,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
LD->isNonTemporal(), LD->isInvariant(), Alignment, LD->isNonTemporal(), LD->isInvariant(), Alignment,
LD->getAAInfo()); LD->getAAInfo());
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
NewLoadedVT, LD->isVolatile(), NewLoadedVT, LD->isVolatile(),
@ -549,7 +549,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
} }
// aggregate the two parts // aggregate the two parts
SDValue ShiftAmount = DAG.getConstant(NumBits, dl, SDValue ShiftAmount = DAG.getConstant(NumBits,
TLI.getShiftAmountTy(Hi.getValueType())); TLI.getShiftAmountTy(Hi.getValueType()));
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
@ -596,8 +596,7 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
// Add the offset to the index. // Add the offset to the index.
unsigned EltSize = EltVT.getSizeInBits()/8; unsigned EltSize = EltVT.getSizeInBits()/8;
Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3, Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
DAG.getConstant(EltSize, dl, IdxVT));
SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
// Store the scalar value. // Store the scalar value.
Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
@ -656,7 +655,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
TLI.isTypeLegal(MVT::i32)) { TLI.isTypeLegal(MVT::i32)) {
SDValue Con = DAG.getConstant(CFP->getValueAPF(). SDValue Con = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32), bitcastToAPInt().zextOrTrunc(32),
SDLoc(CFP), MVT::i32); MVT::i32);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
isVolatile, isNonTemporal, Alignment, AAInfo); isVolatile, isNonTemporal, Alignment, AAInfo);
} }
@ -665,7 +664,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
// If this target supports 64-bit registers, do a single 64-bit store. // If this target supports 64-bit registers, do a single 64-bit store.
if (TLI.isTypeLegal(MVT::i64)) { if (TLI.isTypeLegal(MVT::i64)) {
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), SDLoc(CFP), MVT::i64); zextOrTrunc(64), MVT::i64);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
isVolatile, isNonTemporal, Alignment, AAInfo); isVolatile, isNonTemporal, Alignment, AAInfo);
} }
@ -674,15 +673,15 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit // Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this // stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it. // xform is certainly not worth it.
const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt(); const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32); SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32); SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi); if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile, Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
isNonTemporal, Alignment, AAInfo); isNonTemporal, Alignment, AAInfo);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(4, dl, Ptr.getValueType())); DAG.getConstant(4, Ptr.getValueType()));
Hi = DAG.getStore(Chain, dl, Hi, Ptr, Hi = DAG.getStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4), ST->getPointerInfo().getWithOffset(4),
isVolatile, isNonTemporal, MinAlign(Alignment, 4U), isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
@ -793,10 +792,9 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// Store the remaining ExtraWidth bits. // Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize, Ptr.getValueType()));
Ptr.getValueType()));
Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
DAG.getConstant(RoundWidth, dl, DAG.getConstant(RoundWidth,
TLI.getShiftAmountTy(Value.getValueType()))); TLI.getShiftAmountTy(Value.getValueType())));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), ST->getPointerInfo().getWithOffset(IncrementSize),
@ -807,7 +805,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
// Store the top RoundWidth bits. // Store the top RoundWidth bits.
Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
DAG.getConstant(ExtraWidth, dl, DAG.getConstant(ExtraWidth,
TLI.getShiftAmountTy(Value.getValueType()))); TLI.getShiftAmountTy(Value.getValueType())));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
RoundVT, isVolatile, isNonTemporal, Alignment, RoundVT, isVolatile, isNonTemporal, Alignment,
@ -816,8 +814,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// Store the remaining ExtraWidth bits. // Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize, Ptr.getValueType()));
Ptr.getValueType()));
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, ExtraVT, isVolatile, isNonTemporal,
@ -1007,8 +1004,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Load the remaining ExtraWidth bits. // Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize, Ptr.getValueType()));
Ptr.getValueType()));
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, isInvariant, ExtraVT, isVolatile, isNonTemporal, isInvariant,
@ -1021,7 +1017,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Move the top bits to the right place. // Move the top bits to the right place.
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
DAG.getConstant(RoundWidth, dl, DAG.getConstant(RoundWidth,
TLI.getShiftAmountTy(Hi.getValueType()))); TLI.getShiftAmountTy(Hi.getValueType())));
// Join the hi and lo parts. // Join the hi and lo parts.
@ -1037,8 +1033,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Load the remaining ExtraWidth bits. // Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize, Ptr.getValueType()));
Ptr.getValueType()));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
dl, Node->getValueType(0), Chain, Ptr, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
@ -1052,7 +1047,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Move the top bits to the right place. // Move the top bits to the right place.
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
DAG.getConstant(ExtraWidth, dl, DAG.getConstant(ExtraWidth,
TLI.getShiftAmountTy(Hi.getValueType()))); TLI.getShiftAmountTy(Hi.getValueType())));
// Join the hi and lo parts. // Join the hi and lo parts.
@ -1442,7 +1437,7 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
unsigned EltSize = unsigned EltSize =
Vec.getValueType().getVectorElementType().getSizeInBits()/8; Vec.getValueType().getVectorElementType().getSizeInBits()/8;
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType())); DAG.getConstant(EltSize, Idx.getValueType()));
Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy()); Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
@ -1495,7 +1490,7 @@ SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
Vec.getValueType().getVectorElementType().getSizeInBits()/8; Vec.getValueType().getVectorElementType().getSizeInBits()/8;
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType())); DAG.getConstant(EltSize, Idx.getValueType()));
Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy()); Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
@ -1532,7 +1527,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
unsigned Offset = TypeByteSize*i; unsigned Offset = TypeByteSize*i;
SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType()); SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
// If the destination vector element type is narrower than the source // If the destination vector element type is narrower than the source
@ -1594,8 +1589,7 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr, LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
DAG.getConstant(ByteOffset, dl, DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
LoadPtr.getValueType()));
// Load a legal integer containing the sign bit. // Load a legal integer containing the sign bit.
SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
false, false, false, 0); false, false, false, 0);
@ -1605,14 +1599,13 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
if (BitShift) if (BitShift)
SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
DAG.getConstant(BitShift, dl, DAG.getConstant(BitShift,
TLI.getShiftAmountTy(SignBit.getValueType()))); TLI.getShiftAmountTy(SignBit.getValueType())));
} }
} }
// Now get the sign bit proper, by seeing whether the value is negative. // Now get the sign bit proper, by seeing whether the value is negative.
SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()), SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
SignBit, SignBit, DAG.getConstant(0, SignBit.getValueType()),
DAG.getConstant(0, dl, SignBit.getValueType()),
ISD::SETLT); ISD::SETLT);
// Get the absolute value of the result. // Get the absolute value of the result.
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
@ -1637,7 +1630,8 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
// Chain the dynamic stack allocation so that it doesn't modify the stack // Chain the dynamic stack allocation so that it doesn't modify the stack
// pointer when other instructions are using the stack. // pointer when other instructions are using the stack.
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl); Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
SDLoc(Node));
SDValue Size = Tmp2.getOperand(1); SDValue Size = Tmp2.getOperand(1);
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
@ -1648,11 +1642,12 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
if (Align > StackAlign) if (Align > StackAlign)
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
DAG.getConstant(-(uint64_t)Align, dl, VT)); DAG.getConstant(-(uint64_t)Align, VT));
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true), Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
DAG.getIntPtrConstant(0, dl, true), SDValue(), dl); DAG.getIntPtrConstant(0, true), SDValue(),
SDLoc(Node));
Results.push_back(Tmp1); Results.push_back(Tmp1);
Results.push_back(Tmp2); Results.push_back(Tmp2);
@ -2423,8 +2418,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
// word offset constant for Hi/Lo address computation // word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), dl, SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
StackSlot.getValueType());
// set up Hi and Lo (into buffer) address based on endian // set up Hi and Lo (into buffer) address based on endian
SDValue Hi = StackSlot; SDValue Hi = StackSlot;
SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(), SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
@ -2436,7 +2430,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Op0Mapped; SDValue Op0Mapped;
if (isSigned) { if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping) // constant used to invert sign bit (signed to unsigned mapping)
SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32); SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
} else { } else {
Op0Mapped = Op0; Op0Mapped = Op0;
@ -2446,7 +2440,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
Op0Mapped, Lo, MachinePointerInfo(), Op0Mapped, Lo, MachinePointerInfo(),
false, false, 0); false, false, 0);
// initial hi portion of constructed double // initial hi portion of constructed double
SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32); SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent // store the hi of the constructed double - biased exponent
SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
MachinePointerInfo(), MachinePointerInfo(),
@ -2458,7 +2452,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Bias = DAG.getConstantFP(isSigned ? SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) : BitsToDouble(0x4330000080000000ULL) :
BitsToDouble(0x4330000000000000ULL), BitsToDouble(0x4330000000000000ULL),
dl, MVT::f64); MVT::f64);
// subtract the bias // subtract the bias
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
// final result // final result
@ -2469,7 +2463,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
Result = Sub; Result = Sub;
} else if (DestVT.bitsLT(MVT::f64)) { } else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
} else if (DestVT.bitsGT(MVT::f64)) { } else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
} }
@ -2485,16 +2479,15 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
// TODO: Generalize this for use with other types. // TODO: Generalize this for use with other types.
if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
SDValue TwoP52 = SDValue TwoP52 =
DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64); DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
SDValue TwoP84PlusTwoP52 = SDValue TwoP84PlusTwoP52 =
DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl, DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
MVT::f64);
SDValue TwoP84 = SDValue TwoP84 =
DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64); DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
@ -2513,9 +2506,9 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
SDValue ShiftConst = SDValue ShiftConst =
DAG.getConstant(1, dl, TLI.getShiftAmountTy(Op0.getValueType())); DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
SDValue AndConst = DAG.getConstant(1, dl, MVT::i64); SDValue AndConst = DAG.getConstant(1, MVT::i64);
SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
@ -2527,52 +2520,47 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
// thing most of the time. This would be a good candidate for a // thing most of the time. This would be a good candidate for a
//pseudo-op, or, even better, for whole-function isel. //pseudo-op, or, even better, for whole-function isel.
SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT); Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast); return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
} }
// Otherwise, implement the fully general conversion. // Otherwise, implement the fully general conversion.
SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64)); DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
DAG.getConstant(UINT64_C(0x800), dl, MVT::i64)); DAG.getConstant(UINT64_C(0x800), MVT::i64));
SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64)); DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2, SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
DAG.getConstant(UINT64_C(0), dl, MVT::i64), And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
ISD::SETNE);
SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0); SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0, SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
DAG.getConstant(UINT64_C(0x0020000000000000), dl, Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
MVT::i64), ISD::SETUGE);
ISD::SETUGE);
SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0); SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
DAG.getConstant(32, dl, SHVT)); DAG.getConstant(32, SHVT));
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
SDValue TwoP32 = SDValue TwoP32 =
DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl, DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
MVT::f64);
SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
} }
SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()), SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
Op0, Op0, DAG.getConstant(0, Op0.getValueType()),
DAG.getConstant(0, dl, Op0.getValueType()),
ISD::SETLT); ISD::SETLT);
SDValue Zero = DAG.getIntPtrConstant(0, dl), SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
Four = DAG.getIntPtrConstant(4, dl);
SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(), SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
SignSet, Four, Zero); SignSet, Four, Zero);
@ -2707,41 +2695,34 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled Expand type in BSWAP!"); default: llvm_unreachable("Unhandled Expand type in BSWAP!");
case MVT::i16: case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
case MVT::i32: case MVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
DAG.getConstant(0xFF0000, dl, VT)); Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
case MVT::i64: case MVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
DAG.getConstant(255ULL<<48, dl, VT)); Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
DAG.getConstant(255ULL<<40, dl, VT)); Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
DAG.getConstant(255ULL<<32, dl, VT)); Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
DAG.getConstant(255ULL<<24, dl, VT));
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
DAG.getConstant(255ULL<<16, dl, VT));
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
DAG.getConstant(255ULL<<8 , dl, VT));
Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
@ -2768,38 +2749,34 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
// This is the "best" algorithm from // This is the "best" algorithm from
// http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
dl, VT); SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
dl, VT); SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
dl, VT);
SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
dl, VT);
// v = v - ((v >> 1) & 0x55555555...) // v = v - ((v >> 1) & 0x55555555...)
Op = DAG.getNode(ISD::SUB, dl, VT, Op, Op = DAG.getNode(ISD::SUB, dl, VT, Op,
DAG.getNode(ISD::AND, dl, VT, DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getNode(ISD::SRL, dl, VT, Op,
DAG.getConstant(1, dl, ShVT)), DAG.getConstant(1, ShVT)),
Mask55)); Mask55));
// v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
Op = DAG.getNode(ISD::ADD, dl, VT, Op = DAG.getNode(ISD::ADD, dl, VT,
DAG.getNode(ISD::AND, dl, VT, Op, Mask33), DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
DAG.getNode(ISD::AND, dl, VT, DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getNode(ISD::SRL, dl, VT, Op,
DAG.getConstant(2, dl, ShVT)), DAG.getConstant(2, ShVT)),
Mask33)); Mask33));
// v = (v + (v >> 4)) & 0x0F0F0F0F... // v = (v + (v >> 4)) & 0x0F0F0F0F...
Op = DAG.getNode(ISD::AND, dl, VT, Op = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getNode(ISD::ADD, dl, VT, Op,
DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getNode(ISD::SRL, dl, VT, Op,
DAG.getConstant(4, dl, ShVT))), DAG.getConstant(4, ShVT))),
Mask0F); Mask0F);
// v = (v * 0x01010101...) >> (Len - 8) // v = (v * 0x01010101...) >> (Len - 8)
Op = DAG.getNode(ISD::SRL, dl, VT, Op = DAG.getNode(ISD::SRL, dl, VT,
DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
DAG.getConstant(Len - 8, dl, ShVT)); DAG.getConstant(Len - 8, ShVT));
return Op; return Op;
} }
@ -2820,7 +2797,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
EVT ShVT = TLI.getShiftAmountTy(VT); EVT ShVT = TLI.getShiftAmountTy(VT);
unsigned len = VT.getSizeInBits(); unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT); SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, dl, VT, Op, Op = DAG.getNode(ISD::OR, dl, VT, Op,
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
} }
@ -2839,12 +2816,12 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNOT(dl, Op, VT), DAG.getNOT(dl, Op, VT),
DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getNode(ISD::SUB, dl, VT, Op,
DAG.getConstant(1, dl, VT))); DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead. // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
return DAG.getNode(ISD::SUB, dl, VT, return DAG.getNode(ISD::SUB, dl, VT,
DAG.getConstant(VT.getSizeInBits(), dl, VT), DAG.getConstant(VT.getSizeInBits(), VT),
DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
} }
@ -2880,10 +2857,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::FRAMEADDR: case ISD::FRAMEADDR:
case ISD::RETURNADDR: case ISD::RETURNADDR:
case ISD::FRAME_TO_ARGS_OFFSET: case ISD::FRAME_TO_ARGS_OFFSET:
Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0))); Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
break; break;
case ISD::FLT_ROUNDS_: case ISD::FLT_ROUNDS_:
Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0))); Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
break; break;
case ISD::EH_RETURN: case ISD::EH_RETURN:
case ISD::EH_LABEL: case ISD::EH_LABEL:
@ -2897,7 +2874,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::EH_SJLJ_SETJMP: case ISD::EH_SJLJ_SETJMP:
// If the target didn't expand this, just return 'zero' and preserve the // If the target didn't expand this, just return 'zero' and preserve the
// chain. // chain.
Results.push_back(DAG.getConstant(0, dl, MVT::i32)); Results.push_back(DAG.getConstant(0, MVT::i32));
Results.push_back(Node->getOperand(0)); Results.push_back(Node->getOperand(0));
break; break;
case ISD::ATOMIC_FENCE: { case ISD::ATOMIC_FENCE: {
@ -2918,7 +2895,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
} }
case ISD::ATOMIC_LOAD: { case ISD::ATOMIC_LOAD: {
// There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0)); SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other); SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
SDValue Swap = DAG.getAtomicCmpSwap( SDValue Swap = DAG.getAtomicCmpSwap(
ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs, ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
@ -2994,10 +2971,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::UNDEF: { case ISD::UNDEF: {
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
if (VT.isInteger()) if (VT.isInteger())
Results.push_back(DAG.getConstant(0, dl, VT)); Results.push_back(DAG.getConstant(0, VT));
else { else {
assert(VT.isFloatingPoint() && "Unknown value type!"); assert(VT.isFloatingPoint() && "Unknown value type!");
Results.push_back(DAG.getConstantFP(0, dl, VT)); Results.push_back(DAG.getConstantFP(0, VT));
} }
break; break;
} }
@ -3036,7 +3013,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
ShiftAmountTy = VT; ShiftAmountTy = VT;
unsigned BitsDiff = VT.getScalarType().getSizeInBits() - unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
ExtraVT.getScalarType().getSizeInBits(); ExtraVT.getScalarType().getSizeInBits();
SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy); SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
Node->getOperand(0), ShiftCst); Node->getOperand(0), ShiftCst);
Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
@ -3074,7 +3051,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
APInt::getNullValue(VT.getSizeInBits())); APInt::getNullValue(VT.getSizeInBits()));
APInt x = APInt::getSignBit(NVT.getSizeInBits()); APInt x = APInt::getSignBit(NVT.getSizeInBits());
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp1 = DAG.getConstantFP(apf, dl, VT); Tmp1 = DAG.getConstantFP(apf, VT);
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
Node->getOperand(0), Node->getOperand(0),
Tmp1, ISD::SETLT); Tmp1, ISD::SETLT);
@ -3083,7 +3060,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
DAG.getNode(ISD::FSUB, dl, VT, DAG.getNode(ISD::FSUB, dl, VT,
Node->getOperand(0), Tmp1)); Node->getOperand(0), Tmp1));
False = DAG.getNode(ISD::XOR, dl, NVT, False, False = DAG.getNode(ISD::XOR, dl, NVT, False,
DAG.getConstant(x, dl, NVT)); DAG.getConstant(x, NVT));
Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False); Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
@ -3104,11 +3081,11 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList, VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
DAG.getConstant(Align - 1, dl, DAG.getConstant(Align - 1,
VAList.getValueType())); VAList.getValueType()));
VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList, VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
DAG.getConstant(-(int64_t)Align, dl, DAG.getConstant(-(int64_t)Align,
VAList.getValueType())); VAList.getValueType()));
} }
@ -3116,7 +3093,6 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList, Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
DAG.getConstant(TLI.getDataLayout()-> DAG.getConstant(TLI.getDataLayout()->
getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
dl,
VAList.getValueType())); VAList.getValueType()));
// Store the incremented VAList to the legalized pointer // Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
@ -3231,11 +3207,11 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
if (Idx < NumElems) if (Idx < NumElems)
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
Op0, Op0,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()))); DAG.getConstant(Idx, TLI.getVectorIdxTy())));
else else
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
Op1, Op1,
DAG.getConstant(Idx - NumElems, dl, DAG.getConstant(Idx - NumElems,
TLI.getVectorIdxTy()))); TLI.getVectorIdxTy())));
} }
@ -3250,7 +3226,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
// 1 -> Hi // 1 -> Hi
Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
DAG.getConstant(OpTy.getSizeInBits()/2, dl, DAG.getConstant(OpTy.getSizeInBits()/2,
TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
} else { } else {
@ -3288,7 +3264,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
break; break;
case ISD::FNEG: case ISD::FNEG:
// Expand Y = FNEG(X) -> Y = SUB -0.0, X // Expand Y = FNEG(X) -> Y = SUB -0.0, X
Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0)); Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
Node->getOperand(0)); Node->getOperand(0));
Results.push_back(Tmp1); Results.push_back(Tmp1);
@ -3297,7 +3273,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0); Tmp1 = Node->getOperand(0);
Tmp2 = DAG.getConstantFP(0.0, dl, VT); Tmp2 = DAG.getConstantFP(0.0, VT);
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
Tmp1, Tmp2, ISD::SETUGT); Tmp1, Tmp2, ISD::SETUGT);
Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
@ -3470,7 +3446,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// Under fastmath, we can expand this node into a fround followed by // Under fastmath, we can expand this node into a fround followed by
// a float-half conversion. // a float-half conversion.
SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
Results.push_back( Results.push_back(
DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal)); DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
break; break;
@ -3511,9 +3487,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
TLI.isOperationLegalOrCustom(ISD::XOR, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
"Don't know how to expand this subtraction!"); "Don't know how to expand this subtraction!");
Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
VT)); Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
break; break;
} }
@ -3629,7 +3604,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) { TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi); Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(), dl, SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(),
TLI.getShiftAmountTy(HalfType)); TLI.getShiftAmountTy(HalfType));
Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift); Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi)); Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
@ -3654,7 +3629,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
EVT ResultType = Node->getValueType(1); EVT ResultType = Node->getValueType(1);
EVT OType = getSetCCResultType(Node->getValueType(0)); EVT OType = getSetCCResultType(Node->getValueType(0));
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); SDValue Zero = DAG.getConstant(0, LHS.getValueType());
// LHSSign -> LHS >= 0 // LHSSign -> LHS >= 0
// RHSSign -> RHS >= 0 // RHSSign -> RHS >= 0
@ -3720,9 +3695,9 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1));
} else { } else {
// We can fall back to a libcall with an illegal type for the MUL if we // We can fall back to a libcall with an illegal type for the MUL if we
// have a libcall big enough. // have a libcall big enough.
@ -3743,11 +3718,9 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// part. // part.
unsigned LoSize = VT.getSizeInBits(); unsigned LoSize = VT.getSizeInBits();
SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
DAG.getConstant(LoSize - 1, dl, DAG.getConstant(LoSize-1, TLI.getPointerTy()));
TLI.getPointerTy()));
SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
DAG.getConstant(LoSize - 1, dl, DAG.getConstant(LoSize-1, TLI.getPointerTy()));
TLI.getPointerTy()));
// Here we're passing the 2 arguments explicitly as 4 arguments that are // Here we're passing the 2 arguments explicitly as 4 arguments that are
// pre-lowered to the correct types. This all depends upon WideVT not // pre-lowered to the correct types. This all depends upon WideVT not
@ -3756,9 +3729,9 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1));
// Ret is a node with an illegal type. Because such things are not // Ret is a node with an illegal type. Because such things are not
// generally permitted during this phase of legalization, make sure the // generally permitted during this phase of legalization, make sure the
// node has no more uses. The above EXTRACT_ELEMENT nodes should have been // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
@ -3768,14 +3741,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
} }
if (isSigned) { if (isSigned) {
Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, dl, Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
TLI.getShiftAmountTy(BottomHalf.getValueType())); TLI.getShiftAmountTy(BottomHalf.getValueType()));
Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1, TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
ISD::SETNE); ISD::SETNE);
} else { } else {
TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
DAG.getConstant(0, dl, VT), ISD::SETNE); DAG.getConstant(0, VT), ISD::SETNE);
} }
Results.push_back(BottomHalf); Results.push_back(BottomHalf);
Results.push_back(TopHalf); Results.push_back(TopHalf);
@ -3786,7 +3759,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
DAG.getConstant(PairTy.getSizeInBits()/2, dl, DAG.getConstant(PairTy.getSizeInBits()/2,
TLI.getShiftAmountTy(PairTy))); TLI.getShiftAmountTy(PairTy)));
Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
break; break;
@ -3801,7 +3774,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
} else { } else {
Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp1 = DAG.getSelectCC(dl, Tmp1,
DAG.getConstant(0, dl, Tmp1.getValueType()), DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE); Tmp2, Tmp3, ISD::SETNE);
} }
Results.push_back(Tmp1); Results.push_back(Tmp1);
@ -3817,8 +3790,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
unsigned EntrySize = unsigned EntrySize =
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index, Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
DAG.getConstant(EntrySize, dl, Index.getValueType())); Index, DAG.getConstant(EntrySize, Index.getValueType()));
SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(), SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
Index, Table); Index, Table);
@ -3852,10 +3825,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// We test only the i1 bit. Skip the AND if UNDEF. // We test only the i1 bit. Skip the AND if UNDEF.
Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 : Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
DAG.getConstant(1, dl, Tmp2.getValueType())); DAG.getConstant(1, Tmp2.getValueType()));
Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp3, DAG.getCondCode(ISD::SETNE), Tmp3,
DAG.getConstant(0, dl, Tmp3.getValueType()), DAG.getConstant(0, Tmp3.getValueType()),
Node->getOperand(2)); Node->getOperand(2));
} }
Results.push_back(Tmp1); Results.push_back(Tmp1);
@ -3897,8 +3870,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
break; break;
} }
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getConstant(TrueValue, dl, VT), DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
DAG.getConstant(0, dl, VT),
Tmp3); Tmp3);
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
@ -3966,7 +3938,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
Tmp1, Tmp2, Tmp3, Tmp4, CC); Tmp1, Tmp2, Tmp3, Tmp4, CC);
} else { } else {
Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType()); Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
CC = DAG.getCondCode(ISD::SETNE); CC = DAG.getCondCode(ISD::SETNE);
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
Tmp2, Tmp3, Tmp4, CC); Tmp2, Tmp3, Tmp4, CC);
@ -3997,7 +3969,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
Tmp4, Tmp2, Tmp3, Node->getOperand(4)); Tmp4, Tmp2, Tmp3, Node->getOperand(4));
} else { } else {
Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType()); Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
Tmp4 = DAG.getCondCode(ISD::SETNE); Tmp4 = DAG.getCondCode(ISD::SETNE);
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
Tmp2, Tmp3, Node->getOperand(4)); Tmp2, Tmp3, Node->getOperand(4));
@ -4021,12 +3993,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
for (unsigned Idx = 0; Idx < NumElem; Idx++) { for (unsigned Idx = 0; Idx < NumElem; Idx++) {
SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
VT.getScalarType(), VT.getScalarType(),
Node->getOperand(0), Node->getOperand(0), DAG.getConstant(Idx,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
VT.getScalarType(), VT.getScalarType(),
Node->getOperand(1), Node->getOperand(1), DAG.getConstant(Idx,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
Scalars.push_back(DAG.getNode(Node->getOpcode(), dl, Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
VT.getScalarType(), Ex, Sh)); VT.getScalarType(), Ex, Sh));
} }
@ -4080,16 +4052,16 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
if (Node->getOpcode() == ISD::CTTZ) { if (Node->getOpcode() == ISD::CTTZ) {
// FIXME: This should set a bit in the zero extended value instead. // FIXME: This should set a bit in the zero extended value instead.
Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT), Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
ISD::SETEQ); ISD::SETEQ);
Tmp1 = DAG.getSelect(dl, NVT, Tmp2, Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1); DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
} else if (Node->getOpcode() == ISD::CTLZ || } else if (Node->getOpcode() == ISD::CTLZ ||
Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
DAG.getConstant(NVT.getSizeInBits() - DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), dl, NVT)); OVT.getSizeInBits(), NVT));
} }
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
break; break;
@ -4098,8 +4070,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(DiffBits, dl, DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
TLI.getShiftAmountTy(NVT)));
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
} }
@ -4189,7 +4160,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
else else
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
} }
@ -4246,7 +4217,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
Tmp3, DAG.getIntPtrConstant(0, dl))); Tmp3, DAG.getIntPtrConstant(0)));
break; break;
} }
case ISD::FMA: { case ISD::FMA: {
@ -4256,7 +4227,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Results.push_back( Results.push_back(
DAG.getNode(ISD::FP_ROUND, dl, OVT, DAG.getNode(ISD::FP_ROUND, dl, OVT,
DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3), DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
DAG.getIntPtrConstant(0, dl))); DAG.getIntPtrConstant(0)));
break; break;
} }
case ISD::FPOWI: { case ISD::FPOWI: {
@ -4264,7 +4235,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp2 = Node->getOperand(1); Tmp2 = Node->getOperand(1);
Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
Tmp3, DAG.getIntPtrConstant(0, dl))); Tmp3, DAG.getIntPtrConstant(0)));
break; break;
} }
case ISD::FFLOOR: case ISD::FFLOOR:
@ -4286,7 +4257,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
Tmp2, DAG.getIntPtrConstant(0, dl))); Tmp2, DAG.getIntPtrConstant(0)));
break; break;
} }
} }

67
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
View File

@ -131,7 +131,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
} }
SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
return DAG.getConstant(N->getValueAPF().bitcastToAPInt(), SDLoc(N), return DAG.getConstant(N->getValueAPF().bitcastToAPInt(),
TLI.getTypeToTransformTo(*DAG.getContext(), TLI.getTypeToTransformTo(*DAG.getContext(),
N->getValueType(0))); N->getValueType(0)));
} }
@ -149,8 +149,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
// Mask = ~(1 << (Size-1)) // Mask = ~(1 << (Size-1))
APInt API = APInt::getAllOnesValue(Size); APInt API = APInt::getAllOnesValue(Size);
API.clearBit(Size - 1); API.clearBit(Size-1);
SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT); SDValue Mask = DAG.getConstant(API, NVT);
SDValue Op = GetSoftenedFloat(N->getOperand(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0));
return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask); return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
} }
@ -218,8 +218,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
unsigned RSize = RVT.getSizeInBits(); unsigned RSize = RVT.getSizeInBits();
// First get the sign bit of second operand. // First get the sign bit of second operand.
SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT), SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, RVT),
DAG.getConstant(RSize - 1, dl, DAG.getConstant(RSize - 1,
TLI.getShiftAmountTy(RVT))); TLI.getShiftAmountTy(RVT)));
SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
@ -227,21 +227,21 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits(); int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
if (SizeDiff > 0) { if (SizeDiff > 0) {
SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit, SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit,
DAG.getConstant(SizeDiff, dl, DAG.getConstant(SizeDiff,
TLI.getShiftAmountTy(SignBit.getValueType()))); TLI.getShiftAmountTy(SignBit.getValueType())));
SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
} else if (SizeDiff < 0) { } else if (SizeDiff < 0) {
SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit, SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit,
DAG.getConstant(-SizeDiff, dl, DAG.getConstant(-SizeDiff,
TLI.getShiftAmountTy(SignBit.getValueType()))); TLI.getShiftAmountTy(SignBit.getValueType())));
} }
// Clear the sign bit of the first operand. // Clear the sign bit of the first operand.
SDValue Mask = DAG.getNode(ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT), SDValue Mask = DAG.getNode(ISD::SHL, dl, LVT, DAG.getConstant(1, LVT),
DAG.getConstant(LSize - 1, dl, DAG.getConstant(LSize - 1,
TLI.getShiftAmountTy(LVT))); TLI.getShiftAmountTy(LVT)));
Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT)); Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, LVT));
LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask); LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
// Or the value with the sign bit. // Or the value with the sign bit.
@ -386,9 +386,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N);
// Expand Y = FNEG(X) -> Y = SUB -0.0, X // Expand Y = FNEG(X) -> Y = SUB -0.0, X
SDValue Ops[2] = { DAG.getConstantFP(-0.0, dl, N->getValueType(0)), SDValue Ops[2] = { DAG.getConstantFP(-0.0, N->getValueType(0)),
GetSoftenedFloat(N->getOperand(0)) }; GetSoftenedFloat(N->getOperand(0)) };
return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0), return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
RTLIB::SUB_F32, RTLIB::SUB_F32,
@ -396,7 +395,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
RTLIB::SUB_F80, RTLIB::SUB_F80,
RTLIB::SUB_F128, RTLIB::SUB_F128,
RTLIB::SUB_PPCF128), RTLIB::SUB_PPCF128),
NVT, Ops, 2, false, dl).first; NVT, Ops, 2, false, SDLoc(N)).first;
} }
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
@ -756,7 +755,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
// If softenSetCCOperands returned a scalar, we need to compare the result // If softenSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -795,7 +794,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
// If softenSetCCOperands returned a scalar, we need to compare the result // If softenSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -838,7 +837,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
if (ST->isTruncatingStore()) if (ST->isTruncatingStore())
// Do an FP_ROUND followed by a non-truncating store. // Do an FP_ROUND followed by a non-truncating store.
Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
Val, DAG.getIntPtrConstant(0, dl))); Val, DAG.getIntPtrConstant(0)));
else else
Val = GetSoftenedFloat(Val); Val = GetSoftenedFloat(Val);
@ -928,13 +927,12 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
assert(NVT.getSizeInBits() == integerPartWidth && assert(NVT.getSizeInBits() == integerPartWidth &&
"Do not know how to expand this float constant!"); "Do not know how to expand this float constant!");
APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt(); APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
SDLoc dl(N);
Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
APInt(integerPartWidth, C.getRawData()[1])), APInt(integerPartWidth, C.getRawData()[1])),
dl, NVT); NVT);
Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
APInt(integerPartWidth, C.getRawData()[0])), APInt(integerPartWidth, C.getRawData()[0])),
dl, NVT); NVT);
} }
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
@ -1138,10 +1136,9 @@ void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
SDValue &Hi) { SDValue &Hi) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N); Hi = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
APInt(NVT.getSizeInBits(), 0)), dl, NVT); APInt(NVT.getSizeInBits(), 0)), NVT);
} }
void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N, void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
@ -1265,7 +1262,7 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
// The low part is zero. // The low part is zero.
Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
APInt(NVT.getSizeInBits(), 0)), dl, NVT); APInt(NVT.getSizeInBits(), 0)), NVT);
// Modified the chain - switch anything that used the old chain to use the // Modified the chain - switch anything that used the old chain to use the
// new one. // new one.
@ -1290,7 +1287,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
MVT::i32, Src); MVT::i32, Src);
Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT), Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
APInt(NVT.getSizeInBits(), 0)), dl, NVT); APInt(NVT.getSizeInBits(), 0)), NVT);
Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
} else { } else {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
@ -1338,8 +1335,8 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
DAG.getConstantFP(APFloat(APFloat::PPCDoubleDouble, DAG.getConstantFP(APFloat(APFloat::PPCDoubleDouble,
APInt(128, Parts)), APInt(128, Parts)),
dl, MVT::ppcf128)); MVT::ppcf128));
Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT), Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, SrcVT),
Lo, Hi, ISD::SETLT); Lo, Hi, ISD::SETLT);
GetPairElements(Lo, Lo, Hi); GetPairElements(Lo, Lo, Hi);
} }
@ -1439,7 +1436,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
// If ExpandSetCCOperands returned a scalar, we need to compare the result // If ExpandSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -1482,7 +1479,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
N->getOperand(0), DAG.getValueType(MVT::f64)); N->getOperand(0), DAG.getValueType(MVT::f64));
Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
} }
@ -1502,7 +1499,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
"Logic only correct for ppcf128!"); "Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APFloat::PPCDoubleDouble, APInt(128, TwoE31)); APFloat APF = APFloat(APFloat::PPCDoubleDouble, APInt(128, TwoE31));
SDValue Tmp = DAG.getConstantFP(APF, dl, MVT::ppcf128); SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks. // FIXME: generated code sucks.
return DAG.getSelectCC(dl, N->getOperand(0), Tmp, return DAG.getSelectCC(dl, N->getOperand(0), Tmp,
@ -1512,8 +1509,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
MVT::ppcf128, MVT::ppcf128,
N->getOperand(0), N->getOperand(0),
Tmp)), Tmp)),
DAG.getConstant(0x80000000, dl, DAG.getConstant(0x80000000, MVT::i32)),
MVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, dl, DAG.getNode(ISD::FP_TO_SINT, dl,
MVT::i32, N->getOperand(0)), MVT::i32, N->getOperand(0)),
ISD::SETGE); ISD::SETGE);
@ -1533,7 +1529,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
// If ExpandSetCCOperands returned a scalar, we need to compare the result // If ExpandSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -1797,18 +1793,17 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) { SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N); ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc DL(N);
// Get the (bit-cast) APInt of the APFloat and build an integer constant // Get the (bit-cast) APInt of the APFloat and build an integer constant
EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(), DL, SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(),
IVT); IVT);
// Convert the Constant to the desired FP type // Convert the Constant to the desired FP type
// FIXME We might be able to do the conversion during compilation and get rid // FIXME We might be able to do the conversion during compilation and get rid
// of it from the object code // of it from the object code
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, C); return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, C);
} }
// If the Index operand is a constant, try to redirect the extract operation to // If the Index operand is a constant, try to redirect the extract operation to
@ -1851,7 +1846,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx); Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
else else
Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi, Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
DAG.getConstant(IdxVal - LoElts, DL, DAG.getConstant(IdxVal - LoElts,
Idx.getValueType())); Idx.getValueType()));
ReplaceValueWith(SDValue(N, 0), Res); ReplaceValueWith(SDValue(N, 0), Res);
return SDValue(); return SDValue();

182
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -307,7 +307,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(); unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
DAG.getConstant(DiffBits, dl, TLI.getShiftAmountTy(NVT))); DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
} }
SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
@ -355,7 +355,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// Subtract off the extra leading bits in the bigger type. // Subtract off the extra leading bits in the bigger type.
return DAG.getNode( return DAG.getNode(
ISD::SUB, dl, NVT, Op, ISD::SUB, dl, NVT, Op,
DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(),
NVT)); NVT));
} }
@ -376,7 +376,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
// the top of the original type. // the top of the original type.
auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(), auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
OVT.getScalarSizeInBits()); OVT.getScalarSizeInBits());
Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT)); Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
} }
return DAG.getNode(N->getOpcode(), dl, NVT, Op); return DAG.getNode(N->getOpcode(), dl, NVT, Op);
} }
@ -733,11 +733,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
if (N->getOpcode() == ISD::UMULO) { if (N->getOpcode() == ISD::UMULO) {
// Unsigned overflow occurred if the high part is non-zero. // Unsigned overflow occurred if the high part is non-zero.
SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
DAG.getIntPtrConstant(SmallVT.getSizeInBits(), DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
DL));
Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
DAG.getConstant(0, DL, Hi.getValueType()), DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
ISD::SETNE);
} else { } else {
// Signed overflow occurred if the high part does not sign extend the low. // Signed overflow occurred if the high part does not sign extend the low.
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
@ -796,7 +794,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
// Shift it to the right position and "or" it in. // Shift it to the right position and "or" it in.
Part = DAG.getNode(ISD::SHL, dl, NVT, Part, Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
DAG.getConstant(i*RegVT.getSizeInBits(), dl, DAG.getConstant(i * RegVT.getSizeInBits(),
TLI.getPointerTy())); TLI.getPointerTy()));
Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
} }
@ -989,8 +987,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
SDLoc dl(N); SDLoc dl(N);
Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
DAG.getConstant(OVT.getSizeInBits(), dl, DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
TLI.getPointerTy()));
return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
} }
@ -1160,7 +1157,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpN
unsigned NumConcat = WidenNumElts / MaskNumElts; unsigned NumConcat = WidenNumElts / MaskNumElts;
SmallVector<SDValue, 16> Ops(NumConcat); SmallVector<SDValue, 16> Ops(NumConcat);
SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT); SDValue ZeroVal = DAG.getConstant(0, MaskVT);
Ops[0] = Mask; Ops[0] = Mask;
for (unsigned i = 1; i != NumConcat; ++i) for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = ZeroVal; Ops[i] = ZeroVal;
@ -1366,13 +1363,13 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
if (N->getOpcode() == ISD::SHL) { if (N->getOpcode() == ISD::SHL) {
if (Amt > VTBits) { if (Amt > VTBits) {
Lo = Hi = DAG.getConstant(0, DL, NVT); Lo = Hi = DAG.getConstant(0, NVT);
} else if (Amt > NVTBits) { } else if (Amt > NVTBits) {
Lo = DAG.getConstant(0, DL, NVT); Lo = DAG.getConstant(0, NVT);
Hi = DAG.getNode(ISD::SHL, DL, Hi = DAG.getNode(ISD::SHL, DL,
NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy)); NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
} else if (Amt == NVTBits) { } else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, DL, NVT); Lo = DAG.getConstant(0, NVT);
Hi = InL; Hi = InL;
} else if (Amt == 1 && } else if (Amt == 1 &&
TLI.isOperationLegalOrCustom(ISD::ADDC, TLI.isOperationLegalOrCustom(ISD::ADDC,
@ -1384,34 +1381,34 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps); Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
} else { } else {
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy)); Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
Hi = DAG.getNode(ISD::OR, DL, NVT, Hi = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SHL, DL, NVT, InH, DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(Amt, DL, ShTy)), DAG.getConstant(Amt, ShTy)),
DAG.getNode(ISD::SRL, DL, NVT, InL, DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(NVTBits - Amt, DL, ShTy))); DAG.getConstant(NVTBits-Amt, ShTy)));
} }
return; return;
} }
if (N->getOpcode() == ISD::SRL) { if (N->getOpcode() == ISD::SRL) {
if (Amt > VTBits) { if (Amt > VTBits) {
Lo = DAG.getConstant(0, DL, NVT); Lo = DAG.getConstant(0, NVT);
Hi = DAG.getConstant(0, DL, NVT); Hi = DAG.getConstant(0, NVT);
} else if (Amt > NVTBits) { } else if (Amt > NVTBits) {
Lo = DAG.getNode(ISD::SRL, DL, Lo = DAG.getNode(ISD::SRL, DL,
NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy)); NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
Hi = DAG.getConstant(0, DL, NVT); Hi = DAG.getConstant(0, NVT);
} else if (Amt == NVTBits) { } else if (Amt == NVTBits) {
Lo = InH; Lo = InH;
Hi = DAG.getConstant(0, DL, NVT); Hi = DAG.getConstant(0, NVT);
} else { } else {
Lo = DAG.getNode(ISD::OR, DL, NVT, Lo = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL, DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)), DAG.getConstant(Amt, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH, DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(NVTBits - Amt, DL, ShTy))); DAG.getConstant(NVTBits-Amt, ShTy)));
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
} }
return; return;
} }
@ -1419,23 +1416,23 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
if (Amt > VTBits) { if (Amt > VTBits) {
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else if (Amt > NVTBits) { } else if (Amt > NVTBits) {
Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(Amt-NVTBits, DL, ShTy)); DAG.getConstant(Amt-NVTBits, ShTy));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else if (Amt == NVTBits) { } else if (Amt == NVTBits) {
Lo = InH; Lo = InH;
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
} else { } else {
Lo = DAG.getNode(ISD::OR, DL, NVT, Lo = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL, DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)), DAG.getConstant(Amt, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH, DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(NVTBits - Amt, DL, ShTy))); DAG.getConstant(NVTBits-Amt, ShTy)));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
} }
} }
@ -1471,21 +1468,21 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
if (KnownOne.intersects(HighBitMask)) { if (KnownOne.intersects(HighBitMask)) {
// Mask out the high bit, which we know is set. // Mask out the high bit, which we know is set.
Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
DAG.getConstant(~HighBitMask, dl, ShTy)); DAG.getConstant(~HighBitMask, ShTy));
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: llvm_unreachable("Unknown shift"); default: llvm_unreachable("Unknown shift");
case ISD::SHL: case ISD::SHL:
Lo = DAG.getConstant(0, dl, NVT); // Low part is zero. Lo = DAG.getConstant(0, NVT); // Low part is zero.
Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
return true; return true;
case ISD::SRL: case ISD::SRL:
Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero. Hi = DAG.getConstant(0, NVT); // Hi part is zero.
Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
return true; return true;
case ISD::SRA: case ISD::SRA:
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
DAG.getConstant(NVTBits - 1, dl, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
return true; return true;
} }
@ -1498,7 +1495,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
// shift if x is zero. We can use XOR here because x is known to be smaller // shift if x is zero. We can use XOR here because x is known to be smaller
// than 32. // than 32.
SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
DAG.getConstant(NVTBits - 1, dl, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
unsigned Op1, Op2; unsigned Op1, Op2;
switch (N->getOpcode()) { switch (N->getOpcode()) {
@ -1514,7 +1511,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Use a little trick to get the bits that move from Lo to Hi. First // Use a little trick to get the bits that move from Lo to Hi. First
// shift by one bit. // shift by one bit.
SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy)); SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
// Then compute the remaining shift with amount-1. // Then compute the remaining shift with amount-1.
SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
@ -1545,13 +1542,13 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue InL, InH; SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH); GetExpandedInteger(N->getOperand(0), InL, InH);
SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy); SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy), SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
Amt, NVBitsNode, ISD::SETULT); Amt, NVBitsNode, ISD::SETULT);
SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy), SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
Amt, DAG.getConstant(0, dl, ShTy), Amt, DAG.getConstant(0, ShTy),
ISD::SETEQ); ISD::SETEQ);
SDValue LoS, HiS, LoL, HiL; SDValue LoS, HiS, LoL, HiL;
@ -1565,7 +1562,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
// Long: ShAmt >= NVTBits // Long: ShAmt >= NVTBits
LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero. LoL = DAG.getConstant(0, NVT); // Lo part is zero.
HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL); Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
@ -1582,7 +1579,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
// Long: ShAmt >= NVTBits // Long: ShAmt >= NVTBits
HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero. HiL = DAG.getConstant(0, NVT); // Hi part is zero.
LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
Lo = DAG.getSelect(dl, NVT, isZero, InL, Lo = DAG.getSelect(dl, NVT, isZero, InL,
@ -1598,7 +1595,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Long: ShAmt >= NVTBits // Long: ShAmt >= NVTBits
HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
DAG.getConstant(NVTBits - 1, dl, ShTy)); DAG.getConstant(NVTBits-1, ShTy));
LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
Lo = DAG.getSelect(dl, NVT, isZero, InL, Lo = DAG.getSelect(dl, NVT, isZero, InL,
@ -1650,12 +1647,12 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0], SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
ISD::SETULT); ISD::SETULT);
SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1, SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
DAG.getConstant(1, dl, NVT), DAG.getConstant(1, NVT),
DAG.getConstant(0, dl, NVT)); DAG.getConstant(0, NVT));
SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1], SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
ISD::SETULT); ISD::SETULT);
SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2, SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
DAG.getConstant(1, dl, NVT), Carry1); DAG.getConstant(1, NVT), Carry1);
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
} else { } else {
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps); Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
@ -1664,8 +1661,8 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()), DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
LoOps[0], LoOps[1], ISD::SETULT); LoOps[0], LoOps[1], ISD::SETULT);
SDValue Borrow = DAG.getSelect(dl, NVT, Cmp, SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
DAG.getConstant(1, dl, NVT), DAG.getConstant(1, NVT),
DAG.getConstant(0, dl, NVT)); DAG.getConstant(0, NVT));
Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
} }
} }
@ -1762,7 +1759,7 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part replicates the sign bit of Lo, make it explicit. // The high part replicates the sign bit of Lo, make it explicit.
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(NVTBits - 1, dl, TLI.getPointerTy())); DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
} }
} }
@ -1782,7 +1779,7 @@ void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
} else { } else {
Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part must be zero, make it explicit. // The high part must be zero, make it explicit.
Hi = DAG.getConstant(0, dl, NVT); Hi = DAG.getConstant(0, NVT);
} }
} }
@ -1802,9 +1799,8 @@ void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
const APInt &Cst = Constant->getAPIntValue(); const APInt &Cst = Constant->getAPIntValue();
bool IsTarget = Constant->isTargetOpcode(); bool IsTarget = Constant->isTargetOpcode();
bool IsOpaque = Constant->isOpaque(); bool IsOpaque = Constant->isOpaque();
SDLoc dl(N); Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque); Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
IsOpaque); IsOpaque);
} }
@ -1816,16 +1812,15 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
EVT NVT = Lo.getValueType(); EVT NVT = Lo.getValueType();
SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi, SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
DAG.getConstant(0, dl, NVT), ISD::SETNE); DAG.getConstant(0, NVT), ISD::SETNE);
SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo); SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi); SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ, Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
DAG.getNode(ISD::ADD, dl, NVT, LoLZ, DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
DAG.getConstant(NVT.getSizeInBits(), dl, DAG.getConstant(NVT.getSizeInBits(), NVT)));
NVT))); Hi = DAG.getConstant(0, NVT);
Hi = DAG.getConstant(0, dl, NVT);
} }
void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
@ -1836,7 +1831,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
EVT NVT = Lo.getValueType(); EVT NVT = Lo.getValueType();
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, dl, NVT); Hi = DAG.getConstant(0, NVT);
} }
void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
@ -1847,16 +1842,15 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
EVT NVT = Lo.getValueType(); EVT NVT = Lo.getValueType();
SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
DAG.getConstant(0, dl, NVT), ISD::SETNE); DAG.getConstant(0, NVT), ISD::SETNE);
SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi); SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ, Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
DAG.getNode(ISD::ADD, dl, NVT, HiLZ, DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
DAG.getConstant(NVT.getSizeInBits(), dl, DAG.getConstant(NVT.getSizeInBits(), NVT)));
NVT))); Hi = DAG.getConstant(0, NVT);
Hi = DAG.getConstant(0, dl, NVT);
} }
void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
@ -1929,10 +1923,10 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
// lo part. // lo part.
unsigned LoSize = Lo.getValueType().getSizeInBits(); unsigned LoSize = Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy())); DAG.getConstant(LoSize-1, TLI.getPointerTy()));
} else if (ExtType == ISD::ZEXTLOAD) { } else if (ExtType == ISD::ZEXTLOAD) {
// The high part is just a zero. // The high part is just a zero.
Hi = DAG.getConstant(0, dl, NVT); Hi = DAG.getConstant(0, NVT);
} else { } else {
assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
// The high part is undefined. // The high part is undefined.
@ -1951,7 +1945,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
// Increment the pointer to the other half. // Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), NEVT, N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
isVolatile, isNonTemporal, isInvariant, isVolatile, isNonTemporal, isInvariant,
@ -1978,7 +1972,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
// Increment the pointer to the other half. // Increment the pointer to the other half.
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
// Load the rest of the low bits. // Load the rest of the low bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), N->getPointerInfo().getWithOffset(IncrementSize),
@ -1995,12 +1989,12 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
// Transfer low bits from the bottom of Hi to the top of Lo. // Transfer low bits from the bottom of Hi to the top of Lo.
Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
DAG.getNode(ISD::SHL, dl, NVT, Hi, DAG.getNode(ISD::SHL, dl, NVT, Hi,
DAG.getConstant(ExcessBits, dl, DAG.getConstant(ExcessBits,
TLI.getPointerTy()))); TLI.getPointerTy())));
// Move high bits to the right position in Hi. // Move high bits to the right position in Hi.
Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
NVT, Hi, NVT, Hi,
DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl, DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getPointerTy())); TLI.getPointerTy()));
} }
} }
@ -2076,7 +2070,7 @@ void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
// Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
// //
EVT OType = Node->getValueType(1); EVT OType = Node->getValueType(1);
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); SDValue Zero = DAG.getConstant(0, LHS.getValueType());
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
@ -2225,7 +2219,7 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
// The high part is obtained by SRA'ing all but one of the bits of low part. // The high part is obtained by SRA'ing all but one of the bits of low part.
unsigned LoSize = NVT.getSizeInBits(); unsigned LoSize = NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy())); DAG.getConstant(LoSize-1, TLI.getPointerTy()));
} else { } else {
// For example, extension of an i48 to an i64. The operand type necessarily // For example, extension of an i48 to an i64. The operand type necessarily
// promotes to the result type, so will end up being expanded too. // promotes to the result type, so will end up being expanded too.
@ -2259,7 +2253,7 @@ ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
// The high part gets the sign extension from the lo-part. This handles // The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8. // things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl, DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
TLI.getPointerTy())); TLI.getPointerTy()));
} else { } else {
// For example, extension of an i48 to an i64. Leave the low part alone, // For example, extension of an i48 to an i64. Leave the low part alone,
@ -2299,8 +2293,7 @@ void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::SRL, dl, Hi = DAG.getNode(ISD::SRL, dl,
N->getOperand(0).getValueType(), N->getOperand(0), N->getOperand(0).getValueType(), N->getOperand(0),
DAG.getConstant(NVT.getSizeInBits(), dl, DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
TLI.getPointerTy()));
Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
} }
@ -2342,14 +2335,14 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
// A divide for UMULO will be faster than a function call. Select to // A divide for UMULO will be faster than a function call. Select to
// make sure we aren't using 0. // make sure we aren't using 0.
SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT), SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ); RHS, DAG.getConstant(0, VT), ISD::SETEQ);
SDValue NotZero = DAG.getSelect(dl, VT, isZero, SDValue NotZero = DAG.getSelect(dl, VT, isZero,
DAG.getConstant(1, dl, VT), RHS); DAG.getConstant(1, VT), RHS);
SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero); SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS, SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
ISD::SETNE); ISD::SETNE);
Overflow = DAG.getSelect(dl, N->getValueType(1), isZero, Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
DAG.getConstant(0, dl, N->getValueType(1)), DAG.getConstant(0, N->getValueType(1)),
Overflow); Overflow);
ReplaceValueWith(SDValue(N, 1), Overflow); ReplaceValueWith(SDValue(N, 1), Overflow);
return; return;
@ -2372,7 +2365,7 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
SDValue Temp = DAG.CreateStackTemporary(PtrVT); SDValue Temp = DAG.CreateStackTemporary(PtrVT);
// Temporary for the overflow value, default it to zero. // Temporary for the overflow value, default it to zero.
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
DAG.getConstant(0, dl, PtrVT), Temp, DAG.getConstant(0, PtrVT), Temp,
MachinePointerInfo(), false, false, 0); MachinePointerInfo(), false, false, 0);
TargetLowering::ArgListTy Args; TargetLowering::ArgListTy Args;
@ -2407,7 +2400,7 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2, SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
DAG.getConstant(0, dl, PtrVT), DAG.getConstant(0, PtrVT),
ISD::SETNE); ISD::SETNE);
// Use the overflow from the libcall everywhere. // Use the overflow from the libcall everywhere.
ReplaceValueWith(SDValue(N, 1), Ofl); ReplaceValueWith(SDValue(N, 1), Ofl);
@ -2461,7 +2454,7 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
if (Op.getValueType().bitsLE(NVT)) { if (Op.getValueType().bitsLE(NVT)) {
// The low part is zero extension of the input (degenerates to a copy). // The low part is zero extension of the input (degenerates to a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero. Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
} else { } else {
// For example, extension of an i48 to an i64. The operand type necessarily // For example, extension of an i48 to an i64. The operand type necessarily
// promotes to the result type, so will end up being expanded too. // promotes to the result type, so will end up being expanded too.
@ -2486,7 +2479,7 @@ void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
SDLoc dl(N); SDLoc dl(N);
EVT VT = cast<AtomicSDNode>(N)->getMemoryVT(); EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other); SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
SDValue Zero = DAG.getConstant(0, dl, VT); SDValue Zero = DAG.getConstant(0, VT);
SDValue Swap = DAG.getAtomicCmpSwap( SDValue Swap = DAG.getAtomicCmpSwap(
ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0), cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
@ -2587,7 +2580,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
return; return;
} }
@ -2676,7 +2669,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
// If ExpandSetCCOperands returned a scalar, we need to compare the result // If ExpandSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -2694,7 +2687,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
// If ExpandSetCCOperands returned a scalar, we need to compare the result // If ExpandSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values. // against zero to select between true and false values.
if (!NewRHS.getNode()) { if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType()); NewRHS = DAG.getConstant(0, NewLHS.getValueType());
CCCode = ISD::SETNE; CCCode = ISD::SETNE;
} }
@ -2789,7 +2782,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Increment the pointer to the other half. // Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), N->getPointerInfo().getWithOffset(IncrementSize),
NEVT, isVolatile, isNonTemporal, NEVT, isVolatile, isNonTemporal,
@ -2811,11 +2804,11 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
if (ExcessBits < NVT.getSizeInBits()) { if (ExcessBits < NVT.getSizeInBits()) {
// Transfer high bits from the top of Lo to the bottom of Hi. // Transfer high bits from the top of Lo to the bottom of Hi.
Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl, DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getPointerTy())); TLI.getPointerTy()));
Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
DAG.getNode(ISD::SRL, dl, NVT, Lo, DAG.getNode(ISD::SRL, dl, NVT, Lo,
DAG.getConstant(ExcessBits, dl, DAG.getConstant(ExcessBits,
TLI.getPointerTy()))); TLI.getPointerTy())));
} }
@ -2825,7 +2818,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Increment the pointer to the other half. // Increment the pointer to the other half.
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
// Store the lowest ExcessBits bits in the second half. // Store the lowest ExcessBits bits in the second half.
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), N->getPointerInfo().getWithOffset(IncrementSize),
@ -2881,8 +2874,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
GetExpandedInteger(Op, Lo, Hi); GetExpandedInteger(Op, Lo, Hi);
SDValue SignSet = DAG.getSetCC(dl, SDValue SignSet = DAG.getSetCC(dl,
getSetCCResultType(Hi.getValueType()), getSetCCResultType(Hi.getValueType()),
Hi, Hi, DAG.getConstant(0, Hi.getValueType()),
DAG.getConstant(0, dl, Hi.getValueType()),
ISD::SETLT); ISD::SETLT);
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
@ -2891,8 +2883,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
TLI.getPointerTy()); TLI.getPointerTy());
// Get a pointer to FF if the sign bit was set, or to 0 otherwise. // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
SDValue Zero = DAG.getIntPtrConstant(0, dl); SDValue Zero = DAG.getIntPtrConstant(0);
SDValue Four = DAG.getIntPtrConstant(4, dl); SDValue Four = DAG.getIntPtrConstant(4);
if (TLI.isBigEndian()) std::swap(Zero, Four); if (TLI.isBigEndian()) std::swap(Zero, Four);
SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet, SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
Zero, Four); Zero, Four);
@ -2950,7 +2942,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
// Extract the element from the original vector. // Extract the element from the original vector.
SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType())); BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
InVT.getVectorElementType(), N->getOperand(0), Index); InVT.getVectorElementType(), N->getOperand(0), Index);
@ -3044,7 +3036,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
SDValue Op = N->getOperand(i); SDValue Op = N->getOperand(i);
for (unsigned j = 0; j < NumElem; ++j) { for (unsigned j = 0; j < NumElem; ++j) {
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
InElemTy, Op, DAG.getConstant(j, dl, InElemTy, Op, DAG.getConstant(j,
TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext); Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
} }
@ -3100,7 +3092,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
for (unsigned i=0; i<NumElem; ++i) { for (unsigned i=0; i<NumElem; ++i) {
// Extract element from incoming vector // Extract element from incoming vector
SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
Incoming, DAG.getConstant(i, dl, TLI.getVectorIdxTy())); Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
NewOps.push_back(Tr); NewOps.push_back(Tr);
} }

12
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -997,9 +997,9 @@ void DAGTypeLegalizer::GetPairElements(SDValue Pair,
SDLoc dl(Pair); SDLoc dl(Pair);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Pair.getValueType()); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Pair.getValueType());
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair, Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair, Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1));
} }
SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT,
@ -1012,7 +1012,7 @@ SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT,
unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size. unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index, Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
DAG.getConstant(EltSize, dl, Index.getValueType())); DAG.getConstant(EltSize, Index.getValueType()));
return DAG.getNode(ISD::ADD, dl, Index.getValueType(), Index, VecPtr); return DAG.getNode(ISD::ADD, dl, Index.getValueType(), Index, VecPtr);
} }
@ -1029,8 +1029,7 @@ SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi, Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
DAG.getConstant(LVT.getSizeInBits(), dlHi, DAG.getConstant(LVT.getSizeInBits(), TLI.getPointerTy()));
TLI.getPointerTy()));
return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi); return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
} }
@ -1116,8 +1115,7 @@ void DAGTypeLegalizer::SplitInteger(SDValue Op,
Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op);
Hi = DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op, Hi = DAG.getNode(ISD::SRL, dl, Op.getValueType(), Op,
DAG.getConstant(LoVT.getSizeInBits(), dl, DAG.getConstant(LoVT.getSizeInBits(), TLI.getPointerTy()));
TLI.getPointerTy()));
Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
} }

12
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -120,7 +120,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
SmallVector<SDValue, 8> Vals; SmallVector<SDValue, 8> Vals;
for (unsigned i = 0; i < NumElems; ++i) for (unsigned i = 0; i < NumElems; ++i)
Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT,
CastInOp, DAG.getConstant(i, dl, CastInOp, DAG.getConstant(i,
TLI.getVectorIdxTy()))); TLI.getVectorIdxTy())));
// Build Lo, Hi pair by pairing extracted elements if needed. // Build Lo, Hi pair by pairing extracted elements if needed.
@ -173,7 +173,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Increment the pointer to the other half. // Increment the pointer to the other half.
unsigned IncrementSize = NOutVT.getSizeInBits() / 8; unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize,
StackPtr.getValueType())); StackPtr.getValueType()));
// Load the second half from the stack slot. // Load the second half from the stack slot.
@ -238,7 +238,7 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
DAG.getConstant(1, dl, Idx.getValueType())); DAG.getConstant(1, Idx.getValueType()));
Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
if (TLI.isBigEndian()) if (TLI.isBigEndian())
@ -270,7 +270,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
// Increment the pointer to the other half. // Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits() / 8; unsigned IncrementSize = NVT.getSizeInBits() / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getLoad(NVT, dl, Chain, Ptr, Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
isVolatile, isNonTemporal, isInvariant, isVolatile, isNonTemporal, isInvariant,
@ -439,7 +439,7 @@ SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
Idx = DAG.getNode(ISD::ADD, dl, Idx = DAG.getNode(ISD::ADD, dl,
Idx.getValueType(), Idx, Idx.getValueType(), Idx,
DAG.getConstant(1, dl, Idx.getValueType())); DAG.getConstant(1, Idx.getValueType()));
NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
// Convert the new vector to the old vector type. // Convert the new vector to the old vector type.
@ -488,7 +488,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
isVolatile, isNonTemporal, Alignment, AAInfo); isVolatile, isNonTemporal, Alignment, AAInfo);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getStore(Chain, dl, Hi, Ptr, Hi = DAG.getStore(Chain, dl, Hi, Ptr,
St->getPointerInfo().getWithOffset(IncrementSize), St->getPointerInfo().getWithOffset(IncrementSize),
isVolatile, isNonTemporal, isVolatile, isNonTemporal,

53
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -407,7 +407,7 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
(VT.isVector() && VT.getVectorElementType().isFloatingPoint() && (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())) NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
else else
return DAG.getNode(ISD::BITCAST, dl, VT, Op); return DAG.getNode(ISD::BITCAST, dl, VT, Op);
} }
@ -536,8 +536,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
RemainingBytes -= LoadBytes; RemainingBytes -= LoadBytes;
Offset += LoadBytes; Offset += LoadBytes;
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
DAG.getConstant(LoadBytes, dl, DAG.getConstant(LoadBytes, BasePTR.getValueType()));
BasePTR.getValueType()));
LoadVals.push_back(ScalarLoad.getValue(0)); LoadVals.push_back(ScalarLoad.getValue(0));
LoadChains.push_back(ScalarLoad.getValue(1)); LoadChains.push_back(ScalarLoad.getValue(1));
@ -545,7 +544,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
// Extract bits, pack and extend/trunc them into destination type. // Extract bits, pack and extend/trunc them into destination type.
unsigned SrcEltBits = SrcEltVT.getSizeInBits(); unsigned SrcEltBits = SrcEltVT.getSizeInBits();
SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT); SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
unsigned BitOffset = 0; unsigned BitOffset = 0;
unsigned WideIdx = 0; unsigned WideIdx = 0;
@ -555,7 +554,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
SDValue Lo, Hi, ShAmt; SDValue Lo, Hi, ShAmt;
if (BitOffset < WideBits) { if (BitOffset < WideBits) {
ShAmt = DAG.getConstant(BitOffset, dl, TLI.getShiftAmountTy(WideVT)); ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask); Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
} }
@ -565,7 +564,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
WideIdx++; WideIdx++;
BitOffset -= WideBits; BitOffset -= WideBits;
if (BitOffset > 0) { if (BitOffset > 0) {
ShAmt = DAG.getConstant(SrcEltBits - BitOffset, dl, ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
TLI.getShiftAmountTy(WideVT)); TLI.getShiftAmountTy(WideVT));
Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask); Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
@ -584,7 +583,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT); Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
break; break;
case ISD::SEXTLOAD: case ISD::SEXTLOAD:
ShAmt = DAG.getConstant(WideBits - SrcEltBits, dl, ShAmt = DAG.getConstant(WideBits - SrcEltBits,
TLI.getShiftAmountTy(WideVT)); TLI.getShiftAmountTy(WideVT));
Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
@ -605,7 +604,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo()); MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
DAG.getConstant(Stride, dl, BasePTR.getValueType())); DAG.getConstant(Stride, BasePTR.getValueType()));
Vals.push_back(ScalarLoad.getValue(0)); Vals.push_back(ScalarLoad.getValue(0));
LoadChains.push_back(ScalarLoad.getValue(1)); LoadChains.push_back(ScalarLoad.getValue(1));
@ -656,7 +655,7 @@ SDValue VectorLegalizer::ExpandStore(SDValue Op) {
SmallVector<SDValue, 8> Stores; SmallVector<SDValue, 8> Stores;
for (unsigned Idx = 0; Idx < NumElem; Idx++) { for (unsigned Idx = 0; Idx < NumElem; Idx++) {
SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
RegSclVT, Value, DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())); RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
// This scalar TruncStore may be illegal, but we legalize it later. // This scalar TruncStore may be illegal, but we legalize it later.
SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR, SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
@ -665,7 +664,7 @@ SDValue VectorLegalizer::ExpandStore(SDValue Op) {
AAInfo); AAInfo);
BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
DAG.getConstant(Stride, dl, BasePTR.getValueType())); DAG.getConstant(Stride, BasePTR.getValueType()));
Stores.push_back(Store); Stores.push_back(Store);
} }
@ -735,9 +734,8 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
EVT BitTy = MaskTy.getScalarType(); EVT BitTy = MaskTy.getScalarType();
Mask = DAG.getSelect(DL, BitTy, Mask, Mask = DAG.getSelect(DL, BitTy, Mask,
DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
BitTy), DAG.getConstant(0, BitTy));
DAG.getConstant(0, DL, BitTy));
// Broadcast the mask so that the entire vector is all-one or all zero. // Broadcast the mask so that the entire vector is all-one or all zero.
SmallVector<SDValue, 8> Ops(NumElem, Mask); SmallVector<SDValue, 8> Ops(NumElem, Mask);
@ -750,7 +748,7 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
SDValue AllOnes = DAG.getConstant( SDValue AllOnes = DAG.getConstant(
APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy); APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
@ -772,7 +770,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
unsigned BW = VT.getScalarType().getSizeInBits(); unsigned BW = VT.getScalarType().getSizeInBits();
unsigned OrigBW = OrigTy.getScalarType().getSizeInBits(); unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
Op = Op.getOperand(0); Op = Op.getOperand(0);
Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
@ -819,7 +817,7 @@ SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
// without full scalarization than the sign extension does. // without full scalarization than the sign extension does.
unsigned EltWidth = VT.getVectorElementType().getSizeInBits(); unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits(); unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
return DAG.getNode(ISD::SRA, DL, VT, return DAG.getNode(ISD::SRA, DL, VT,
DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
ShiftAmount); ShiftAmount);
@ -838,7 +836,7 @@ SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
// Build up a zero vector to blend into this one. // Build up a zero vector to blend into this one.
EVT SrcScalarVT = SrcVT.getScalarType(); EVT SrcScalarVT = SrcVT.getScalarType();
SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT); SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero); SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands); SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
@ -919,7 +917,7 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
SDValue AllOnes = DAG.getConstant( SDValue AllOnes = DAG.getConstant(
APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT); APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
@ -942,16 +940,16 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"); "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
unsigned BW = SVT.getSizeInBits(); unsigned BW = SVT.getSizeInBits();
SDValue HalfWord = DAG.getConstant(BW/2, DL, VT); SDValue HalfWord = DAG.getConstant(BW/2, VT);
// Constants to clear the upper part of the word. // Constants to clear the upper part of the word.
// Notice that we can also use SHL+SHR, but using a constant is slightly // Notice that we can also use SHL+SHR, but using a constant is slightly
// faster on x86. // faster on x86.
uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF; uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT); SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
// Two to the power of half-word-size. // Two to the power of half-word-size.
SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType()); SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
// Clear upper part of LO, lower HI // Clear upper part of LO, lower HI
SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
@ -970,9 +968,8 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
SDLoc DL(Op); SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType()); return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
Zero, Op.getOperand(0)); Zero, Op.getOperand(0));
} }
return DAG.UnrollVectorOp(Op.getNode()); return DAG.UnrollVectorOp(Op.getNode());
@ -988,16 +985,16 @@ SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
SmallVector<SDValue, 8> Ops(NumElems); SmallVector<SDValue, 8> Ops(NumElems);
for (unsigned i = 0; i < NumElems; ++i) { for (unsigned i = 0; i < NumElems; ++i) {
SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
DAG.getConstant(i, dl, TLI.getVectorIdxTy())); DAG.getConstant(i, TLI.getVectorIdxTy()));
SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
DAG.getConstant(i, dl, TLI.getVectorIdxTy())); DAG.getConstant(i, TLI.getVectorIdxTy()));
Ops[i] = DAG.getNode(ISD::SETCC, dl, Ops[i] = DAG.getNode(ISD::SETCC, dl,
TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT), TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
LHSElem, RHSElem, CC); LHSElem, RHSElem, CC);
Ops[i] = DAG.getSelect(dl, EltVT, Ops[i], Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
DAG.getConstant(APInt::getAllOnesValue DAG.getConstant(APInt::getAllOnesValue
(EltVT.getSizeInBits()), dl, EltVT), (EltVT.getSizeInBits()), EltVT),
DAG.getConstant(0, dl, EltVT)); DAG.getConstant(0, EltVT));
} }
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
} }

123
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -252,7 +252,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
} else { } else {
EVT VT = OpVT.getVectorElementType(); EVT VT = OpVT.getVectorElementType();
Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
} }
return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
} }
@ -308,7 +308,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent); VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
// Vector read from all ones, scalar expects a single 1 so mask. // Vector read from all ones, scalar expects a single 1 so mask.
Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT, Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
Cond, DAG.getConstant(1, SDLoc(N), CondVT)); Cond, DAG.getConstant(1, CondVT));
break; break;
case TargetLowering::ZeroOrNegativeOneBooleanContent: case TargetLowering::ZeroOrNegativeOneBooleanContent:
assert(VecBool == TargetLowering::UndefinedBooleanContent || assert(VecBool == TargetLowering::UndefinedBooleanContent ||
@ -385,9 +385,9 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
} else { } else {
EVT VT = OpVT.getVectorElementType(); EVT VT = OpVT.getVectorElementType();
LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
} }
// Turn it into a scalar SETCC. // Turn it into a scalar SETCC.
@ -811,7 +811,7 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl, DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
} }
@ -845,7 +845,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
StackPtr = StackPtr =
DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getConstant(IncrementSize, dl, StackPtr.getValueType())); DAG.getConstant(IncrementSize, StackPtr.getValueType()));
// Load the Hi part from the stack slot. // Load the Hi part from the stack slot.
Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
@ -892,7 +892,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
Lo.getValueType(), Lo, Elt, Idx); Lo.getValueType(), Lo, Elt, Idx);
else else
Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
DAG.getConstant(IdxVal - LoNumElts, dl, DAG.getConstant(IdxVal - LoNumElts,
TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
return; return;
} }
@ -924,8 +924,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
// Increment the pointer to the other part. // Increment the pointer to the other part.
unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getConstant(IncrementSize, dl, DAG.getConstant(IncrementSize, StackPtr.getValueType()));
StackPtr.getValueType()));
// Load the Hi part from the stack slot. // Load the Hi part from the stack slot.
Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
@ -968,7 +967,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
unsigned IncrementSize = LoMemVT.getSizeInBits()/8; unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment, HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
@ -1023,7 +1022,7 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
unsigned IncrementSize = LoMemVT.getSizeInBits()/8; unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, dl, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
MMO = DAG.getMachineFunction(). MMO = DAG.getMachineFunction().
getMachineMemOperand(MLD->getPointerInfo(), getMachineMemOperand(MLD->getPointerInfo(),
@ -1238,9 +1237,8 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
// Extract the vector element by hand. // Extract the vector element by hand.
SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
Inputs[Input], Inputs[Input], DAG.getConstant(Idx,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())));
TLI.getVectorIdxTy())));
} }
// Construct the Lo/Hi output using a BUILD_VECTOR. // Construct the Lo/Hi output using a BUILD_VECTOR.
@ -1435,8 +1433,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
} else { } else {
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
DAG.getConstant(IdxVal - LoElts, dl, DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
Idx.getValueType()));
} }
} }
@ -1457,7 +1454,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
if (IdxVal < LoElts) if (IdxVal < LoElts)
return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
return SDValue(DAG.UpdateNodeOperands(N, Hi, return SDValue(DAG.UpdateNodeOperands(N, Hi,
DAG.getConstant(IdxVal - LoElts, SDLoc(N), DAG.getConstant(IdxVal - LoElts,
Idx.getValueType())), 0); Idx.getValueType())), 0);
} }
@ -1513,7 +1510,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
unsigned IncrementSize = LoMemVT.getSizeInBits()/8; unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, DL, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
MMO = DAG.getMachineFunction(). MMO = DAG.getMachineFunction().
getMachineMemOperand(N->getPointerInfo(), getMachineMemOperand(N->getPointerInfo(),
@ -1560,7 +1557,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Increment the pointer to the other half. // Increment the pointer to the other half.
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, DL, Ptr.getValueType())); DAG.getConstant(IncrementSize, Ptr.getValueType()));
if (isTruncating) if (isTruncating)
Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
@ -1589,7 +1586,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
i != e; ++i) { i != e; ++i) {
Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
Op, DAG.getConstant(i, DL, TLI.getVectorIdxTy()))); Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
} }
} }
@ -1656,7 +1653,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
// restricted set of legal types, this split can chain to build things up. // restricted set of legal types, this split can chain to build things up.
return IsFloat ? return IsFloat ?
DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
DAG.getTargetConstant(0, DL, TLI.getPointerTy())) : DAG.getTargetConstant(0, TLI.getPointerTy())) :
DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec); DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
} }
@ -1888,11 +1885,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
while (CurNumElts != 0) { while (CurNumElts != 0) {
while (CurNumElts >= NumElts) { while (CurNumElts >= NumElts) {
SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
DAG.getConstant(Idx, dl, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
TLI.getVectorIdxTy()));
SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
DAG.getConstant(Idx, dl, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
TLI.getVectorIdxTy()));
ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
Idx += NumElts; Idx += NumElts;
CurNumElts -= NumElts; CurNumElts -= NumElts;
@ -1905,13 +1900,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
if (NumElts == 1) { if (NumElts == 1) {
for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
InOp1, InOp1, DAG.getConstant(Idx,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
TLI.getVectorIdxTy()));
SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
InOp2, InOp2, DAG.getConstant(Idx,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
TLI.getVectorIdxTy()));
ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
EOp1, EOp2); EOp1, EOp2);
} }
@ -1949,8 +1942,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
unsigned NumToInsert = ConcatEnd - Idx - 1; unsigned NumToInsert = ConcatEnd - Idx - 1;
for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
ConcatOps[OpIdx], ConcatOps[OpIdx], DAG.getConstant(i,
DAG.getConstant(i, dl, TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
} }
ConcatOps[Idx+1] = VecOp; ConcatOps[Idx+1] = VecOp;
ConcatEnd = Idx + 2; ConcatEnd = Idx + 2;
@ -2036,8 +2029,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
} }
if (InVTNumElts % WidenNumElts == 0) { if (InVTNumElts % WidenNumElts == 0) {
SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp, SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); InOp, DAG.getConstant(0,
TLI.getVectorIdxTy()));
// Extract the input and convert the shorten input vector. // Extract the input and convert the shorten input vector.
if (N->getNumOperands() == 1) if (N->getNumOperands() == 1)
return DAG.getNode(Opcode, DL, WidenVT, InVal); return DAG.getNode(Opcode, DL, WidenVT, InVal);
@ -2052,7 +2046,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
unsigned i; unsigned i;
for (i=0; i < MinElts; ++i) { for (i=0; i < MinElts; ++i) {
SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
DAG.getConstant(i, DL, TLI.getVectorIdxTy())); DAG.getConstant(i, TLI.getVectorIdxTy()));
if (N->getNumOperands() == 1) if (N->getNumOperands() == 1)
Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
else else
@ -2279,7 +2273,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
InOp = GetWidenedVector(InOp); InOp = GetWidenedVector(InOp);
for (unsigned j=0; j < NumInElts; ++j) for (unsigned j=0; j < NumInElts; ++j)
Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getConstant(j, dl, TLI.getVectorIdxTy())); DAG.getConstant(j, TLI.getVectorIdxTy()));
} }
SDValue UndefVal = DAG.getUNDEF(EltVT); SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; Idx < WidenNumElts; ++Idx) for (; Idx < WidenNumElts; ++Idx)
@ -2337,7 +2331,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
if (InVTNumElts % WidenNumElts == 0) { if (InVTNumElts % WidenNumElts == 0) {
// Extract the input and convert the shorten input vector. // Extract the input and convert the shorten input vector.
InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
SatOp, CvtCode); SatOp, CvtCode);
} }
@ -2353,7 +2347,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
unsigned i; unsigned i;
for (i=0; i < MinElts; ++i) { for (i=0; i < MinElts; ++i) {
SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
DAG.getConstant(i, dl, TLI.getVectorIdxTy())); DAG.getConstant(i, TLI.getVectorIdxTy()));
Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
SatOp, CvtCode); SatOp, CvtCode);
} }
@ -2396,7 +2390,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
unsigned i; unsigned i;
for (i=0; i < NumElts; ++i) for (i=0; i < NumElts; ++i)
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getConstant(IdxVal + i, dl, TLI.getVectorIdxTy())); DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
SDValue UndefVal = DAG.getUNDEF(EltVT); SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; i < WidenNumElts; ++i) for (; i < WidenNumElts; ++i)
@ -2459,7 +2453,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
unsigned NumConcat = WidenNumElts / MaskNumElts; unsigned NumConcat = WidenNumElts / MaskNumElts;
SmallVector<SDValue, 16> Ops(NumConcat); SmallVector<SDValue, 16> Ops(NumConcat);
SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT); SDValue ZeroVal = DAG.getConstant(0, MaskVT);
Ops[0] = Mask; Ops[0] = Mask;
for (unsigned i = 1; i != NumConcat; ++i) for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = ZeroVal; Ops[i] = ZeroVal;
@ -2699,10 +2693,10 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements()) if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT, InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
DAG.getUNDEF(FixedVT), InOp, DAG.getUNDEF(FixedVT), InOp,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
else else
InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp, InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
DAG.getConstant(0, DL, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
break; break;
} }
} }
@ -2747,8 +2741,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
for (unsigned i=0; i < NumElts; ++i) for (unsigned i=0; i < NumElts; ++i)
Ops[i] = DAG.getNode(Opcode, dl, EltVT, Ops[i] = DAG.getNode(Opcode, dl, EltVT,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
DAG.getConstant(i, dl, DAG.getConstant(i, TLI.getVectorIdxTy())));
TLI.getVectorIdxTy())));
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
} }
@ -2769,7 +2762,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
if (TLI.isTypeLegal(NewVT)) { if (TLI.isTypeLegal(NewVT)) {
SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
} }
} }
@ -2797,7 +2790,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
InOp = GetWidenedVector(InOp); InOp = GetWidenedVector(InOp);
for (unsigned j=0; j < NumInElts; ++j) for (unsigned j=0; j < NumInElts; ++j)
Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getConstant(j, dl, TLI.getVectorIdxTy())); DAG.getConstant(j, TLI.getVectorIdxTy()));
} }
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
} }
@ -2852,7 +2845,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
unsigned NumConcat = WidenNumElts / MaskNumElts; unsigned NumConcat = WidenNumElts / MaskNumElts;
SmallVector<SDValue, 16> Ops(NumConcat); SmallVector<SDValue, 16> Ops(NumConcat);
SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT); SDValue ZeroVal = DAG.getConstant(0, MaskVT);
Ops[0] = Mask; Ops[0] = Mask;
for (unsigned i = 1; i != NumConcat; ++i) for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = ZeroVal; Ops[i] = ZeroVal;
@ -2887,8 +2880,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
SVT.getVectorElementType(), SVT.getVectorElementType(),
N->getValueType(0).getVectorNumElements()); N->getValueType(0).getVectorNumElements());
SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
ResVT, WideSETCC, ResVT, WideSETCC, DAG.getConstant(0,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); TLI.getVectorIdxTy()));
return PromoteTargetBoolean(CC, N->getValueType(0)); return PromoteTargetBoolean(CC, N->getValueType(0));
} }
@ -2982,7 +2975,7 @@ static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
LdTy = NewLdTy; LdTy = NewLdTy;
} }
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy())); DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
} }
return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
} }
@ -3053,7 +3046,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
unsigned Increment = NewVTWidth / 8; unsigned Increment = NewVTWidth / 8;
Offset += Increment; Offset += Increment;
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getConstant(Increment, dl, BasePtr.getValueType())); DAG.getConstant(Increment, BasePtr.getValueType()));
SDValue L; SDValue L;
if (LdWidth < NewVTWidth) { if (LdWidth < NewVTWidth) {
@ -3179,7 +3172,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
for (i=1; i < NumElts; ++i, Offset += Increment) { for (i=1; i < NumElts; ++i, Offset += Increment) {
SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
BasePtr, BasePtr,
DAG.getConstant(Offset, dl, DAG.getConstant(Offset,
BasePtr.getValueType())); BasePtr.getValueType()));
Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
LD->getPointerInfo().getWithOffset(Offset), LdEltVT, LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
@ -3230,8 +3223,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
unsigned NumVTElts = NewVT.getVectorNumElements(); unsigned NumVTElts = NewVT.getVectorNumElements();
do { do {
SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
DAG.getConstant(Idx, dl, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
TLI.getVectorIdxTy()));
StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
ST->getPointerInfo().getWithOffset(Offset), ST->getPointerInfo().getWithOffset(Offset),
isVolatile, isNonTemporal, isVolatile, isNonTemporal,
@ -3240,8 +3232,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
Offset += Increment; Offset += Increment;
Idx += NumVTElts; Idx += NumVTElts;
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getConstant(Increment, dl, DAG.getConstant(Increment, BasePtr.getValueType()));
BasePtr.getValueType()));
} while (StWidth != 0 && StWidth >= NewVTWidth); } while (StWidth != 0 && StWidth >= NewVTWidth);
} else { } else {
// Cast the vector to the scalar type we can store // Cast the vector to the scalar type we can store
@ -3252,7 +3243,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
Idx = Idx * ValEltWidth / NewVTWidth; Idx = Idx * ValEltWidth / NewVTWidth;
do { do {
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy())); DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
ST->getPointerInfo().getWithOffset(Offset), ST->getPointerInfo().getWithOffset(Offset),
isVolatile, isNonTemporal, isVolatile, isNonTemporal,
@ -3260,8 +3251,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
StWidth -= NewVTWidth; StWidth -= NewVTWidth;
Offset += Increment; Offset += Increment;
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getConstant(Increment, dl, DAG.getConstant(Increment, BasePtr.getValueType()));
BasePtr.getValueType()));
} while (StWidth != 0 && StWidth >= NewVTWidth); } while (StWidth != 0 && StWidth >= NewVTWidth);
// Restore index back to be relative to the original widen element type // Restore index back to be relative to the original widen element type
Idx = Idx * NewVTWidth / ValEltWidth; Idx = Idx * NewVTWidth / ValEltWidth;
@ -3299,7 +3289,7 @@ DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
unsigned Increment = ValEltVT.getSizeInBits() / 8; unsigned Increment = ValEltVT.getSizeInBits() / 8;
unsigned NumElts = StVT.getVectorNumElements(); unsigned NumElts = StVT.getVectorNumElements();
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
ST->getPointerInfo(), StEltVT, ST->getPointerInfo(), StEltVT,
isVolatile, isNonTemporal, Align, isVolatile, isNonTemporal, Align,
@ -3307,11 +3297,10 @@ DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
unsigned Offset = Increment; unsigned Offset = Increment;
for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
BasePtr, BasePtr, DAG.getConstant(Offset,
DAG.getConstant(Offset, dl, BasePtr.getValueType()));
BasePtr.getValueType()));
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
ST->getPointerInfo().getWithOffset(Offset), ST->getPointerInfo().getWithOffset(Offset),
StEltVT, isVolatile, isNonTemporal, StEltVT, isVolatile, isNonTemporal,
@ -3348,7 +3337,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
DAG.getConstant(0, dl, TLI.getVectorIdxTy())); DAG.getConstant(0, TLI.getVectorIdxTy()));
// Fall back to extract and build. // Fall back to extract and build.
SmallVector<SDValue, 16> Ops(WidenNumElts); SmallVector<SDValue, 16> Ops(WidenNumElts);
@ -3357,7 +3346,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
unsigned Idx; unsigned Idx;
for (Idx = 0; Idx < MinNumElts; ++Idx) for (Idx = 0; Idx < MinNumElts; ++Idx)
Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())); DAG.getConstant(Idx, TLI.getVectorIdxTy()));
SDValue UndefVal = DAG.getUNDEF(EltVT); SDValue UndefVal = DAG.getUNDEF(EltVT);
for ( ; Idx < WidenNumElts; ++Idx) for ( ; Idx < WidenNumElts; ++Idx)

246
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1030,7 +1030,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) {
APInt Imm = APInt::getLowBitsSet(BitWidth, APInt Imm = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits()); VT.getSizeInBits());
return getNode(ISD::AND, DL, Op.getValueType(), Op, return getNode(ISD::AND, DL, Op.getValueType(), Op,
getConstant(Imm, DL, Op.getValueType())); getConstant(Imm, Op.getValueType()));
} }
SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
@ -1068,7 +1068,7 @@ SDValue SelectionDAG::getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
SDValue SelectionDAG::getNOT(SDLoc DL, SDValue Val, EVT VT) { SDValue SelectionDAG::getNOT(SDLoc DL, SDValue Val, EVT VT) {
EVT EltVT = VT.getScalarType(); EVT EltVT = VT.getScalarType();
SDValue NegOne = SDValue NegOne =
getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, VT); getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
return getNode(ISD::XOR, DL, VT, Val, NegOne); return getNode(ISD::XOR, DL, VT, Val, NegOne);
} }
@ -1078,33 +1078,31 @@ SDValue SelectionDAG::getLogicalNOT(SDLoc DL, SDValue Val, EVT VT) {
switch (TLI->getBooleanContents(VT)) { switch (TLI->getBooleanContents(VT)) {
case TargetLowering::ZeroOrOneBooleanContent: case TargetLowering::ZeroOrOneBooleanContent:
case TargetLowering::UndefinedBooleanContent: case TargetLowering::UndefinedBooleanContent:
TrueValue = getConstant(1, DL, VT); TrueValue = getConstant(1, VT);
break; break;
case TargetLowering::ZeroOrNegativeOneBooleanContent: case TargetLowering::ZeroOrNegativeOneBooleanContent:
TrueValue = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, TrueValue = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()),
VT); VT);
break; break;
} }
return getNode(ISD::XOR, DL, VT, Val, TrueValue); return getNode(ISD::XOR, DL, VT, Val, TrueValue);
} }
SDValue SelectionDAG::getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isT, SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT, bool isO) {
bool isO) {
EVT EltVT = VT.getScalarType(); EVT EltVT = VT.getScalarType();
assert((EltVT.getSizeInBits() >= 64 || assert((EltVT.getSizeInBits() >= 64 ||
(uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
"getConstant with a uint64_t value that doesn't fit in the type!"); "getConstant with a uint64_t value that doesn't fit in the type!");
return getConstant(APInt(EltVT.getSizeInBits(), Val), DL, VT, isT, isO); return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT, isO);
} }
SDValue SelectionDAG::getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isT, SDValue SelectionDAG::getConstant(const APInt &Val, EVT VT, bool isT, bool isO)
bool isO)
{ {
return getConstant(*ConstantInt::get(*Context, Val), DL, VT, isT, isO); return getConstant(*ConstantInt::get(*Context, Val), VT, isT, isO);
} }
SDValue SelectionDAG::getConstant(const ConstantInt &Val, SDLoc DL, EVT VT, SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT,
bool isT, bool isO) { bool isO) {
assert(VT.isInteger() && "Cannot create FP integer constant!"); assert(VT.isInteger() && "Cannot create FP integer constant!");
EVT EltVT = VT.getScalarType(); EVT EltVT = VT.getScalarType();
@ -1143,7 +1141,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
SmallVector<SDValue, 2> EltParts; SmallVector<SDValue, 2> EltParts;
for (unsigned i = 0; i < ViaVecNumElts / VT.getVectorNumElements(); ++i) { for (unsigned i = 0; i < ViaVecNumElts / VT.getVectorNumElements(); ++i) {
EltParts.push_back(getConstant(NewVal.lshr(i * ViaEltSizeInBits) EltParts.push_back(getConstant(NewVal.lshr(i * ViaEltSizeInBits)
.trunc(ViaEltSizeInBits), DL, .trunc(ViaEltSizeInBits),
ViaEltVT, isT, isO)); ViaEltVT, isT, isO));
} }
@ -1183,8 +1181,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
return SDValue(N, 0); return SDValue(N, 0);
if (!N) { if (!N) {
N = new (NodeAllocator) ConstantSDNode(isT, isO, Elt, DL.getDebugLoc(), N = new (NodeAllocator) ConstantSDNode(isT, isO, Elt, EltVT);
EltVT);
CSEMap.InsertNode(N, IP); CSEMap.InsertNode(N, IP);
InsertNode(N); InsertNode(N);
} }
@ -1198,17 +1195,16 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
return Result; return Result;
} }
SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget) { SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
return getConstant(Val, DL, TLI->getPointerTy(), isTarget); return getConstant(Val, TLI->getPointerTy(), isTarget);
} }
SDValue SelectionDAG::getConstantFP(const APFloat& V, SDLoc DL, EVT VT,
bool isTarget) { SDValue SelectionDAG::getConstantFP(const APFloat& V, EVT VT, bool isTarget) {
return getConstantFP(*ConstantFP::get(*getContext(), V), DL, VT, isTarget); return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget);
} }
SDValue SelectionDAG::getConstantFP(const ConstantFP& V, SDLoc DL, EVT VT, SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
bool isTarget){
assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
EVT EltVT = VT.getScalarType(); EVT EltVT = VT.getScalarType();
@ -1236,25 +1232,25 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP& V, SDLoc DL, EVT VT,
if (VT.isVector()) { if (VT.isVector()) {
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
Ops.assign(VT.getVectorNumElements(), Result); Ops.assign(VT.getVectorNumElements(), Result);
// FIXME SDLoc info might be appropriate here
Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops); Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops);
} }
return Result; return Result;
} }
SDValue SelectionDAG::getConstantFP(double Val, SDLoc DL, EVT VT, SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
bool isTarget) {
EVT EltVT = VT.getScalarType(); EVT EltVT = VT.getScalarType();
if (EltVT==MVT::f32) if (EltVT==MVT::f32)
return getConstantFP(APFloat((float)Val), DL, VT, isTarget); return getConstantFP(APFloat((float)Val), VT, isTarget);
else if (EltVT==MVT::f64) else if (EltVT==MVT::f64)
return getConstantFP(APFloat(Val), DL, VT, isTarget); return getConstantFP(APFloat(Val), VT, isTarget);
else if (EltVT==MVT::f80 || EltVT==MVT::f128 || EltVT==MVT::ppcf128 || else if (EltVT==MVT::f80 || EltVT==MVT::f128 || EltVT==MVT::ppcf128 ||
EltVT==MVT::f16) { EltVT==MVT::f16) {
bool ignored; bool ignored;
APFloat apf = APFloat(Val); APFloat apf = APFloat(Val);
apf.convert(EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven, apf.convert(EVTToAPFloatSemantics(EltVT), APFloat::rmNearestTiesToEven,
&ignored); &ignored);
return getConstantFP(apf, DL, VT, isTarget); return getConstantFP(apf, VT, isTarget);
} else } else
llvm_unreachable("Unsupported type in getConstantFP"); llvm_unreachable("Unsupported type in getConstantFP");
} }
@ -1840,14 +1836,13 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
switch (Cond) { switch (Cond) {
default: break; default: break;
case ISD::SETFALSE: case ISD::SETFALSE:
case ISD::SETFALSE2: return getConstant(0, dl, VT); case ISD::SETFALSE2: return getConstant(0, VT);
case ISD::SETTRUE: case ISD::SETTRUE:
case ISD::SETTRUE2: { case ISD::SETTRUE2: {
TargetLowering::BooleanContent Cnt = TargetLowering::BooleanContent Cnt =
TLI->getBooleanContents(N1->getValueType(0)); TLI->getBooleanContents(N1->getValueType(0));
return getConstant( return getConstant(
Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl, Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
VT);
} }
case ISD::SETOEQ: case ISD::SETOEQ:
@ -1871,16 +1866,16 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
switch (Cond) { switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!"); default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: return getConstant(C1 == C2, dl, VT); case ISD::SETEQ: return getConstant(C1 == C2, VT);
case ISD::SETNE: return getConstant(C1 != C2, dl, VT); case ISD::SETNE: return getConstant(C1 != C2, VT);
case ISD::SETULT: return getConstant(C1.ult(C2), dl, VT); case ISD::SETULT: return getConstant(C1.ult(C2), VT);
case ISD::SETUGT: return getConstant(C1.ugt(C2), dl, VT); case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
case ISD::SETULE: return getConstant(C1.ule(C2), dl, VT); case ISD::SETULE: return getConstant(C1.ule(C2), VT);
case ISD::SETUGE: return getConstant(C1.uge(C2), dl, VT); case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
case ISD::SETLT: return getConstant(C1.slt(C2), dl, VT); case ISD::SETLT: return getConstant(C1.slt(C2), VT);
case ISD::SETGT: return getConstant(C1.sgt(C2), dl, VT); case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
case ISD::SETLE: return getConstant(C1.sle(C2), dl, VT); case ISD::SETLE: return getConstant(C1.sle(C2), VT);
case ISD::SETGE: return getConstant(C1.sge(C2), dl, VT); case ISD::SETGE: return getConstant(C1.sge(C2), VT);
} }
} }
} }
@ -1892,41 +1887,41 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
case ISD::SETEQ: if (R==APFloat::cmpUnordered) case ISD::SETEQ: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, dl, VT); case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
case ISD::SETNE: if (R==APFloat::cmpUnordered) case ISD::SETNE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpLessThan, dl, VT); R==APFloat::cmpLessThan, VT);
case ISD::SETLT: if (R==APFloat::cmpUnordered) case ISD::SETLT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, dl, VT); case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
case ISD::SETGT: if (R==APFloat::cmpUnordered) case ISD::SETGT: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, dl, VT); case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
case ISD::SETLE: if (R==APFloat::cmpUnordered) case ISD::SETLE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
R==APFloat::cmpEqual, dl, VT); R==APFloat::cmpEqual, VT);
case ISD::SETGE: if (R==APFloat::cmpUnordered) case ISD::SETGE: if (R==APFloat::cmpUnordered)
return getUNDEF(VT); return getUNDEF(VT);
// fall through // fall through
case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpEqual, dl, VT); R==APFloat::cmpEqual, VT);
case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, dl, VT); case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, dl, VT); case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
R==APFloat::cmpEqual, dl, VT); R==APFloat::cmpEqual, VT);
case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, dl, VT); case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
R==APFloat::cmpLessThan, dl, VT); R==APFloat::cmpLessThan, VT);
case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpUnordered, dl, VT); R==APFloat::cmpUnordered, VT);
case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, dl, VT); case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, dl, VT); case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
} }
} else { } else {
// Ensure that the constant occurs on the RHS. // Ensure that the constant occurs on the RHS.
@ -2746,12 +2741,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
switch (Opcode) { switch (Opcode) {
default: break; default: break;
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT, return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), VT,
C->isTargetOpcode(), C->isOpaque()); C->isTargetOpcode(), C->isOpaque());
case ISD::ANY_EXTEND: case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
case ISD::TRUNCATE: case ISD::TRUNCATE:
return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT, return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), VT,
C->isTargetOpcode(), C->isOpaque()); C->isTargetOpcode(), C->isOpaque());
case ISD::UINT_TO_FP: case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP: { case ISD::SINT_TO_FP: {
@ -2760,29 +2755,29 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
(void)apf.convertFromAPInt(Val, (void)apf.convertFromAPInt(Val,
Opcode==ISD::SINT_TO_FP, Opcode==ISD::SINT_TO_FP,
APFloat::rmNearestTiesToEven); APFloat::rmNearestTiesToEven);
return getConstantFP(apf, DL, VT); return getConstantFP(apf, VT);
} }
case ISD::BITCAST: case ISD::BITCAST:
if (VT == MVT::f16 && C->getValueType(0) == MVT::i16) if (VT == MVT::f16 && C->getValueType(0) == MVT::i16)
return getConstantFP(APFloat(APFloat::IEEEhalf, Val), DL, VT); return getConstantFP(APFloat(APFloat::IEEEhalf, Val), VT);
if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
return getConstantFP(APFloat(APFloat::IEEEsingle, Val), DL, VT); return getConstantFP(APFloat(APFloat::IEEEsingle, Val), VT);
else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
return getConstantFP(APFloat(APFloat::IEEEdouble, Val), DL, VT); return getConstantFP(APFloat(APFloat::IEEEdouble, Val), VT);
break; break;
case ISD::BSWAP: case ISD::BSWAP:
return getConstant(Val.byteSwap(), DL, VT, C->isTargetOpcode(), return getConstant(Val.byteSwap(), VT, C->isTargetOpcode(),
C->isOpaque()); C->isOpaque());
case ISD::CTPOP: case ISD::CTPOP:
return getConstant(Val.countPopulation(), DL, VT, C->isTargetOpcode(), return getConstant(Val.countPopulation(), VT, C->isTargetOpcode(),
C->isOpaque()); C->isOpaque());
case ISD::CTLZ: case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF: case ISD::CTLZ_ZERO_UNDEF:
return getConstant(Val.countLeadingZeros(), DL, VT, C->isTargetOpcode(), return getConstant(Val.countLeadingZeros(), VT, C->isTargetOpcode(),
C->isOpaque()); C->isOpaque());
case ISD::CTTZ: case ISD::CTTZ:
case ISD::CTTZ_ZERO_UNDEF: case ISD::CTTZ_ZERO_UNDEF:
return getConstant(Val.countTrailingZeros(), DL, VT, C->isTargetOpcode(), return getConstant(Val.countTrailingZeros(), VT, C->isTargetOpcode(),
C->isOpaque()); C->isOpaque());
} }
} }
@ -2793,26 +2788,26 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
switch (Opcode) { switch (Opcode) {
case ISD::FNEG: case ISD::FNEG:
V.changeSign(); V.changeSign();
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
case ISD::FABS: case ISD::FABS:
V.clearSign(); V.clearSign();
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
case ISD::FCEIL: { case ISD::FCEIL: {
APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardPositive); APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardPositive);
if (fs == APFloat::opOK || fs == APFloat::opInexact) if (fs == APFloat::opOK || fs == APFloat::opInexact)
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
break; break;
} }
case ISD::FTRUNC: { case ISD::FTRUNC: {
APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardZero); APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardZero);
if (fs == APFloat::opOK || fs == APFloat::opInexact) if (fs == APFloat::opOK || fs == APFloat::opInexact)
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
break; break;
} }
case ISD::FFLOOR: { case ISD::FFLOOR: {
APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardNegative); APFloat::opStatus fs = V.roundToIntegral(APFloat::rmTowardNegative);
if (fs == APFloat::opOK || fs == APFloat::opInexact) if (fs == APFloat::opOK || fs == APFloat::opInexact)
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
break; break;
} }
case ISD::FP_EXTEND: { case ISD::FP_EXTEND: {
@ -2821,7 +2816,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
// FIXME need to be more flexible about rounding mode. // FIXME need to be more flexible about rounding mode.
(void)V.convert(EVTToAPFloatSemantics(VT), (void)V.convert(EVTToAPFloatSemantics(VT),
APFloat::rmNearestTiesToEven, &ignored); APFloat::rmNearestTiesToEven, &ignored);
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
} }
case ISD::FP_TO_SINT: case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: { case ISD::FP_TO_UINT: {
@ -2835,15 +2830,15 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual
break; break;
APInt api(VT.getSizeInBits(), x); APInt api(VT.getSizeInBits(), x);
return getConstant(api, DL, VT); return getConstant(api, VT);
} }
case ISD::BITCAST: case ISD::BITCAST:
if (VT == MVT::i16 && C->getValueType(0) == MVT::f16) if (VT == MVT::i16 && C->getValueType(0) == MVT::f16)
return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), DL, VT); return getConstant((uint16_t)V.bitcastToAPInt().getZExtValue(), VT);
else if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) else if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), DL, VT); return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
return getConstant(V.bitcastToAPInt().getZExtValue(), DL, VT); return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
break; break;
} }
} }
@ -2919,7 +2914,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
else if (OpOpcode == ISD::UNDEF) else if (OpOpcode == ISD::UNDEF)
// sext(undef) = 0, because the top bits will all be the same. // sext(undef) = 0, because the top bits will all be the same.
return getConstant(0, DL, VT); return getConstant(0, VT);
break; break;
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
assert(VT.isInteger() && Operand.getValueType().isInteger() && assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@ -2936,7 +2931,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
Operand.getNode()->getOperand(0)); Operand.getNode()->getOperand(0));
else if (OpOpcode == ISD::UNDEF) else if (OpOpcode == ISD::UNDEF)
// zext(undef) = 0, because the top bits will be zero. // zext(undef) = 0, because the top bits will be zero.
return getConstant(0, DL, VT); return getConstant(0, VT);
break; break;
case ISD::ANY_EXTEND: case ISD::ANY_EXTEND:
assert(VT.isInteger() && Operand.getValueType().isInteger() && assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@ -3050,7 +3045,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
return SDValue(N, 0); return SDValue(N, 0);
} }
SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT, SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, EVT VT,
SDNode *Cst1, SDNode *Cst2) { SDNode *Cst1, SDNode *Cst2) {
// If the opcode is a target-specific ISD node, there's nothing we can // If the opcode is a target-specific ISD node, there's nothing we can
// do here and the operand rules may not line up with the below, so // do here and the operand rules may not line up with the below, so
@ -3105,57 +3100,57 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
switch (Opcode) { switch (Opcode) {
case ISD::ADD: case ISD::ADD:
Outputs.push_back(getConstant(C1 + C2, DL, SVT)); Outputs.push_back(getConstant(C1 + C2, SVT));
break; break;
case ISD::SUB: case ISD::SUB:
Outputs.push_back(getConstant(C1 - C2, DL, SVT)); Outputs.push_back(getConstant(C1 - C2, SVT));
break; break;
case ISD::MUL: case ISD::MUL:
Outputs.push_back(getConstant(C1 * C2, DL, SVT)); Outputs.push_back(getConstant(C1 * C2, SVT));
break; break;
case ISD::UDIV: case ISD::UDIV:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
return SDValue(); return SDValue();
Outputs.push_back(getConstant(C1.udiv(C2), DL, SVT)); Outputs.push_back(getConstant(C1.udiv(C2), SVT));
break; break;
case ISD::UREM: case ISD::UREM:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
return SDValue(); return SDValue();
Outputs.push_back(getConstant(C1.urem(C2), DL, SVT)); Outputs.push_back(getConstant(C1.urem(C2), SVT));
break; break;
case ISD::SDIV: case ISD::SDIV:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
return SDValue(); return SDValue();
Outputs.push_back(getConstant(C1.sdiv(C2), DL, SVT)); Outputs.push_back(getConstant(C1.sdiv(C2), SVT));
break; break;
case ISD::SREM: case ISD::SREM:
if (!C2.getBoolValue()) if (!C2.getBoolValue())
return SDValue(); return SDValue();
Outputs.push_back(getConstant(C1.srem(C2), DL, SVT)); Outputs.push_back(getConstant(C1.srem(C2), SVT));
break; break;
case ISD::AND: case ISD::AND:
Outputs.push_back(getConstant(C1 & C2, DL, SVT)); Outputs.push_back(getConstant(C1 & C2, SVT));
break; break;
case ISD::OR: case ISD::OR:
Outputs.push_back(getConstant(C1 | C2, DL, SVT)); Outputs.push_back(getConstant(C1 | C2, SVT));
break; break;
case ISD::XOR: case ISD::XOR:
Outputs.push_back(getConstant(C1 ^ C2, DL, SVT)); Outputs.push_back(getConstant(C1 ^ C2, SVT));
break; break;
case ISD::SHL: case ISD::SHL:
Outputs.push_back(getConstant(C1 << C2, DL, SVT)); Outputs.push_back(getConstant(C1 << C2, SVT));
break; break;
case ISD::SRL: case ISD::SRL:
Outputs.push_back(getConstant(C1.lshr(C2), DL, SVT)); Outputs.push_back(getConstant(C1.lshr(C2), SVT));
break; break;
case ISD::SRA: case ISD::SRA:
Outputs.push_back(getConstant(C1.ashr(C2), DL, SVT)); Outputs.push_back(getConstant(C1.ashr(C2), SVT));
break; break;
case ISD::ROTL: case ISD::ROTL:
Outputs.push_back(getConstant(C1.rotl(C2), DL, SVT)); Outputs.push_back(getConstant(C1.rotl(C2), SVT));
break; break;
case ISD::ROTR: case ISD::ROTR:
Outputs.push_back(getConstant(C1.rotr(C2), DL, SVT)); Outputs.push_back(getConstant(C1.rotr(C2), SVT));
break; break;
default: default:
return SDValue(); return SDValue();
@ -3384,7 +3379,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
unsigned FromBits = EVT.getScalarType().getSizeInBits(); unsigned FromBits = EVT.getScalarType().getSizeInBits();
Val <<= Val.getBitWidth()-FromBits; Val <<= Val.getBitWidth()-FromBits;
Val = Val.ashr(Val.getBitWidth()-FromBits); Val = Val.ashr(Val.getBitWidth()-FromBits);
return getConstant(Val, DL, VT); return getConstant(Val, VT);
} }
break; break;
} }
@ -3402,7 +3397,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
N1.getOperand(0).getValueType().getVectorNumElements(); N1.getOperand(0).getValueType().getVectorNumElements();
return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
N1.getOperand(N2C->getZExtValue() / Factor), N1.getOperand(N2C->getZExtValue() / Factor),
getConstant(N2C->getZExtValue() % Factor, DL, getConstant(N2C->getZExtValue() % Factor,
N2.getValueType())); N2.getValueType()));
} }
@ -3459,7 +3454,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
unsigned ElementSize = VT.getSizeInBits(); unsigned ElementSize = VT.getSizeInBits();
unsigned Shift = ElementSize * N2C->getZExtValue(); unsigned Shift = ElementSize * N2C->getZExtValue();
APInt ShiftedVal = C->getAPIntValue().lshr(Shift); APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
return getConstant(ShiftedVal.trunc(ElementSize), DL, VT); return getConstant(ShiftedVal.trunc(ElementSize), VT);
} }
break; break;
case ISD::EXTRACT_SUBVECTOR: { case ISD::EXTRACT_SUBVECTOR: {
@ -3490,7 +3485,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
// Perform trivial constant folding. // Perform trivial constant folding.
if (SDValue SV = if (SDValue SV =
FoldConstantArithmetic(Opcode, DL, VT, N1.getNode(), N2.getNode())) FoldConstantArithmetic(Opcode, VT, N1.getNode(), N2.getNode()))
return SV; return SV;
// Canonicalize constant to RHS if commutative. // Canonicalize constant to RHS if commutative.
@ -3515,35 +3510,35 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
case ISD::FADD: case ISD::FADD:
s = V1.add(V2, APFloat::rmNearestTiesToEven); s = V1.add(V2, APFloat::rmNearestTiesToEven);
if (!HasFPExceptions || s != APFloat::opInvalidOp) if (!HasFPExceptions || s != APFloat::opInvalidOp)
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FSUB: case ISD::FSUB:
s = V1.subtract(V2, APFloat::rmNearestTiesToEven); s = V1.subtract(V2, APFloat::rmNearestTiesToEven);
if (!HasFPExceptions || s!=APFloat::opInvalidOp) if (!HasFPExceptions || s!=APFloat::opInvalidOp)
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FMUL: case ISD::FMUL:
s = V1.multiply(V2, APFloat::rmNearestTiesToEven); s = V1.multiply(V2, APFloat::rmNearestTiesToEven);
if (!HasFPExceptions || s!=APFloat::opInvalidOp) if (!HasFPExceptions || s!=APFloat::opInvalidOp)
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
break; break;
case ISD::FDIV: case ISD::FDIV:
s = V1.divide(V2, APFloat::rmNearestTiesToEven); s = V1.divide(V2, APFloat::rmNearestTiesToEven);
if (!HasFPExceptions || (s!=APFloat::opInvalidOp && if (!HasFPExceptions || (s!=APFloat::opInvalidOp &&
s!=APFloat::opDivByZero)) { s!=APFloat::opDivByZero)) {
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
} }
break; break;
case ISD::FREM : case ISD::FREM :
s = V1.mod(V2, APFloat::rmNearestTiesToEven); s = V1.mod(V2, APFloat::rmNearestTiesToEven);
if (!HasFPExceptions || (s!=APFloat::opInvalidOp && if (!HasFPExceptions || (s!=APFloat::opInvalidOp &&
s!=APFloat::opDivByZero)) { s!=APFloat::opDivByZero)) {
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
} }
break; break;
case ISD::FCOPYSIGN: case ISD::FCOPYSIGN:
V1.copySign(V2); V1.copySign(V2);
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
default: break; default: break;
} }
} }
@ -3555,7 +3550,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
// FIXME need to be more flexible about rounding mode. // FIXME need to be more flexible about rounding mode.
(void)V.convert(EVTToAPFloatSemantics(VT), (void)V.convert(EVTToAPFloatSemantics(VT),
APFloat::rmNearestTiesToEven, &ignored); APFloat::rmNearestTiesToEven, &ignored);
return getConstantFP(V, DL, VT); return getConstantFP(V, VT);
} }
} }
@ -3580,7 +3575,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
case ISD::SRL: case ISD::SRL:
case ISD::SHL: case ISD::SHL:
if (!VT.isVector()) if (!VT.isVector())
return getConstant(0, DL, VT); // fold op(undef, arg2) -> 0 return getConstant(0, VT); // fold op(undef, arg2) -> 0
// For vectors, we can't easily build an all zero vector, just return // For vectors, we can't easily build an all zero vector, just return
// the LHS. // the LHS.
return N2; return N2;
@ -3595,7 +3590,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
if (N1.getOpcode() == ISD::UNDEF) if (N1.getOpcode() == ISD::UNDEF)
// Handle undef ^ undef -> 0 special case. This is a common // Handle undef ^ undef -> 0 special case. This is a common
// idiom (misuse). // idiom (misuse).
return getConstant(0, DL, VT); return getConstant(0, VT);
// fallthrough // fallthrough
case ISD::ADD: case ISD::ADD:
case ISD::ADDC: case ISD::ADDC:
@ -3619,13 +3614,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
case ISD::SRL: case ISD::SRL:
case ISD::SHL: case ISD::SHL:
if (!VT.isVector()) if (!VT.isVector())
return getConstant(0, DL, VT); // fold op(arg1, undef) -> 0 return getConstant(0, VT); // fold op(arg1, undef) -> 0
// For vectors, we can't easily build an all zero vector, just return // For vectors, we can't easily build an all zero vector, just return
// the LHS. // the LHS.
return N1; return N1;
case ISD::OR: case ISD::OR:
if (!VT.isVector()) if (!VT.isVector())
return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT); return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
// For vectors, we can't easily build an all one vector, just return // For vectors, we can't easily build an all one vector, just return
// the LHS. // the LHS.
return N1; return N1;
@ -3675,7 +3670,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
APFloat::opStatus s = APFloat::opStatus s =
V1.fusedMultiplyAdd(V2, V3, APFloat::rmNearestTiesToEven); V1.fusedMultiplyAdd(V2, V3, APFloat::rmNearestTiesToEven);
if (!TLI->hasFloatingPointExceptions() || s != APFloat::opInvalidOp) if (!TLI->hasFloatingPointExceptions() || s != APFloat::opInvalidOp)
return getConstantFP(V1, DL, VT); return getConstantFP(V1, VT);
} }
break; break;
} }
@ -3810,9 +3805,8 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
assert(C->getAPIntValue().getBitWidth() == 8); assert(C->getAPIntValue().getBitWidth() == 8);
APInt Val = APInt::getSplat(NumBits, C->getAPIntValue()); APInt Val = APInt::getSplat(NumBits, C->getAPIntValue());
if (VT.isInteger()) if (VT.isInteger())
return DAG.getConstant(Val, dl, VT); return DAG.getConstant(Val, VT);
return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), dl, return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), VT);
VT);
} }
assert(Value.getValueType() == MVT::i8 && "memset with non-byte fill value?"); assert(Value.getValueType() == MVT::i8 && "memset with non-byte fill value?");
@ -3826,7 +3820,7 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
// required length. // required length.
APInt Magic = APInt::getSplat(NumBits, APInt(8, 0x01)); APInt Magic = APInt::getSplat(NumBits, APInt(8, 0x01));
Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, Value = DAG.getNode(ISD::MUL, dl, IntVT, Value,
DAG.getConstant(Magic, dl, IntVT)); DAG.getConstant(Magic, IntVT));
} }
if (VT != Value.getValueType() && !VT.isInteger()) if (VT != Value.getValueType() && !VT.isInteger())
@ -3849,16 +3843,15 @@ static SDValue getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG,
// Handle vector with all elements zero. // Handle vector with all elements zero.
if (Str.empty()) { if (Str.empty()) {
if (VT.isInteger()) if (VT.isInteger())
return DAG.getConstant(0, dl, VT); return DAG.getConstant(0, VT);
else if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) else if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
return DAG.getConstantFP(0.0, dl, VT); return DAG.getConstantFP(0.0, VT);
else if (VT.isVector()) { else if (VT.isVector()) {
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
return DAG.getNode(ISD::BITCAST, dl, VT, return DAG.getNode(ISD::BITCAST, dl, VT,
DAG.getConstant(0, dl, DAG.getConstant(0, EVT::getVectorVT(*DAG.getContext(),
EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts)));
EltVT, NumElts)));
} else } else
llvm_unreachable("Expected type!"); llvm_unreachable("Expected type!");
} }
@ -3881,7 +3874,7 @@ static SDValue getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG,
// of a load, then it is cost effective to turn the load into the immediate. // of a load, then it is cost effective to turn the load into the immediate.
Type *Ty = VT.getTypeForEVT(*DAG.getContext()); Type *Ty = VT.getTypeForEVT(*DAG.getContext());
if (TLI.shouldConvertConstantLoadToIntImm(Val, Ty)) if (TLI.shouldConvertConstantLoadToIntImm(Val, Ty))
return DAG.getConstant(Val, dl, VT); return DAG.getConstant(Val, VT);
return SDValue(nullptr, 0); return SDValue(nullptr, 0);
} }
@ -3891,7 +3884,7 @@ static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc dl,
SelectionDAG &DAG) { SelectionDAG &DAG) {
EVT VT = Base.getValueType(); EVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, dl, return DAG.getNode(ISD::ADD, dl,
VT, Base, DAG.getConstant(Offset, dl, VT)); VT, Base, DAG.getConstant(Offset, VT));
} }
/// isMemSrcFromString - Returns true if memcpy source is a string constant. /// isMemSrcFromString - Returns true if memcpy source is a string constant.
@ -5157,7 +5150,7 @@ SDValue SelectionDAG::getVAArg(EVT VT, SDLoc dl,
SDValue Chain, SDValue Ptr, SDValue Chain, SDValue Ptr,
SDValue SV, SDValue SV,
unsigned Align) { unsigned Align) {
SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32) }; SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, MVT::i32) };
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops); return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops);
} }
@ -5936,7 +5929,7 @@ SelectionDAG::getMachineNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
SDValue SDValue
SelectionDAG::getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SelectionDAG::getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
SDValue Operand) { SDValue Operand) {
SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32); SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32);
SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
VT, Operand, SRIdxVal); VT, Operand, SRIdxVal);
return SDValue(Subreg, 0); return SDValue(Subreg, 0);
@ -5947,7 +5940,7 @@ SelectionDAG::getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
SDValue SDValue
SelectionDAG::getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SelectionDAG::getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
SDValue Operand, SDValue Subreg) { SDValue Operand, SDValue Subreg) {
SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32); SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32);
SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL, SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
VT, Operand, Subreg, SRIdxVal); VT, Operand, Subreg, SRIdxVal);
return SDValue(Result, 0); return SDValue(Result, 0);
@ -6662,7 +6655,7 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT, OperandEltVT,
Operand, Operand,
getConstant(i, dl, TLI->getVectorIdxTy())); getConstant(i, TLI->getVectorIdxTy()));
} else { } else {
// A scalar operand; just use it as is. // A scalar operand; just use it as is.
Operands[j] = Operand; Operands[j] = Operand;
@ -6825,10 +6818,9 @@ SelectionDAG::SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT,
"More vector elements requested than available!"); "More vector elements requested than available!");
SDValue Lo, Hi; SDValue Lo, Hi;
Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
getConstant(0, DL, TLI->getVectorIdxTy())); getConstant(0, TLI->getVectorIdxTy()));
Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N,
getConstant(LoVT.getVectorNumElements(), DL, getConstant(LoVT.getVectorNumElements(), TLI->getVectorIdxTy()));
TLI->getVectorIdxTy()));
return std::make_pair(Lo, Hi); return std::make_pair(Lo, Hi);
} }
@ -6844,7 +6836,7 @@ void SelectionDAG::ExtractVectorElements(SDValue Op,
SDLoc SL(Op); SDLoc SL(Op);
for (unsigned i = Start, e = Start + Count; i != e; ++i) { for (unsigned i = Start, e = Start + Count; i != e; ++i) {
Args.push_back(getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Args.push_back(getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
Op, getConstant(i, SL, IdxTy))); Op, getConstant(i, IdxTy)));
} }
} }

501
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

File diff suppressed because it is too large Load Diff

20
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1710,10 +1710,11 @@ bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
return false; return false;
} }
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it. /// by tblgen. Others should not call it.
void SelectionDAGISel:: void SelectionDAGISel::
SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) { SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
std::vector<SDValue> InOps; std::vector<SDValue> InOps;
std::swap(InOps, Ops); std::swap(InOps, Ops);
@ -1759,7 +1760,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
// Add this to the output node. // Add this to the output node.
unsigned NewFlags = unsigned NewFlags =
InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2; i += 2;
} }
@ -1905,13 +1906,11 @@ bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
} }
SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
SDLoc DL(N);
std::vector<SDValue> Ops(N->op_begin(), N->op_end()); std::vector<SDValue> Ops(N->op_begin(), N->op_end());
SelectInlineAsmMemoryOperands(Ops, DL); SelectInlineAsmMemoryOperands(Ops);
const EVT VTs[] = {MVT::Other, MVT::Glue}; const EVT VTs[] = {MVT::Other, MVT::Glue};
SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops); SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
New->setNodeId(-1); New->setNodeId(-1);
return New.getNode(); return New.getNode();
} }
@ -2933,8 +2932,7 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
if (Val & 128) if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex); Val = GetVBR(Val, MatcherTable, MatcherIndex);
RecordedNodes.push_back(std::pair<SDValue, SDNode*>( RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch), CurDAG->getTargetConstant(Val, VT), nullptr));
VT), nullptr));
continue; continue;
} }
case OPC_EmitRegister: { case OPC_EmitRegister: {
@ -2966,12 +2964,10 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
if (Imm->getOpcode() == ISD::Constant) { if (Imm->getOpcode() == ISD::Constant) {
const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(), Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
true);
} else if (Imm->getOpcode() == ISD::ConstantFP) { } else if (Imm->getOpcode() == ISD::ConstantFP) {
const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch), Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
Imm.getValueType(), true);
} }
RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));

29
llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
View File

@ -271,8 +271,7 @@ static SDNode *lowerCallFromStatepoint(ImmutableStatepoint StatepointSite,
} }
} else { } else {
// The token value is never used from here on, just generate a poison value // The token value is never used from here on, just generate a poison value
Builder.setValue(CS.getInstruction(), Builder.setValue(CS.getInstruction(), Builder.DAG.getIntPtrConstant(-1));
Builder.DAG.getIntPtrConstant(-1, Builder.getCurSDLoc()));
} }
// Remove the fake entry we created so we don't have a hanging reference // Remove the fake entry we created so we don't have a hanging reference
// after we delete this node. // after we delete this node.
@ -394,12 +393,9 @@ static void lowerIncomingStatepointValue(SDValue Incoming,
// such in the stackmap. This is required so that the consumer can // such in the stackmap. This is required so that the consumer can
// parse any internal format to the deopt state. It also handles null // parse any internal format to the deopt state. It also handles null
// pointers and other constant pointers in GC states // pointers and other constant pointers in GC states
Ops.push_back(Builder.DAG.getTargetConstant(StackMaps::ConstantOp, Ops.push_back(
Builder.getCurSDLoc(), Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
MVT::i64)); Ops.push_back(Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
Ops.push_back(Builder.DAG.getTargetConstant(C->getSExtValue(),
Builder.getCurSDLoc(),
MVT::i64));
} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Incoming)) { } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Incoming)) {
// This handles allocas as arguments to the statepoint (this is only // This handles allocas as arguments to the statepoint (this is only
// really meaningful for a deopt value. For GC, we'd be trying to // really meaningful for a deopt value. For GC, we'd be trying to
@ -494,11 +490,9 @@ static void lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
// lowered. Note that this is the number of *Values* not the // lowered. Note that this is the number of *Values* not the
// number of SDValues required to lower them. // number of SDValues required to lower them.
const int NumVMSArgs = StatepointSite.numTotalVMSArgs(); const int NumVMSArgs = StatepointSite.numTotalVMSArgs();
Ops.push_back( Builder.DAG.getTargetConstant(StackMaps::ConstantOp, Ops.push_back(
Builder.getCurSDLoc(), Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
MVT::i64)); Ops.push_back(Builder.DAG.getTargetConstant(NumVMSArgs, MVT::i64));
Ops.push_back(Builder.DAG.getTargetConstant(NumVMSArgs, Builder.getCurSDLoc(),
MVT::i64));
assert(NumVMSArgs + 1 == std::distance(StatepointSite.vm_state_begin(), assert(NumVMSArgs + 1 == std::distance(StatepointSite.vm_state_begin(),
StatepointSite.vm_state_end())); StatepointSite.vm_state_end()));
@ -614,7 +608,7 @@ SelectionDAGBuilder::LowerStatepoint(ImmutableStatepoint ISP,
// Get number of arguments incoming directly into call node // Get number of arguments incoming directly into call node
unsigned NumCallRegArgs = unsigned NumCallRegArgs =
CallNode->getNumOperands() - (Glue.getNode() ? 4 : 3); CallNode->getNumOperands() - (Glue.getNode() ? 4 : 3);
Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, getCurSDLoc(), MVT::i32)); Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
// Add call target // Add call target
SDValue CallTarget = SDValue(CallNode->getOperand(1).getNode(), 0); SDValue CallTarget = SDValue(CallNode->getOperand(1).getNode(), 0);
@ -634,10 +628,9 @@ SelectionDAGBuilder::LowerStatepoint(ImmutableStatepoint ISP,
CallingConv::ID CallConv = CS.getCallingConv(); CallingConv::ID CallConv = CS.getCallingConv();
int Flags = cast<ConstantInt>(CS.getArgument(2))->getZExtValue(); int Flags = cast<ConstantInt>(CS.getArgument(2))->getZExtValue();
assert(Flags == 0 && "not expected to be used"); assert(Flags == 0 && "not expected to be used");
Ops.push_back(DAG.getTargetConstant(StackMaps::ConstantOp, getCurSDLoc(), Ops.push_back(DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
MVT::i64)); Ops.push_back(
Ops.push_back(DAG.getTargetConstant(Flags | ((unsigned)CallConv << 1), DAG.getTargetConstant(Flags | ((unsigned)CallConv << 1), MVT::i64));
getCurSDLoc(), MVT::i64));
// Insert all vmstate and gcstate arguments // Insert all vmstate and gcstate arguments
Ops.insert(Ops.end(), LoweredArgs.begin(), LoweredArgs.end()); Ops.insert(Ops.end(), LoweredArgs.begin(), LoweredArgs.end());

199
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -203,7 +203,7 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
SDValue Ops[2] = { NewLHS, NewRHS }; SDValue Ops[2] = { NewLHS, NewRHS };
NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
dl).first; dl).first;
NewRHS = DAG.getConstant(0, dl, RetVT); NewRHS = DAG.getConstant(0, RetVT);
CCCode = getCmpLibcallCC(LC1); CCCode = getCmpLibcallCC(LC1);
if (LC2 != RTLIB::UNKNOWN_LIBCALL) { if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
SDValue Tmp = DAG.getNode(ISD::SETCC, dl, SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
@ -305,7 +305,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded & DAG.getConstant(Demanded &
C->getAPIntValue(), C->getAPIntValue(),
dl, VT)); VT));
return CombineTo(Op, New); return CombineTo(Op, New);
} }
@ -449,7 +449,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return TLO.CombineTo(Op, Op.getOperand(1)); return TLO.CombineTo(Op, Op.getOperand(1));
// If all of the demanded bits in the inputs are known zeros, return zero. // If all of the demanded bits in the inputs are known zeros, return zero.
if ((NewMask & (KnownZero|KnownZero2)) == NewMask) if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType())); return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
// If the RHS is a constant, see if we can simplify it. // If the RHS is a constant, see if we can simplify it.
if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
return true; return true;
@ -537,7 +537,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
if (KnownOne == KnownOne2) { // set bits are the same on both sides if (KnownOne == KnownOne2) { // set bits are the same on both sides
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT); SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Op.getOperand(0), ANDC)); Op.getOperand(0), ANDC));
} }
@ -553,7 +553,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (Expanded != C->getAPIntValue()) { if (Expanded != C->getAPIntValue()) {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, dl, VT)); TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New); return TLO.CombineTo(Op, New);
} }
// if it already has all the bits set, nothing to change // if it already has all the bits set, nothing to change
@ -626,7 +626,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
} }
SDValue NewSA = SDValue NewSA =
TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
InOp.getOperand(0), NewSA)); InOp.getOperand(0), NewSA));
@ -650,7 +650,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
ShTy = InnerVT; ShTy = InnerVT;
SDValue NarrowShl = SDValue NarrowShl =
TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
TLO.DAG.getConstant(ShAmt, dl, ShTy)); TLO.DAG.getConstant(ShAmt, ShTy));
return return
TLO.CombineTo(Op, TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
@ -672,7 +672,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
NewMask.trunc(ShAmt) == 0) { NewMask.trunc(ShAmt) == 0) {
SDValue NewSA = SDValue NewSA =
TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, TLO.DAG.getConstant(ShAmt - InnerShAmt,
Op.getOperand(1).getValueType()); Op.getOperand(1).getValueType());
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
@ -715,7 +715,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
} }
SDValue NewSA = SDValue NewSA =
TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
InOp.getOperand(0), NewSA)); InOp.getOperand(0), NewSA));
} }
@ -780,7 +780,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (Log2 >= 0) { if (Log2 >= 0) {
// The bit must come from the sign. // The bit must come from the sign.
SDValue NewSA = SDValue NewSA =
TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, TLO.DAG.getConstant(BitWidth - 1 - Log2,
Op.getOperand(1).getValueType()); Op.getOperand(1).getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Op.getOperand(0), NewSA)); Op.getOperand(0), NewSA));
@ -811,8 +811,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl, SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
ShiftAmtTy);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
Op.getValueType(), InOp, Op.getValueType(), InOp,
ShiftAmt)); ShiftAmt));
@ -995,7 +994,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (TLO.LegalTypes()) { if (TLO.LegalTypes()) {
uint64_t ShVal = ShAmt->getZExtValue(); uint64_t ShVal = ShAmt->getZExtValue();
Shift = Shift =
TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(Op.getValueType())); TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
} }
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
@ -1053,7 +1052,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (!OpVTLegal && OpVTSizeInBits > 32) if (!OpVTLegal && OpVTSizeInBits > 32)
Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
unsigned ShVal = Op.getValueType().getSizeInBits()-1; unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType()); SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
Op.getValueType(), Op.getValueType(),
Sign, ShAmt)); Sign, ShAmt));
@ -1087,8 +1086,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If we know the value of all of the demanded bits, return this as a // If we know the value of all of the demanded bits, return this as a
// constant. // constant.
if ((NewMask & (KnownZero|KnownOne)) == NewMask) if ((NewMask & (KnownZero|KnownOne)) == NewMask)
return TLO.CombineTo(Op, return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
return false; return false;
} }
@ -1224,14 +1222,13 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
switch (Cond) { switch (Cond) {
default: break; default: break;
case ISD::SETFALSE: case ISD::SETFALSE:
case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT); case ISD::SETFALSE2: return DAG.getConstant(0, VT);
case ISD::SETTRUE: case ISD::SETTRUE:
case ISD::SETTRUE2: { case ISD::SETTRUE2: {
TargetLowering::BooleanContent Cnt = TargetLowering::BooleanContent Cnt =
getBooleanContents(N0->getValueType(0)); getBooleanContents(N0->getValueType(0));
return DAG.getConstant( return DAG.getConstant(
Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl, Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
VT);
} }
} }
@ -1265,7 +1262,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// (srl (ctlz x), 5) == 1 -> X == 0 // (srl (ctlz x), 5) == 1 -> X == 0
Cond = ISD::SETEQ; Cond = ISD::SETEQ;
} }
SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); SDValue Zero = DAG.getConstant(0, N0.getValueType());
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
Zero, Cond); Zero, Cond);
} }
@ -1286,10 +1283,10 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// (ctpop x) u> 1 -> (x & x-1) != 0 // (ctpop x) u> 1 -> (x & x-1) != 0
if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
DAG.getConstant(1, dl, CTVT)); DAG.getConstant(1, CTVT));
SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC); return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
} }
// TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
@ -1343,7 +1340,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
// Will get folded away. // Will get folded away.
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
return DAG.getSetCC(dl, VT, Trunc, C, Cond); return DAG.getSetCC(dl, VT, Trunc, C, Cond);
} }
} }
@ -1394,7 +1391,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
SDValue Ptr = Lod->getBasePtr(); SDValue Ptr = Lod->getBasePtr();
if (bestOffset != 0) if (bestOffset != 0)
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
DAG.getConstant(bestOffset, dl, PtrType)); DAG.getConstant(bestOffset, PtrType));
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Lod->getPointerInfo().getWithOffset(bestOffset), Lod->getPointerInfo().getWithOffset(bestOffset),
@ -1402,8 +1399,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getSetCC(dl, VT, return DAG.getSetCC(dl, VT,
DAG.getNode(ISD::AND, dl, newVT, NewLoad, DAG.getNode(ISD::AND, dl, newVT, NewLoad,
DAG.getConstant(bestMask.trunc(bestWidth), DAG.getConstant(bestMask.trunc(bestWidth),
dl, newVT)), newVT)),
DAG.getConstant(0LL, dl, newVT), Cond); DAG.getConstant(0LL, newVT), Cond);
} }
} }
} }
@ -1419,18 +1416,18 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
switch (Cond) { switch (Cond) {
case ISD::SETUGT: case ISD::SETUGT:
case ISD::SETUGE: case ISD::SETUGE:
case ISD::SETEQ: return DAG.getConstant(0, dl, VT); case ISD::SETEQ: return DAG.getConstant(0, VT);
case ISD::SETULT: case ISD::SETULT:
case ISD::SETULE: case ISD::SETULE:
case ISD::SETNE: return DAG.getConstant(1, dl, VT); case ISD::SETNE: return DAG.getConstant(1, VT);
case ISD::SETGT: case ISD::SETGT:
case ISD::SETGE: case ISD::SETGE:
// True if the sign bit of C1 is set. // True if the sign bit of C1 is set.
return DAG.getConstant(C1.isNegative(), dl, VT); return DAG.getConstant(C1.isNegative(), VT);
case ISD::SETLT: case ISD::SETLT:
case ISD::SETLE: case ISD::SETLE:
// True if the sign bit of C1 isn't set. // True if the sign bit of C1 isn't set.
return DAG.getConstant(C1.isNonNegative(), dl, VT); return DAG.getConstant(C1.isNonNegative(), VT);
default: default:
break; break;
} }
@ -1449,7 +1446,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
(isOperationLegal(ISD::SETCC, newVT) && (isOperationLegal(ISD::SETCC, newVT) &&
getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) { getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT); EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
NewConst, Cond); NewConst, Cond);
@ -1470,7 +1467,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// If the constant doesn't fit into the number of bits for the source of // If the constant doesn't fit into the number of bits for the source of
// the sign extension, it is impossible for both sides to be equal. // the sign extension, it is impossible for both sides to be equal.
if (C1.getMinSignedBits() > ExtSrcTyBits) if (C1.getMinSignedBits() > ExtSrcTyBits)
return DAG.getConstant(Cond == ISD::SETNE, dl, VT); return DAG.getConstant(Cond == ISD::SETNE, VT);
SDValue ZextOp; SDValue ZextOp;
EVT Op0Ty = N0.getOperand(0).getValueType(); EVT Op0Ty = N0.getOperand(0).getValueType();
@ -1479,7 +1476,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
} else { } else {
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
DAG.getConstant(Imm, dl, Op0Ty)); DAG.getConstant(Imm, Op0Ty));
} }
if (!DCI.isCalledByLegalizer()) if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(ZextOp.getNode()); DCI.AddToWorklist(ZextOp.getNode());
@ -1488,7 +1485,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
DAG.getConstant(C1 & APInt::getLowBitsSet( DAG.getConstant(C1 & APInt::getLowBitsSet(
ExtDstTyBits, ExtDstTyBits,
ExtSrcTyBits), ExtSrcTyBits),
dl, ExtDstTy), ExtDstTy),
Cond); Cond);
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) { (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
@ -1558,20 +1555,20 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (Op0.getValueType().bitsGT(VT)) if (Op0.getValueType().bitsGT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT, Op0 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
DAG.getConstant(1, dl, VT)); DAG.getConstant(1, VT));
else if (Op0.getValueType().bitsLT(VT)) else if (Op0.getValueType().bitsLT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT, Op0 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
DAG.getConstant(1, dl, VT)); DAG.getConstant(1, VT));
return DAG.getSetCC(dl, VT, Op0, return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, dl, Op0.getValueType()), DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
} }
if (Op0.getOpcode() == ISD::AssertZext && if (Op0.getOpcode() == ISD::AssertZext &&
cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
return DAG.getSetCC(dl, VT, Op0, return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, dl, Op0.getValueType()), DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
} }
} }
@ -1588,7 +1585,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// Canonicalize GE/LE comparisons to use GT/LT comparisons. // Canonicalize GE/LE comparisons to use GT/LT comparisons.
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
// X >= C0 --> X > (C0 - 1) // X >= C0 --> X > (C0 - 1)
APInt C = C1 - 1; APInt C = C1 - 1;
ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
@ -1597,13 +1594,13 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
(!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
isLegalICmpImmediate(C.getSExtValue())))) { isLegalICmpImmediate(C.getSExtValue())))) {
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(C, dl, N1.getValueType()), DAG.getConstant(C, N1.getValueType()),
NewCC); NewCC);
} }
} }
if (Cond == ISD::SETLE || Cond == ISD::SETULE) { if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
// X <= C0 --> X < (C0 + 1) // X <= C0 --> X < (C0 + 1)
APInt C = C1 + 1; APInt C = C1 + 1;
ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
@ -1612,19 +1609,19 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
(!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
isLegalICmpImmediate(C.getSExtValue())))) { isLegalICmpImmediate(C.getSExtValue())))) {
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(C, dl, N1.getValueType()), DAG.getConstant(C, N1.getValueType()),
NewCC); NewCC);
} }
} }
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
return DAG.getConstant(0, dl, VT); // X < MIN --> false return DAG.getConstant(0, VT); // X < MIN --> false
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
return DAG.getConstant(1, dl, VT); // X >= MIN --> true return DAG.getConstant(1, VT); // X >= MIN --> true
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
return DAG.getConstant(0, dl, VT); // X > MAX --> false return DAG.getConstant(0, VT); // X > MAX --> false
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
return DAG.getConstant(1, dl, VT); // X <= MAX --> true return DAG.getConstant(1, VT); // X <= MAX --> true
// Canonicalize setgt X, Min --> setne X, Min // Canonicalize setgt X, Min --> setne X, Min
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
@ -1636,12 +1633,12 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// If we have setult X, 1, turn it into seteq X, 0 // If we have setult X, 1, turn it into seteq X, 0
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(MinVal, dl, N0.getValueType()), DAG.getConstant(MinVal, N0.getValueType()),
ISD::SETEQ); ISD::SETEQ);
// If we have setugt X, Max-1, turn it into seteq X, Max // If we have setugt X, Max-1, turn it into seteq X, Max
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(MaxVal, dl, N0.getValueType()), DAG.getConstant(MaxVal, N0.getValueType()),
ISD::SETEQ); ISD::SETEQ);
// If we have "setcc X, C0", check to see if we can shrink the immediate // If we have "setcc X, C0", check to see if we can shrink the immediate
@ -1651,14 +1648,14 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (Cond == ISD::SETUGT && if (Cond == ISD::SETUGT &&
C1 == APInt::getSignedMaxValue(OperandBitSize)) C1 == APInt::getSignedMaxValue(OperandBitSize))
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(0, dl, N1.getValueType()), DAG.getConstant(0, N1.getValueType()),
ISD::SETLT); ISD::SETLT);
// SETULT X, SINTMIN -> SETGT X, -1 // SETULT X, SINTMIN -> SETGT X, -1
if (Cond == ISD::SETULT && if (Cond == ISD::SETULT &&
C1 == APInt::getSignedMinValue(OperandBitSize)) { C1 == APInt::getSignedMinValue(OperandBitSize)) {
SDValue ConstMinusOne = SDValue ConstMinusOne =
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl, DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
N1.getValueType()); N1.getValueType());
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
} }
@ -1677,8 +1674,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (AndRHS->getAPIntValue().isPowerOf2()) { if (AndRHS->getAPIntValue().isPowerOf2()) {
return DAG.getNode(ISD::TRUNCATE, dl, VT, return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl, DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
ShiftTy)));
} }
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
// (X & 8) == 8 --> (X & 8) >> 3 // (X & 8) == 8 --> (X & 8) >> 3
@ -1686,8 +1682,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (C1.isPowerOf2()) { if (C1.isPowerOf2()) {
return DAG.getNode(ISD::TRUNCATE, dl, VT, return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
DAG.getConstant(C1.logBase2(), dl, DAG.getConstant(C1.logBase2(), ShiftTy)));
ShiftTy)));
} }
} }
} }
@ -1706,9 +1701,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
getPointerTy() : getShiftAmountTy(N0.getValueType()); getPointerTy() : getShiftAmountTy(N0.getValueType());
EVT CmpTy = N0.getValueType(); EVT CmpTy = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
DAG.getConstant(ShiftBits, dl, DAG.getConstant(ShiftBits, ShiftTy));
ShiftTy)); SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
} }
} }
@ -1735,8 +1729,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
getPointerTy() : getShiftAmountTy(N0.getValueType()); getPointerTy() : getShiftAmountTy(N0.getValueType());
EVT CmpTy = N0.getValueType(); EVT CmpTy = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
DAG.getConstant(ShiftBits, dl, ShiftTy)); DAG.getConstant(ShiftBits, ShiftTy));
SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy); SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
} }
} }
@ -1755,9 +1749,9 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
switch (ISD::getUnorderedFlavor(Cond)) { switch (ISD::getUnorderedFlavor(Cond)) {
default: llvm_unreachable("Unknown flavor!"); default: llvm_unreachable("Unknown flavor!");
case 0: // Known false. case 0: // Known false.
return DAG.getConstant(0, dl, VT); return DAG.getConstant(0, VT);
case 1: // Known true. case 1: // Known true.
return DAG.getConstant(1, dl, VT); return DAG.getConstant(1, VT);
case 2: // Undefined. case 2: // Undefined.
return DAG.getUNDEF(VT); return DAG.getUNDEF(VT);
} }
@ -1824,13 +1818,13 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// We can always fold X == X for integer setcc's. // We can always fold X == X for integer setcc's.
if (N0.getValueType().isInteger()) { if (N0.getValueType().isInteger()) {
return DAG.getConstant(EqVal, dl, VT); return DAG.getConstant(EqVal, VT);
} }
unsigned UOF = ISD::getUnorderedFlavor(Cond); unsigned UOF = ISD::getUnorderedFlavor(Cond);
if (UOF == 2) // FP operators that are undefined on NaNs. if (UOF == 2) // FP operators that are undefined on NaNs.
return DAG.getConstant(EqVal, dl, VT); return DAG.getConstant(EqVal, VT);
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
return DAG.getConstant(EqVal, dl, VT); return DAG.getConstant(EqVal, VT);
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
// if it is not already. // if it is not already.
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
@ -1871,7 +1865,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getSetCC(dl, VT, N0.getOperand(0), return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(RHSC->getAPIntValue()- DAG.getConstant(RHSC->getAPIntValue()-
LHSR->getAPIntValue(), LHSR->getAPIntValue(),
dl, N0.getValueType()), Cond); N0.getValueType()), Cond);
} }
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
@ -1883,7 +1877,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
DAG.getSetCC(dl, VT, N0.getOperand(0), DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(LHSR->getAPIntValue() ^ DAG.getConstant(LHSR->getAPIntValue() ^
RHSC->getAPIntValue(), RHSC->getAPIntValue(),
dl, N0.getValueType()), N0.getValueType()),
Cond); Cond);
} }
@ -1894,7 +1888,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
DAG.getSetCC(dl, VT, N0.getOperand(1), DAG.getSetCC(dl, VT, N0.getOperand(1),
DAG.getConstant(SUBC->getAPIntValue() - DAG.getConstant(SUBC->getAPIntValue() -
RHSC->getAPIntValue(), RHSC->getAPIntValue(),
dl, N0.getValueType()), N0.getValueType()),
Cond); Cond);
} }
} }
@ -1911,18 +1905,16 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (!LegalRHSImm || N0.getNode()->hasOneUse()) { if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
if (N0.getOperand(0) == N1) if (N0.getOperand(0) == N1)
return DAG.getSetCC(dl, VT, N0.getOperand(1), return DAG.getSetCC(dl, VT, N0.getOperand(1),
DAG.getConstant(0, dl, N0.getValueType()), Cond); DAG.getConstant(0, N0.getValueType()), Cond);
if (N0.getOperand(1) == N1) { if (N0.getOperand(1) == N1) {
if (DAG.isCommutativeBinOp(N0.getOpcode())) if (DAG.isCommutativeBinOp(N0.getOpcode()))
return DAG.getSetCC(dl, VT, N0.getOperand(0), return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(0, dl, N0.getValueType()), DAG.getConstant(0, N0.getValueType()), Cond);
Cond);
if (N0.getNode()->hasOneUse()) { if (N0.getNode()->hasOneUse()) {
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1 // (Z-X) == X --> Z == X<<1
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
DAG.getConstant(1, dl, DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
getShiftAmountTy(N1.getValueType())));
if (!DCI.isCalledByLegalizer()) if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(SH.getNode()); DCI.AddToWorklist(SH.getNode());
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
@ -1936,17 +1928,16 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// Simplify X == (X+Z) --> Z == 0 // Simplify X == (X+Z) --> Z == 0
if (N1.getOperand(0) == N0) if (N1.getOperand(0) == N0)
return DAG.getSetCC(dl, VT, N1.getOperand(1), return DAG.getSetCC(dl, VT, N1.getOperand(1),
DAG.getConstant(0, dl, N1.getValueType()), Cond); DAG.getConstant(0, N1.getValueType()), Cond);
if (N1.getOperand(1) == N0) { if (N1.getOperand(1) == N0) {
if (DAG.isCommutativeBinOp(N1.getOpcode())) if (DAG.isCommutativeBinOp(N1.getOpcode()))
return DAG.getSetCC(dl, VT, N1.getOperand(0), return DAG.getSetCC(dl, VT, N1.getOperand(0),
DAG.getConstant(0, dl, N1.getValueType()), Cond); DAG.getConstant(0, N1.getValueType()), Cond);
if (N1.getNode()->hasOneUse()) { if (N1.getNode()->hasOneUse()) {
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// X == (Z-X) --> X<<1 == Z // X == (Z-X) --> X<<1 == Z
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
DAG.getConstant(1, dl, DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
getShiftAmountTy(N0.getValueType())));
if (!DCI.isCalledByLegalizer()) if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(SH.getNode()); DCI.AddToWorklist(SH.getNode());
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
@ -1964,7 +1955,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
if (DCI.isBeforeLegalizeOps() || if (DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(Cond, N0.getSimpleValueType())) { isCondCodeLegal(Cond, N0.getSimpleValueType())) {
SDValue Zero = DAG.getConstant(0, dl, N1.getValueType()); SDValue Zero = DAG.getConstant(0, N1.getValueType());
return DAG.getSetCC(dl, VT, N0, Zero, Cond); return DAG.getSetCC(dl, VT, N0, Zero, Cond);
} }
} }
@ -1975,7 +1966,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
if (DCI.isBeforeLegalizeOps() || if (DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(Cond, N1.getSimpleValueType())) { isCondCodeLegal(Cond, N1.getSimpleValueType())) {
SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); SDValue Zero = DAG.getConstant(0, N0.getValueType());
return DAG.getSetCC(dl, VT, N1, Zero, Cond); return DAG.getSetCC(dl, VT, N1, Zero, Cond);
} }
} }
@ -2190,7 +2181,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
// now; without this it would get ZExt'd later in // now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic. // ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
SDLoc(C), MVT::i64)); MVT::i64));
return; return;
} }
} }
@ -2658,8 +2649,7 @@ SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
unsigned ShAmt = d.countTrailingZeros(); unsigned ShAmt = d.countTrailingZeros();
if (ShAmt) { if (ShAmt) {
// TODO: For UDIV use SRL instead of SRA. // TODO: For UDIV use SRL instead of SRA.
SDValue Amt = DAG.getConstant(ShAmt, dl, SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
getShiftAmountTy(Op1.getValueType()));
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false, Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
true); true);
d = d.ashr(ShAmt); d = d.ashr(ShAmt);
@ -2670,7 +2660,7 @@ SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
while ((t = d*xn) != 1) while ((t = d*xn) != 1)
xn *= APInt(d.getBitWidth(), 2) - t; xn *= APInt(d.getBitWidth(), 2) - t;
Op2 = DAG.getConstant(xn, dl, Op1.getValueType()); Op2 = DAG.getConstant(xn, Op1.getValueType());
return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
} }
@ -2699,12 +2689,12 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
isOperationLegalOrCustom(ISD::MULHS, VT)) isOperationLegalOrCustom(ISD::MULHS, VT))
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
DAG.getConstant(magics.m, dl, VT)); DAG.getConstant(magics.m, VT));
else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
N->getOperand(0), N->getOperand(0),
DAG.getConstant(magics.m, dl, VT)).getNode(), 1); DAG.getConstant(magics.m, VT)).getNode(), 1);
else else
return SDValue(); // No mulhs or equvialent return SDValue(); // No mulhs or equvialent
// If d > 0 and m < 0, add the numerator // If d > 0 and m < 0, add the numerator
@ -2720,13 +2710,12 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
// Shift right algebraic if shift value is nonzero // Shift right algebraic if shift value is nonzero
if (magics.s > 0) { if (magics.s > 0) {
Q = DAG.getNode(ISD::SRA, dl, VT, Q, Q = DAG.getNode(ISD::SRA, dl, VT, Q,
DAG.getConstant(magics.s, dl, DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
getShiftAmountTy(Q.getValueType())));
Created->push_back(Q.getNode()); Created->push_back(Q.getNode());
} }
// Extract the sign bit and add it to the quotient // Extract the sign bit and add it to the quotient
SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, DAG.getConstant(VT.getScalarSizeInBits() - 1,
getShiftAmountTy(Q.getValueType()))); getShiftAmountTy(Q.getValueType())));
Created->push_back(T.getNode()); Created->push_back(T.getNode());
return DAG.getNode(ISD::ADD, dl, VT, Q, T); return DAG.getNode(ISD::ADD, dl, VT, Q, T);
@ -2760,8 +2749,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
if (magics.a != 0 && !Divisor[0]) { if (magics.a != 0 && !Divisor[0]) {
unsigned Shift = Divisor.countTrailingZeros(); unsigned Shift = Divisor.countTrailingZeros();
Q = DAG.getNode(ISD::SRL, dl, VT, Q, Q = DAG.getNode(ISD::SRL, dl, VT, Q,
DAG.getConstant(Shift, dl, DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
getShiftAmountTy(Q.getValueType())));
Created->push_back(Q.getNode()); Created->push_back(Q.getNode());
// Get magic number for the shifted divisor. // Get magic number for the shifted divisor.
@ -2773,11 +2761,11 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
// FIXME: We should support doing a MUL in a wider type // FIXME: We should support doing a MUL in a wider type
if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
isOperationLegalOrCustom(ISD::MULHU, VT)) isOperationLegalOrCustom(ISD::MULHU, VT))
Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT)); Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
DAG.getConstant(magics.m, dl, VT)).getNode(), 1); DAG.getConstant(magics.m, VT)).getNode(), 1);
else else
return SDValue(); // No mulhu or equvialent return SDValue(); // No mulhu or equvialent
@ -2787,20 +2775,17 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
assert(magics.s < Divisor.getBitWidth() && assert(magics.s < Divisor.getBitWidth() &&
"We shouldn't generate an undefined shift!"); "We shouldn't generate an undefined shift!");
return DAG.getNode(ISD::SRL, dl, VT, Q, return DAG.getNode(ISD::SRL, dl, VT, Q,
DAG.getConstant(magics.s, dl, DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
getShiftAmountTy(Q.getValueType())));
} else { } else {
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Created->push_back(NPQ.getNode()); Created->push_back(NPQ.getNode());
NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
DAG.getConstant(1, dl, DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
getShiftAmountTy(NPQ.getValueType())));
Created->push_back(NPQ.getNode()); Created->push_back(NPQ.getNode());
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Created->push_back(NPQ.getNode()); Created->push_back(NPQ.getNode());
return DAG.getNode(ISD::SRL, dl, VT, NPQ, return DAG.getNode(ISD::SRL, dl, VT, NPQ,
DAG.getConstant(magics.s - 1, dl, DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
getShiftAmountTy(NPQ.getValueType())));
} }
} }
@ -2887,7 +2872,7 @@ bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
isOperationLegalOrCustom(ISD::SRL, VT) && isOperationLegalOrCustom(ISD::SRL, VT) &&
isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT)); SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
@ -2937,13 +2922,13 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
// https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
VT.getSizeInBits()); VT.getSizeInBits());
SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
SDValue Bias = DAG.getConstant(127, dl, IntVT); SDValue Bias = DAG.getConstant(127, IntVT);
SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl, SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
IntVT); IntVT);
SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
@ -2959,7 +2944,7 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
SDValue R = DAG.getNode(ISD::OR, dl, IntVT, SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
DAG.getConstant(0x00800000, dl, IntVT)); DAG.getConstant(0x00800000, IntVT));
R = DAG.getZExtOrTrunc(R, dl, NVT); R = DAG.getZExtOrTrunc(R, dl, NVT);
@ -2979,7 +2964,7 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
DAG.getNode(ISD::XOR, dl, NVT, R, Sign), DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
Sign); Sign);
Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT), Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT); DAG.getConstant(0, NVT), Ret, ISD::SETLT);
return true; return true;
} }

139
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -252,9 +252,8 @@ bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
return false; return false;
unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
SDLoc dl(N); Val = CurDAG->getTargetConstant(Immed, MVT::i32);
Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32); Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
return true; return true;
} }
@ -287,8 +286,7 @@ bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
return false; return false;
Immed &= 0xFFFFFFULL; Immed &= 0xFFFFFFULL;
return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val, return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
Shift);
} }
/// getShiftTypeForNode - Translate a shift node to the corresponding /// getShiftTypeForNode - Translate a shift node to the corresponding
@ -336,7 +334,7 @@ bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val); unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
Reg = N.getOperand(0); Reg = N.getOperand(0);
Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32); Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
return isWorthFolding(N); return isWorthFolding(N);
} }
@ -437,7 +435,6 @@ static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
/// is a lane in the upper half of a 128-bit vector. Recognize and select this /// is a lane in the upper half of a 128-bit vector. Recognize and select this
/// so that we don't emit unnecessary lane extracts. /// so that we don't emit unnecessary lane extracts.
SDNode *AArch64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) { SDNode *AArch64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
SDLoc dl(N);
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1); SDValue Op1 = N->getOperand(1);
SDValue MLAOp1; // Will hold ordinary multiplicand for MLA. SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
@ -454,7 +451,7 @@ SDNode *AArch64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
return nullptr; return nullptr;
} }
SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal }; SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
@ -477,11 +474,10 @@ SDNode *AArch64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
break; break;
} }
return CurDAG->getMachineNode(MLAOpc, dl, N->getValueType(0), Ops); return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
} }
SDNode *AArch64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) { SDNode *AArch64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
SDLoc dl(N);
SDValue SMULLOp0; SDValue SMULLOp0;
SDValue SMULLOp1; SDValue SMULLOp1;
int LaneIdx; int LaneIdx;
@ -490,7 +486,7 @@ SDNode *AArch64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
LaneIdx)) LaneIdx))
return nullptr; return nullptr;
SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal }; SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
@ -521,7 +517,7 @@ SDNode *AArch64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
} else } else
llvm_unreachable("Unrecognized intrinsic."); llvm_unreachable("Unrecognized intrinsic.");
return CurDAG->getMachineNode(SMULLOpc, dl, N->getValueType(0), Ops); return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
} }
/// Instructions that accept extend modifiers like UXTW expect the register /// Instructions that accept extend modifiers like UXTW expect the register
@ -532,10 +528,9 @@ static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
if (N.getValueType() == MVT::i32) if (N.getValueType() == MVT::i32)
return N; return N;
SDLoc dl(N); SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
dl, MVT::i32, N, SubReg); SDLoc(N), MVT::i32, N, SubReg);
return SDValue(Node, 0); return SDValue(Node, 0);
} }
@ -575,8 +570,7 @@ bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
// (harmlessly) synthesize one by injected an EXTRACT_SUBREG here. // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
Reg = narrowIfNeeded(CurDAG, Reg); Reg = narrowIfNeeded(CurDAG, Reg);
Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), MVT::i32);
MVT::i32);
return isWorthFolding(N); return isWorthFolding(N);
} }
@ -606,12 +600,11 @@ static bool isWorthFoldingADDlow(SDValue N) {
/// reference, which determines the scale. /// reference, which determines the scale.
bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size, bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
SDValue &Base, SDValue &OffImm) { SDValue &Base, SDValue &OffImm) {
SDLoc dl(N);
const TargetLowering *TLI = getTargetLowering(); const TargetLowering *TLI = getTargetLowering();
if (N.getOpcode() == ISD::FrameIndex) { if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64); OffImm = CurDAG->getTargetConstant(0, MVT::i64);
return true; return true;
} }
@ -644,7 +637,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
int FI = cast<FrameIndexSDNode>(Base)->getIndex(); int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64); OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
return true; return true;
} }
} }
@ -660,7 +653,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
// add x0, Xbase, #offset // add x0, Xbase, #offset
// ldr x0, [x0] // ldr x0, [x0]
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64); OffImm = CurDAG->getTargetConstant(0, MVT::i64);
return true; return true;
} }
@ -687,7 +680,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
const TargetLowering *TLI = getTargetLowering(); const TargetLowering *TLI = getTargetLowering();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i64); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i64);
return true; return true;
} }
} }
@ -695,12 +688,12 @@ bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
} }
static SDValue Widen(SelectionDAG *CurDAG, SDValue N) { static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
SDLoc dl(N); SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
SDValue ImpDef = SDValue( SDValue ImpDef = SDValue(
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0); CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
0);
MachineSDNode *Node = CurDAG->getMachineNode( MachineSDNode *Node = CurDAG->getMachineNode(
TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
return SDValue(Node, 0); return SDValue(Node, 0);
} }
@ -714,7 +707,6 @@ bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue()) if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
return false; return false;
SDLoc dl(N);
if (WantExtend) { if (WantExtend) {
AArch64_AM::ShiftExtendType Ext = AArch64_AM::ShiftExtendType Ext =
getExtendTypeForNode(N.getOperand(0), true); getExtendTypeForNode(N.getOperand(0), true);
@ -722,11 +714,10 @@ bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
return false; return false;
Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0)); Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
MVT::i32);
} else { } else {
Offset = N.getOperand(0); Offset = N.getOperand(0);
SignExtend = CurDAG->getTargetConstant(0, dl, MVT::i32); SignExtend = CurDAG->getTargetConstant(0, MVT::i32);
} }
unsigned LegalShiftVal = Log2_32(Size); unsigned LegalShiftVal = Log2_32(Size);
@ -749,7 +740,6 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
return false; return false;
SDValue LHS = N.getOperand(0); SDValue LHS = N.getOperand(0);
SDValue RHS = N.getOperand(1); SDValue RHS = N.getOperand(1);
SDLoc dl(N);
// We don't want to match immediate adds here, because they are better lowered // We don't want to match immediate adds here, because they are better lowered
// to the register-immediate addressing modes. // to the register-immediate addressing modes.
@ -772,7 +762,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL && if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) { SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
Base = LHS; Base = LHS;
DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32); DoShift = CurDAG->getTargetConstant(true, MVT::i32);
return true; return true;
} }
@ -780,12 +770,12 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL && if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) { SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
Base = RHS; Base = RHS;
DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32); DoShift = CurDAG->getTargetConstant(true, MVT::i32);
return true; return true;
} }
// There was no shift, whatever else we find. // There was no shift, whatever else we find.
DoShift = CurDAG->getTargetConstant(false, dl, MVT::i32); DoShift = CurDAG->getTargetConstant(false, MVT::i32);
AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend; AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
// Try to match an unshifted extend on the LHS. // Try to match an unshifted extend on the LHS.
@ -794,8 +784,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
AArch64_AM::InvalidShiftExtend) { AArch64_AM::InvalidShiftExtend) {
Base = RHS; Base = RHS;
Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0)); Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
MVT::i32);
if (isWorthFolding(LHS)) if (isWorthFolding(LHS))
return true; return true;
} }
@ -806,8 +795,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
AArch64_AM::InvalidShiftExtend) { AArch64_AM::InvalidShiftExtend) {
Base = LHS; Base = LHS;
Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0)); Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
MVT::i32);
if (isWorthFolding(RHS)) if (isWorthFolding(RHS))
return true; return true;
} }
@ -838,7 +826,6 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
return false; return false;
SDValue LHS = N.getOperand(0); SDValue LHS = N.getOperand(0);
SDValue RHS = N.getOperand(1); SDValue RHS = N.getOperand(1);
SDLoc DL(N);
// Check if this particular node is reused in any non-memory related // Check if this particular node is reused in any non-memory related
// operation. If yes, do not try to fold this node into the address // operation. If yes, do not try to fold this node into the address
@ -870,6 +857,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
isPreferredADD(ImmOff) || isPreferredADD(-ImmOff)) isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
return false; return false;
SDLoc DL(N.getNode());
SDValue Ops[] = { RHS }; SDValue Ops[] = { RHS };
SDNode *MOVI = SDNode *MOVI =
CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops); CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
@ -885,7 +873,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL && if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) { SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
Base = LHS; Base = LHS;
DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32); DoShift = CurDAG->getTargetConstant(true, MVT::i32);
return true; return true;
} }
@ -893,15 +881,15 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL && if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) { SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
Base = RHS; Base = RHS;
DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32); DoShift = CurDAG->getTargetConstant(true, MVT::i32);
return true; return true;
} }
// Match any non-shifted, non-extend, non-immediate add expression. // Match any non-shifted, non-extend, non-immediate add expression.
Base = LHS; Base = LHS;
Offset = RHS; Offset = RHS;
SignExtend = CurDAG->getTargetConstant(false, DL, MVT::i32); SignExtend = CurDAG->getTargetConstant(false, MVT::i32);
DoShift = CurDAG->getTargetConstant(false, DL, MVT::i32); DoShift = CurDAG->getTargetConstant(false, MVT::i32);
// Reg1 + Reg2 is free: no check needed. // Reg1 + Reg2 is free: no check needed.
return true; return true;
} }
@ -934,18 +922,18 @@ SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
assert(Regs.size() >= 2 && Regs.size() <= 4); assert(Regs.size() >= 2 && Regs.size() <= 4);
SDLoc DL(Regs[0]); SDLoc DL(Regs[0].getNode());
SmallVector<SDValue, 4> Ops; SmallVector<SDValue, 4> Ops;
// First operand of REG_SEQUENCE is the desired RegClass. // First operand of REG_SEQUENCE is the desired RegClass.
Ops.push_back( Ops.push_back(
CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32)); CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
// Then we get pairs of source & subregister-position for the components. // Then we get pairs of source & subregister-position for the components.
for (unsigned i = 0; i < Regs.size(); ++i) { for (unsigned i = 0; i < Regs.size(); ++i) {
Ops.push_back(Regs[i]); Ops.push_back(Regs[i]);
Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
} }
SDNode *N = SDNode *N =
@ -1042,21 +1030,19 @@ SDNode *AArch64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset()); ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
int OffsetVal = (int)OffsetOp->getZExtValue(); int OffsetVal = (int)OffsetOp->getZExtValue();
SDLoc dl(N); SDValue Offset = CurDAG->getTargetConstant(OffsetVal, MVT::i64);
SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
SDValue Ops[] = { Base, Offset, Chain }; SDValue Ops[] = { Base, Offset, Chain };
SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, DstVT,
MVT::Other, Ops); MVT::Other, Ops);
// Either way, we're replacing the node, so tell the caller that. // Either way, we're replacing the node, so tell the caller that.
Done = true; Done = true;
SDValue LoadedVal = SDValue(Res, 1); SDValue LoadedVal = SDValue(Res, 1);
if (InsertTo64) { if (InsertTo64) {
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
LoadedVal = LoadedVal =
SDValue(CurDAG->getMachineNode( SDValue(CurDAG->getMachineNode(
AArch64::SUBREG_TO_REG, dl, MVT::i64, AArch64::SUBREG_TO_REG, SDLoc(N), MVT::i64,
CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal, CurDAG->getTargetConstant(0, MVT::i64), LoadedVal, SubReg),
SubReg),
0); 0);
} }
@ -1212,7 +1198,7 @@ SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
unsigned LaneNo = unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue(); cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 3), N->getOperand(0)}; N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
SDValue SuperReg = SDValue(Ld, 0); SDValue SuperReg = SDValue(Ld, 0);
@ -1254,8 +1240,7 @@ SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue(); cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
SDValue Ops[] = {RegSeq, SDValue Ops[] = {RegSeq,
CurDAG->getTargetConstant(LaneNo, dl, CurDAG->getTargetConstant(LaneNo, MVT::i64), // Lane Number
MVT::i64), // Lane Number
N->getOperand(NumVecs + 2), // Base register N->getOperand(NumVecs + 2), // Base register
N->getOperand(NumVecs + 3), // Incremental N->getOperand(NumVecs + 3), // Incremental
N->getOperand(0)}; N->getOperand(0)};
@ -1306,7 +1291,7 @@ SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
unsigned LaneNo = unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue(); cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 3), N->getOperand(0)}; N->getOperand(NumVecs + 3), N->getOperand(0)};
SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops); SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
@ -1339,7 +1324,7 @@ SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
unsigned LaneNo = unsigned LaneNo =
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue(); cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, MVT::i64),
N->getOperand(NumVecs + 2), // Base Register N->getOperand(NumVecs + 2), // Base Register
N->getOperand(NumVecs + 3), // Incremental N->getOperand(NumVecs + 3), // Incremental
N->getOperand(0)}; N->getOperand(0)};
@ -1605,24 +1590,23 @@ SDNode *AArch64DAGToDAGISel::SelectBitfieldExtractOp(SDNode *N) {
return nullptr; return nullptr;
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc dl(N);
// If the bit extract operation is 64bit but the original type is 32bit, we // If the bit extract operation is 64bit but the original type is 32bit, we
// need to add one EXTRACT_SUBREG. // need to add one EXTRACT_SUBREG.
if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) { if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(LSB, dl, MVT::i64), SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(LSB, MVT::i64),
CurDAG->getTargetConstant(MSB, dl, MVT::i64)}; CurDAG->getTargetConstant(MSB, MVT::i64)};
SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); SDNode *BFM = CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i64, Ops64);
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
MachineSDNode *Node = MachineSDNode *Node =
CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::i32, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32,
SDValue(BFM, 0), SubReg); SDValue(BFM, 0), SubReg);
return Node; return Node;
} }
SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(LSB, dl, VT), SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(LSB, VT),
CurDAG->getTargetConstant(MSB, dl, VT)}; CurDAG->getTargetConstant(MSB, VT)};
return CurDAG->SelectNodeTo(N, Opc, VT, Ops); return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
} }
@ -1826,7 +1810,6 @@ static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
return Op; return Op;
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned BitWidth = VT.getSizeInBits(); unsigned BitWidth = VT.getSizeInBits();
unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri; unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
@ -1834,16 +1817,16 @@ static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
if (ShlAmount > 0) { if (ShlAmount > 0) {
// LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
ShiftNode = CurDAG->getMachineNode( ShiftNode = CurDAG->getMachineNode(
UBFMOpc, dl, VT, Op, UBFMOpc, SDLoc(Op), VT, Op,
CurDAG->getTargetConstant(BitWidth - ShlAmount, dl, VT), CurDAG->getTargetConstant(BitWidth - ShlAmount, VT),
CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, dl, VT)); CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, VT));
} else { } else {
// LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
assert(ShlAmount < 0 && "expected right shift"); assert(ShlAmount < 0 && "expected right shift");
int ShrAmount = -ShlAmount; int ShrAmount = -ShlAmount;
ShiftNode = CurDAG->getMachineNode( ShiftNode = CurDAG->getMachineNode(
UBFMOpc, dl, VT, Op, CurDAG->getTargetConstant(ShrAmount, dl, VT), UBFMOpc, SDLoc(Op), VT, Op, CurDAG->getTargetConstant(ShrAmount, VT),
CurDAG->getTargetConstant(BitWidth - 1, dl, VT)); CurDAG->getTargetConstant(BitWidth - 1, VT));
} }
return SDValue(ShiftNode, 0); return SDValue(ShiftNode, 0);
@ -2008,11 +1991,10 @@ SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
return nullptr; return nullptr;
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc dl(N);
SDValue Ops[] = { Opd0, SDValue Ops[] = { Opd0,
Opd1, Opd1,
CurDAG->getTargetConstant(LSB, dl, VT), CurDAG->getTargetConstant(LSB, VT),
CurDAG->getTargetConstant(MSB, dl, VT) }; CurDAG->getTargetConstant(MSB, VT) };
return CurDAG->SelectNodeTo(N, Opc, VT, Ops); return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
} }
@ -2110,7 +2092,7 @@ AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
// finding FBits, but it must still be in range. // finding FBits, but it must still be in range.
if (FBits == 0 || FBits > RegWidth) return false; if (FBits == 0 || FBits > RegWidth) return false;
FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32); FixedPos = CurDAG->getTargetConstant(FBits, MVT::i32);
return true; return true;
} }
@ -2225,9 +2207,8 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
const TargetLowering *TLI = getTargetLowering(); const TargetLowering *TLI = getTargetLowering();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
SDLoc DL(Node); SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32), CurDAG->getTargetConstant(Shifter, MVT::i32) };
CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
return CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops); return CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
} }
case ISD::INTRINSIC_W_CHAIN: { case ISD::INTRINSIC_W_CHAIN: {

484
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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File diff suppressed because it is too large Load Diff

13
llvm/lib/Target/AArch64/AArch64InstrFormats.td
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@ -441,11 +441,11 @@ def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
// instructions for splatting repeating bit patterns across the immediate. // instructions for splatting repeating bit patterns across the immediate.
def logical_imm32_XFORM : SDNodeXForm<imm, [{ def logical_imm32_XFORM : SDNodeXForm<imm, [{
uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32); uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>; }]>;
def logical_imm64_XFORM : SDNodeXForm<imm, [{ def logical_imm64_XFORM : SDNodeXForm<imm, [{
uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64); uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>; }]>;
let DiagnosticType = "LogicalSecondSource" in { let DiagnosticType = "LogicalSecondSource" in {
@ -682,7 +682,7 @@ def fpimm32 : Operand<f32>,
}], SDNodeXForm<fpimm, [{ }], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF(); APFloat InVal = N->getValueAPF();
uint32_t enc = AArch64_AM::getFP32Imm(InVal); uint32_t enc = AArch64_AM::getFP32Imm(InVal);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> { }]>> {
let ParserMatchClass = FPImmOperand; let ParserMatchClass = FPImmOperand;
let PrintMethod = "printFPImmOperand"; let PrintMethod = "printFPImmOperand";
@ -693,7 +693,7 @@ def fpimm64 : Operand<f64>,
}], SDNodeXForm<fpimm, [{ }], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF(); APFloat InVal = N->getValueAPF();
uint32_t enc = AArch64_AM::getFP64Imm(InVal); uint32_t enc = AArch64_AM::getFP64Imm(InVal);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> { }]>> {
let ParserMatchClass = FPImmOperand; let ParserMatchClass = FPImmOperand;
let PrintMethod = "printFPImmOperand"; let PrintMethod = "printFPImmOperand";
@ -768,7 +768,7 @@ def simdimmtype10 : Operand<i32>,
uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF() uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
.bitcastToAPInt() .bitcastToAPInt()
.getZExtValue()); .getZExtValue());
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> { }]>> {
let ParserMatchClass = SIMDImmType10Operand; let ParserMatchClass = SIMDImmType10Operand;
let PrintMethod = "printSIMDType10Operand"; let PrintMethod = "printSIMDType10Operand";
@ -2192,8 +2192,7 @@ class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
def inv_cond_XFORM : SDNodeXForm<imm, [{ def inv_cond_XFORM : SDNodeXForm<imm, [{
AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue()); AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), SDLoc(N), return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
MVT::i32);
}]>; }]>;
multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> { multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {

30
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -498,7 +498,7 @@ def i64imm_32bit : ImmLeaf<i64, [{
}]>; }]>;
def trunc_imm : SDNodeXForm<imm, [{ def trunc_imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
}]>; }]>;
def : Pat<(i64 i64imm_32bit:$src), def : Pat<(i64 i64imm_32bit:$src),
@ -507,12 +507,12 @@ def : Pat<(i64 i64imm_32bit:$src),
// Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant( return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
}]>; }]>;
def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant( return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
}]>; }]>;
@ -857,57 +857,57 @@ defm UBFM : BitfieldImm<0b10, "ubfm">;
def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{ def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = (32 - N->getZExtValue()) & 0x1f; uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{ def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 31 - N->getZExtValue(); uint64_t enc = 31 - N->getZExtValue();
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
// min(7, 31 - shift_amt) // min(7, 31 - shift_amt)
def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 31 - N->getZExtValue(); uint64_t enc = 31 - N->getZExtValue();
enc = enc > 7 ? 7 : enc; enc = enc > 7 ? 7 : enc;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
// min(15, 31 - shift_amt) // min(15, 31 - shift_amt)
def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 31 - N->getZExtValue(); uint64_t enc = 31 - N->getZExtValue();
enc = enc > 15 ? 15 : enc; enc = enc > 15 ? 15 : enc;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{ def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = (64 - N->getZExtValue()) & 0x3f; uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{ def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 63 - N->getZExtValue(); uint64_t enc = 63 - N->getZExtValue();
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
// min(7, 63 - shift_amt) // min(7, 63 - shift_amt)
def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 63 - N->getZExtValue(); uint64_t enc = 63 - N->getZExtValue();
enc = enc > 7 ? 7 : enc; enc = enc > 7 ? 7 : enc;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
// min(15, 63 - shift_amt) // min(15, 63 - shift_amt)
def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 63 - N->getZExtValue(); uint64_t enc = 63 - N->getZExtValue();
enc = enc > 15 ? 15 : enc; enc = enc > 15 ? 15 : enc;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
// min(31, 63 - shift_amt) // min(31, 63 - shift_amt)
def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{ def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
uint64_t enc = 63 - N->getZExtValue(); uint64_t enc = 63 - N->getZExtValue();
enc = enc > 31 ? 31 : enc; enc = enc > 31 ? 31 : enc;
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(enc, MVT::i64);
}]>; }]>;
def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)), def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
@ -3563,13 +3563,13 @@ def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
// instruction even if the types don't match: we just have to remap the lane // instruction even if the types don't match: we just have to remap the lane
// carefully. N.b. this trick only applies to truncations. // carefully. N.b. this trick only applies to truncations.
def VecIndex_x2 : SDNodeXForm<imm, [{ def VecIndex_x2 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
}]>; }]>;
def VecIndex_x4 : SDNodeXForm<imm, [{ def VecIndex_x4 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
}]>; }]>;
def VecIndex_x8 : SDNodeXForm<imm, [{ def VecIndex_x8 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
}]>; }]>;
multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT, multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,

304
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -83,8 +83,8 @@ public:
/// getI32Imm - Return a target constant of type i32 with the specified /// getI32Imm - Return a target constant of type i32 with the specified
/// value. /// value.
inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
SDNode *Select(SDNode *N) override; SDNode *Select(SDNode *N) override;
@ -134,7 +134,7 @@ public:
bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) { bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
const ConstantSDNode *CN = cast<ConstantSDNode>(N); const ConstantSDNode *CN = cast<ConstantSDNode>(N);
Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32); Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
return true; return true;
} }
@ -272,8 +272,7 @@ private:
SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
// Get the alignment operand for a NEON VLD or VST instruction. // Get the alignment operand for a NEON VLD or VST instruction.
SDValue GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs, SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
bool is64BitVector);
}; };
} }
@ -395,13 +394,11 @@ void ARMDAGToDAGISel::PreprocessISelDAG() {
// Now make the transformation. // Now make the transformation.
Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
Srl.getOperand(0), Srl.getOperand(0),
CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
MVT::i32));
N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32, N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
Srl, Srl, CurDAG->getConstant(And_imm, MVT::i32));
CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32));
N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32, N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); N1, CurDAG->getConstant(TZ, MVT::i32));
CurDAG->UpdateNodeOperands(N, N0, N1); CurDAG->UpdateNodeOperands(N, N0, N1);
} }
} }
@ -486,7 +483,7 @@ bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
if (!RHS) return false; if (!RHS) return false;
ShImmVal = RHS->getZExtValue() & 31; ShImmVal = RHS->getZExtValue() & 31;
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -513,7 +510,7 @@ bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal)) if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
return false; return false;
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -530,7 +527,7 @@ bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
// Match frame index. // Match frame index.
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -539,7 +536,7 @@ bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
Base = N.getOperand(0); Base = N.getOperand(0);
} else } else
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -554,14 +551,14 @@ bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
int FI = cast<FrameIndexSDNode>(Base)->getIndex(); int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
} }
// Base only. // Base only.
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -586,7 +583,7 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
Base = Offset = N.getOperand(0); Base = Offset = N.getOperand(0);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
ARM_AM::lsl), ARM_AM::lsl),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
} }
@ -657,7 +654,7 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
} }
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -685,7 +682,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
Base = Offset = N.getOperand(0); Base = Offset = N.getOperand(0);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
ARM_AM::lsl), ARM_AM::lsl),
SDLoc(N), MVT::i32); MVT::i32);
return AM2_SHOP; return AM2_SHOP;
} }
} }
@ -706,7 +703,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
ARM_AM::no_shift), ARM_AM::no_shift),
SDLoc(N), MVT::i32); MVT::i32);
return AM2_BASE; return AM2_BASE;
} }
@ -729,7 +726,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
} }
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
ARM_AM::no_shift), ARM_AM::no_shift),
SDLoc(N), MVT::i32); MVT::i32);
return AM2_BASE; return AM2_BASE;
} }
} }
@ -740,7 +737,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
ARM_AM::no_shift), ARM_AM::no_shift),
SDLoc(N), MVT::i32); MVT::i32);
return AM2_BASE; return AM2_BASE;
} }
@ -795,7 +792,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
} }
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
SDLoc(N), MVT::i32); MVT::i32);
return AM2_SHOP; return AM2_SHOP;
} }
@ -831,7 +828,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
} }
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -847,7 +844,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits. if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
if (AddSub == ARM_AM::sub) Val *= -1; if (AddSub == ARM_AM::sub) Val *= -1;
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(Val, SDLoc(Op), MVT::i32); Opc = CurDAG->getTargetConstant(Val, MVT::i32);
return true; return true;
} }
@ -868,7 +865,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
ARM_AM::no_shift), ARM_AM::no_shift),
SDLoc(Op), MVT::i32); MVT::i32);
return true; return true;
} }
@ -887,8 +884,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
// X - C is canonicalize to X + -C, no need to handle it here. // X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0); Base = N.getOperand(0);
Offset = N.getOperand(1); Offset = N.getOperand(1);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0), SDLoc(N), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
MVT::i32);
return true; return true;
} }
@ -899,8 +895,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
MVT::i32);
return true; return true;
} }
@ -920,15 +915,13 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
AddSub = ARM_AM::sub; AddSub = ARM_AM::sub;
RHSC = -RHSC; RHSC = -RHSC;
} }
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC), SDLoc(N), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
MVT::i32);
return true; return true;
} }
Base = N.getOperand(0); Base = N.getOperand(0);
Offset = N.getOperand(1); Offset = N.getOperand(1);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
MVT::i32);
return true; return true;
} }
@ -943,14 +936,12 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
int Val; int Val;
if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits. if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
Offset = CurDAG->getRegister(0, MVT::i32); Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), SDLoc(Op), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
MVT::i32);
return true; return true;
} }
Offset = N; Offset = N;
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op), Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
MVT::i32);
return true; return true;
} }
@ -966,7 +957,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
Base = N.getOperand(0); Base = N.getOperand(0);
} }
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -986,13 +977,13 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
RHSC = -RHSC; RHSC = -RHSC;
} }
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
Base = N; Base = N;
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -1021,7 +1012,7 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
Alignment = MemN->getAlignment(); Alignment = MemN->getAlignment();
} }
Align = CurDAG->getTargetConstant(Alignment, SDLoc(N), MVT::i32); Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
return true; return true;
} }
@ -1045,7 +1036,7 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
Offset = N.getOperand(0); Offset = N.getOperand(0);
SDValue N1 = N.getOperand(1); SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
SDLoc(N), MVT::i32); MVT::i32);
return true; return true;
} }
@ -1150,7 +1141,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
Base = N; Base = N;
} }
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1167,7 +1158,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
if (LHSC != 0 || RHSC != 0) return false; if (LHSC != 0 || RHSC != 0) return false;
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1175,12 +1166,12 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
int RHSC; int RHSC;
if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) { if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
Base = N.getOperand(0); Base = N.getOperand(0);
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
Base = N.getOperand(0); Base = N.getOperand(0);
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1212,7 +1203,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
if (MFI->getObjectAlignment(FI) < 4) if (MFI->getObjectAlignment(FI) < 4)
MFI->setObjectAlignment(FI, 4); MFI->setObjectAlignment(FI, 4);
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1235,7 +1226,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
MFI->setObjectAlignment(FI, 4); MFI->setObjectAlignment(FI, 4);
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
} }
@ -1264,7 +1255,7 @@ bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
unsigned ShImmVal = 0; unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
ShImmVal = RHS->getZExtValue() & 31; ShImmVal = RHS->getZExtValue() & 31;
Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), SDLoc(N)); Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
return true; return true;
} }
@ -1282,7 +1273,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
// Match frame index. // Match frame index.
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1293,7 +1284,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
return false; // We want to select t2LDRpci instead. return false; // We want to select t2LDRpci instead.
} else } else
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1312,14 +1303,14 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
int FI = cast<FrameIndexSDNode>(Base)->getIndex(); int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
} }
// Base only. // Base only.
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -1341,7 +1332,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
int FI = cast<FrameIndexSDNode>(Base)->getIndex(); int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
} }
@ -1358,8 +1349,8 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
int RHSC; int RHSC;
if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits. if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
? CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32) ? CurDAG->getTargetConstant(RHSC, MVT::i32)
: CurDAG->getTargetConstant(-RHSC, SDLoc(N), MVT::i32); : CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true; return true;
} }
@ -1408,7 +1399,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
} }
} }
ShImm = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32); ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
return true; return true;
} }
@ -1418,7 +1409,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
// This *must* succeed since it's used for the irreplaceable ldrex and strex // This *must* succeed since it's used for the irreplaceable ldrex and strex
// instructions. // instructions.
Base = N; Base = N;
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N)) if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
return true; return true;
@ -1437,15 +1428,15 @@ bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
} }
OffImm = CurDAG->getTargetConstant(RHSC/4, SDLoc(N), MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
return true; return true;
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// getAL - Returns a ARMCC::AL immediate node. /// getAL - Returns a ARMCC::AL immediate node.
static inline SDValue getAL(SelectionDAG *CurDAG, SDLoc dl) { static inline SDValue getAL(SelectionDAG *CurDAG) {
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, dl, MVT::i32); return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
} }
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
@ -1504,14 +1495,14 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain }; CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
MVT::i32, MVT::Other, Ops); MVT::i32, MVT::Other, Ops);
} else { } else {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain }; CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
MVT::i32, MVT::Other, Ops); MVT::i32, MVT::Other, Ops);
@ -1560,7 +1551,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
if (Match) { if (Match) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), SDValue Ops[]= { Base, Offset, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain }; CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32, return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
MVT::Other, Ops); MVT::Other, Ops);
@ -1573,9 +1564,9 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = SDValue RegClass =
CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
} }
@ -1584,9 +1575,9 @@ SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = SDValue RegClass =
CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32); CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
} }
@ -1594,10 +1585,9 @@ SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
/// \brief Form a quad register from a pair of D registers. /// \brief Form a quad register from a pair of D registers.
SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
} }
@ -1605,10 +1595,9 @@ SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
/// \brief Form 4 consecutive D registers from a pair of Q registers. /// \brief Form 4 consecutive D registers from a pair of Q registers.
SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
} }
@ -1618,11 +1607,11 @@ SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
SDValue V2, SDValue V3) { SDValue V2, SDValue V3) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = SDValue RegClass =
CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32); CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32); SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
V2, SubReg2, V3, SubReg3 }; V2, SubReg2, V3, SubReg3 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
@ -1632,12 +1621,11 @@ SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
SDValue V2, SDValue V3) { SDValue V2, SDValue V3) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
V2, SubReg2, V3, SubReg3 }; V2, SubReg2, V3, SubReg3 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
@ -1647,12 +1635,11 @@ SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
SDValue V2, SDValue V3) { SDValue V2, SDValue V3) {
SDLoc dl(V0.getNode()); SDLoc dl(V0.getNode());
SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
MVT::i32); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
V2, SubReg2, V3, SubReg3 }; V2, SubReg2, V3, SubReg3 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
@ -1661,8 +1648,8 @@ SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
/// of a NEON VLD or VST instruction. The supported values depend on the /// of a NEON VLD or VST instruction. The supported values depend on the
/// number of registers being loaded. /// number of registers being loaded.
SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, SDLoc dl, SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
unsigned NumVecs, bool is64BitVector) { bool is64BitVector) {
unsigned NumRegs = NumVecs; unsigned NumRegs = NumVecs;
if (!is64BitVector && NumVecs < 3) if (!is64BitVector && NumVecs < 3)
NumRegs *= 2; NumRegs *= 2;
@ -1677,7 +1664,7 @@ SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, SDLoc dl,
else else
Alignment = 0; Alignment = 0;
return CurDAG->getTargetConstant(Alignment, dl, MVT::i32); return CurDAG->getTargetConstant(Alignment, MVT::i32);
} }
static bool isVLDfixed(unsigned Opc) static bool isVLDfixed(unsigned Opc)
@ -1797,7 +1784,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
bool is64BitVector = VT.is64BitVector(); bool is64BitVector = VT.is64BitVector();
Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
unsigned OpcodeIndex; unsigned OpcodeIndex;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
@ -1834,7 +1821,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
ResTys.push_back(MVT::i32); ResTys.push_back(MVT::i32);
ResTys.push_back(MVT::Other); ResTys.push_back(MVT::Other);
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDNode *VLd; SDNode *VLd;
SmallVector<SDValue, 7> Ops; SmallVector<SDValue, 7> Ops;
@ -1934,7 +1921,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
EVT VT = N->getOperand(Vec0Idx).getValueType(); EVT VT = N->getOperand(Vec0Idx).getValueType();
bool is64BitVector = VT.is64BitVector(); bool is64BitVector = VT.is64BitVector();
Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
unsigned OpcodeIndex; unsigned OpcodeIndex;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
@ -1961,7 +1948,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
ResTys.push_back(MVT::i32); ResTys.push_back(MVT::i32);
ResTys.push_back(MVT::Other); ResTys.push_back(MVT::Other);
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 7> Ops; SmallVector<SDValue, 7> Ops;
@ -2097,7 +2084,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
if (Alignment == 1) if (Alignment == 1)
Alignment = 0; Alignment = 0;
} }
Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32); Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
unsigned OpcodeIndex; unsigned OpcodeIndex;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
@ -2125,7 +2112,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
ResTys.push_back(MVT::i32); ResTys.push_back(MVT::i32);
ResTys.push_back(MVT::Other); ResTys.push_back(MVT::Other);
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
@ -2155,7 +2142,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
} }
Ops.push_back(SuperReg); Ops.push_back(SuperReg);
Ops.push_back(getI32Imm(Lane, dl)); Ops.push_back(getI32Imm(Lane));
Ops.push_back(Pred); Ops.push_back(Pred);
Ops.push_back(Reg0); Ops.push_back(Reg0);
Ops.push_back(Chain); Ops.push_back(Chain);
@ -2210,7 +2197,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
if (Alignment == 1) if (Alignment == 1)
Alignment = 0; Alignment = 0;
} }
Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32); Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
unsigned OpcodeIndex; unsigned OpcodeIndex;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
@ -2221,7 +2208,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
case MVT::v2i32: OpcodeIndex = 2; break; case MVT::v2i32: OpcodeIndex = 2; break;
} }
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue SuperReg; SDValue SuperReg;
unsigned Opc = Opcodes[OpcodeIndex]; unsigned Opc = Opcodes[OpcodeIndex];
@ -2292,7 +2279,7 @@ SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
Ops.push_back(N->getOperand(1)); Ops.push_back(N->getOperand(1));
Ops.push_back(RegSeq); Ops.push_back(RegSeq);
Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
Ops.push_back(getAL(CurDAG, dl)); // predicate Ops.push_back(getAL(CurDAG)); // predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
return CurDAG->getMachineNode(Opc, dl, VT, Ops); return CurDAG->getMachineNode(Opc, dl, VT, Ops);
} }
@ -2305,7 +2292,6 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
unsigned Opc = isSigned unsigned Opc = isSigned
? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
: (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
SDLoc dl(N);
// For unsigned extracts, check for a shift right and mask // For unsigned extracts, check for a shift right and mask
unsigned And_imm = 0; unsigned And_imm = 0;
@ -2332,25 +2318,25 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32), CurDAG->getTargetConstant(LSB, MVT::i32),
getAL(CurDAG, dl), Reg0, Reg0 }; getAL(CurDAG), Reg0, Reg0 };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
} }
// ARM models shift instructions as MOVsi with shifter operand. // ARM models shift instructions as MOVsi with shifter operand.
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
SDValue ShOpc = SDValue ShOpc =
CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB), dl, CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
MVT::i32); MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
getAL(CurDAG, dl), Reg0, Reg0 }; getAL(CurDAG), Reg0, Reg0 };
return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
} }
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32), CurDAG->getTargetConstant(LSB, MVT::i32),
CurDAG->getTargetConstant(Width, dl, MVT::i32), CurDAG->getTargetConstant(Width, MVT::i32),
getAL(CurDAG, dl), Reg0 }; getAL(CurDAG), Reg0 };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
} }
} }
@ -2371,9 +2357,9 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
return nullptr; return nullptr;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32), CurDAG->getTargetConstant(LSB, MVT::i32),
CurDAG->getTargetConstant(Width, dl, MVT::i32), CurDAG->getTargetConstant(Width, MVT::i32),
getAL(CurDAG, dl), Reg0 }; getAL(CurDAG), Reg0 };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
} }
} }
@ -2390,9 +2376,9 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, dl, MVT::i32), CurDAG->getTargetConstant(LSB, MVT::i32),
CurDAG->getTargetConstant(Width - 1, dl, MVT::i32), CurDAG->getTargetConstant(Width - 1, MVT::i32),
getAL(CurDAG, dl), Reg0 }; getAL(CurDAG), Reg0 };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
} }
@ -2498,7 +2484,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDNode *ResNode; SDNode *ResNode;
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
@ -2506,8 +2492,8 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
} else { } else {
SDValue Ops[] = { SDValue Ops[] = {
CPIdx, CPIdx,
CurDAG->getTargetConstant(0, dl, MVT::i32), CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG, dl), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode() CurDAG->getEntryNode()
}; };
@ -2532,12 +2518,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
if (MFI->getObjectAlignment(FI) < 4) if (MFI->getObjectAlignment(FI) < 4)
MFI->setObjectAlignment(FI, 4); MFI->setObjectAlignment(FI, 4);
return CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI, return CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
CurDAG->getTargetConstant(0, dl, MVT::i32)); CurDAG->getTargetConstant(0, MVT::i32));
} else { } else {
unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
ARM::t2ADDri : ARM::ADDri); ARM::t2ADDri : ARM::ADDri);
SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32), SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) }; CurDAG->getRegister(0, MVT::i32) };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
} }
@ -2563,14 +2549,13 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
break; break;
SDValue V = N->getOperand(0); SDValue V = N->getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32); SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
} else { } else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
Reg0 };
return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
} }
} }
@ -2580,14 +2565,13 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
break; break;
SDValue V = N->getOperand(0); SDValue V = N->getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32); SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
} else { } else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
Reg0 };
return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
} }
} }
@ -2626,9 +2610,9 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
(N1CVal & 0xffffU) == 0xffffU && (N1CVal & 0xffffU) == 0xffffU &&
(N2CVal & 0xffffU) == 0x0U) { (N2CVal & 0xffffU) == 0x0U) {
SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16, SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
dl, MVT::i32); MVT::i32);
SDValue Ops[] = { N0.getOperand(0), Imm16, SDValue Ops[] = { N0.getOperand(0), Imm16,
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) }; getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(Opc, dl, VT, Ops); return CurDAG->getMachineNode(Opc, dl, VT, Ops);
} }
} }
@ -2636,18 +2620,18 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
} }
case ARMISD::VMOVRRD: case ARMISD::VMOVRRD:
return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
N->getOperand(0), getAL(CurDAG, dl), N->getOperand(0), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32)); CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: { case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only()) if (Subtarget->isThumb1Only())
break; break;
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) }; getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops); return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
} else { } else {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) }; CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
ARM::UMULL : ARM::UMULLv5, ARM::UMULL : ARM::UMULLv5,
@ -2659,11 +2643,11 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
break; break;
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) }; getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops); return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
} else { } else {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32), getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) }; CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
ARM::SMULL : ARM::SMULLv5, ARM::SMULL : ARM::SMULLv5,
@ -2673,12 +2657,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case ARMISD::UMLAL:{ case ARMISD::UMLAL:{
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl), N->getOperand(3), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32)}; CurDAG->getRegister(0, MVT::i32)};
return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops); return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
}else{ }else{
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl), N->getOperand(3), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) }; CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
@ -2689,12 +2673,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case ARMISD::SMLAL:{ case ARMISD::SMLAL:{
if (Subtarget->isThumb()) { if (Subtarget->isThumb()) {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl), N->getOperand(3), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32)}; CurDAG->getRegister(0, MVT::i32)};
return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops); return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
}else{ }else{
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
N->getOperand(3), getAL(CurDAG, dl), N->getOperand(3), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) }; CurDAG->getRegister(0, MVT::i32) };
return CurDAG->getMachineNode(Subtarget->hasV6Ops() ? return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
@ -2738,7 +2722,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
assert(N3.getOpcode() == ISD::Register); assert(N3.getOpcode() == ISD::Register);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()), dl, cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32); MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
@ -2767,7 +2751,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VZIPq32; break; case MVT::v4i32: Opc = ARM::VZIPq32; break;
} }
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
@ -2787,7 +2771,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VUZPq32; break; case MVT::v4i32: Opc = ARM::VUZPq32; break;
} }
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
@ -2806,7 +2790,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VTRNq32; break; case MVT::v4i32: Opc = ARM::VTRNq32; break;
} }
SDValue Pred = getAL(CurDAG, dl); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
@ -3054,7 +3038,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
// Place arguments in the right order. // Place arguments in the right order.
SmallVector<SDValue, 7> Ops; SmallVector<SDValue, 7> Ops;
Ops.push_back(MemAddr); Ops.push_back(MemAddr);
Ops.push_back(getAL(CurDAG, dl)); Ops.push_back(getAL(CurDAG));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
@ -3070,8 +3054,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
if (isThumb) if (isThumb)
Result = SDValue(Ld, 0); Result = SDValue(Ld, 0);
else { else {
SDValue SubRegIdx = SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
Result = SDValue(ResNode,0); Result = SDValue(ResNode,0);
@ -3083,8 +3066,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
if (isThumb) if (isThumb)
Result = SDValue(Ld, 1); Result = SDValue(Ld, 1);
else { else {
SDValue SubRegIdx = SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
Result = SDValue(ResNode,0); Result = SDValue(ResNode,0);
@ -3116,7 +3098,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
// arm_strexd uses GPRPair. // arm_strexd uses GPRPair.
Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
Ops.push_back(MemAddr); Ops.push_back(MemAddr);
Ops.push_back(getAL(CurDAG, dl)); Ops.push_back(getAL(CurDAG));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
@ -3308,7 +3290,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
Ops.push_back(N->getOperand(0)); Ops.push_back(N->getOperand(0));
Ops.push_back(N->getOperand(1)); Ops.push_back(N->getOperand(1));
Ops.push_back(getAL(CurDAG, dl)); // Predicate Ops.push_back(getAL(CurDAG)); // Predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops); return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
} }
@ -3324,7 +3306,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SmallVector<SDValue, 6> Ops; SmallVector<SDValue, 6> Ops;
Ops.push_back(RegSeq); Ops.push_back(RegSeq);
Ops.push_back(N->getOperand(2)); Ops.push_back(N->getOperand(2));
Ops.push_back(getAL(CurDAG, dl)); // Predicate Ops.push_back(getAL(CurDAG)); // Predicate
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops); return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
} }
@ -3469,7 +3451,7 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID); Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
// Replace the current flag. // Replace the current flag.
AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant( AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
Flag, dl, MVT::i32); Flag, MVT::i32);
// Add the new register node and skip the original two GPRs. // Add the new register node and skip the original two GPRs.
AsmNodeOperands.push_back(PairedReg); AsmNodeOperands.push_back(PairedReg);
// Skip the next two GPRs. // Skip the next two GPRs.

474
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

21
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -323,12 +323,12 @@ class RegConstraint<string C> {
// imm_neg_XFORM - Return the negation of an i32 immediate value. // imm_neg_XFORM - Return the negation of an i32 immediate value.
def imm_neg_XFORM : SDNodeXForm<imm, [{ def imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>; }]>;
// imm_not_XFORM - Return the complement of a i32 immediate value. // imm_not_XFORM - Return the complement of a i32 immediate value.
def imm_not_XFORM : SDNodeXForm<imm, [{ def imm_not_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
}]>; }]>;
/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
@ -343,8 +343,7 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{
/// Split a 32-bit immediate into two 16 bit parts. /// Split a 32-bit immediate into two 16 bit parts.
def hi16 : SDNodeXForm<imm, [{ def hi16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
MVT::i32);
}]>; }]>;
def lo16AllZero : PatLeaf<(i32 imm), [{ def lo16AllZero : PatLeaf<(i32 imm), [{
@ -486,10 +485,10 @@ def neon_vcvt_imm32 : Operand<i32> {
def rot_imm_XFORM: SDNodeXForm<imm, [{ def rot_imm_XFORM: SDNodeXForm<imm, [{
switch (N->getZExtValue()){ switch (N->getZExtValue()){
default: llvm_unreachable(nullptr); default: llvm_unreachable(nullptr);
case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); case 0: return CurDAG->getTargetConstant(0, MVT::i32);
case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); case 8: return CurDAG->getTargetConstant(1, MVT::i32);
case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); case 16: return CurDAG->getTargetConstant(2, MVT::i32);
case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); case 24: return CurDAG->getTargetConstant(3, MVT::i32);
} }
}]>; }]>;
def RotImmAsmOperand : AsmOperandClass { def RotImmAsmOperand : AsmOperandClass {
@ -768,8 +767,7 @@ def bf_inv_mask_imm : Operand<i32>,
} }
def imm1_32_XFORM: SDNodeXForm<imm, [{ def imm1_32_XFORM: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
MVT::i32);
}]>; }]>;
def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
@ -782,8 +780,7 @@ def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
} }
def imm1_16_XFORM: SDNodeXForm<imm, [{ def imm1_16_XFORM: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
MVT::i32);
}]>; }]>;
def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],

21
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -2393,41 +2393,36 @@ def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
// Extract D sub-registers of Q registers. // Extract D sub-registers of Q registers.
def DSubReg_i8_reg : SDNodeXForm<imm, [{ def DSubReg_i8_reg : SDNodeXForm<imm, [{
assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N), return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
MVT::i32);
}]>; }]>;
def DSubReg_i16_reg : SDNodeXForm<imm, [{ def DSubReg_i16_reg : SDNodeXForm<imm, [{
assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N), return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
MVT::i32);
}]>; }]>;
def DSubReg_i32_reg : SDNodeXForm<imm, [{ def DSubReg_i32_reg : SDNodeXForm<imm, [{
assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N), return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
MVT::i32);
}]>; }]>;
def DSubReg_f64_reg : SDNodeXForm<imm, [{ def DSubReg_f64_reg : SDNodeXForm<imm, [{
assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N), return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
MVT::i32);
}]>; }]>;
// Extract S sub-registers of Q/D registers. // Extract S sub-registers of Q/D registers.
def SSubReg_f32_reg : SDNodeXForm<imm, [{ def SSubReg_f32_reg : SDNodeXForm<imm, [{
assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N), return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
MVT::i32);
}]>; }]>;
// Translate lane numbers from Q registers to D subregs. // Translate lane numbers from Q registers to D subregs.
def SubReg_i8_lane : SDNodeXForm<imm, [{ def SubReg_i8_lane : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
}]>; }]>;
def SubReg_i16_lane : SDNodeXForm<imm, [{ def SubReg_i16_lane : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
}]>; }]>;
def SubReg_i32_lane : SDNodeXForm<imm, [{ def SubReg_i32_lane : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

9
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -21,7 +21,7 @@ def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
def imm_sr_XFORM: SDNodeXForm<imm, [{ def imm_sr_XFORM: SDNodeXForm<imm, [{
unsigned Imm = N->getZExtValue(); unsigned Imm = N->getZExtValue();
return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
}]>; }]>;
def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
def imm_sr : Operand<i32>, PatLeaf<(imm), [{ def imm_sr : Operand<i32>, PatLeaf<(imm), [{
@ -33,8 +33,7 @@ def imm_sr : Operand<i32>, PatLeaf<(imm), [{
} }
def imm_comp_XFORM : SDNodeXForm<imm, [{ def imm_comp_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
MVT::i32);
}]>; }]>;
def imm0_7_neg : PatLeaf<(i32 imm), [{ def imm0_7_neg : PatLeaf<(i32 imm), [{
@ -62,12 +61,12 @@ def thumb_immshifted : PatLeaf<(imm), [{
def thumb_immshifted_val : SDNodeXForm<imm, [{ def thumb_immshifted_val : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(V, MVT::i32);
}]>; }]>;
def thumb_immshifted_shamt : SDNodeXForm<imm, [{ def thumb_immshifted_shamt : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(V, MVT::i32);
}]>; }]>;
// Scaled 4 immediate. // Scaled 4 immediate.

8
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -54,14 +54,12 @@ def t2_so_reg : Operand<i32>, // reg imm
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
MVT::i32);
}]>; }]>;
// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
MVT::i32);
}]>; }]>;
// so_imm_notSext_XFORM - Return a so_imm value packed into the format // so_imm_notSext_XFORM - Return a so_imm value packed into the format
@ -70,7 +68,7 @@ def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{ def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
APInt apIntN = N->getAPIntValue(); APInt apIntN = N->getAPIntValue();
unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
}]>; }]>;
// t2_so_imm - Match a 32-bit immediate operand, which is an // t2_so_imm - Match a 32-bit immediate operand, which is an

4
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -37,7 +37,7 @@ def vfp_f32imm : Operand<f32>,
}], SDNodeXForm<fpimm, [{ }], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF(); APFloat InVal = N->getValueAPF();
uint32_t enc = ARM_AM::getFP32Imm(InVal); uint32_t enc = ARM_AM::getFP32Imm(InVal);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> { }]>> {
let PrintMethod = "printFPImmOperand"; let PrintMethod = "printFPImmOperand";
let ParserMatchClass = FPImmOperand; let ParserMatchClass = FPImmOperand;
@ -49,7 +49,7 @@ def vfp_f64imm : Operand<f64>,
}], SDNodeXForm<fpimm, [{ }], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF(); APFloat InVal = N->getValueAPF();
uint32_t enc = ARM_AM::getFP64Imm(InVal); uint32_t enc = ARM_AM::getFP64Imm(InVal);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> { }]>> {
let PrintMethod = "printFPImmOperand"; let PrintMethod = "printFPImmOperand";
let ParserMatchClass = FPImmOperand; let ParserMatchClass = FPImmOperand;

8
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
View File

@ -67,7 +67,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Loads[i] = DAG.getLoad(VT, dl, Chain, Loads[i] = DAG.getLoad(VT, dl, Chain,
DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
DAG.getConstant(SrcOff, dl, MVT::i32)), DAG.getConstant(SrcOff, MVT::i32)),
SrcPtrInfo.getWithOffset(SrcOff), isVolatile, SrcPtrInfo.getWithOffset(SrcOff), isVolatile,
false, false, 0); false, false, 0);
TFOps[i] = Loads[i].getValue(1); TFOps[i] = Loads[i].getValue(1);
@ -80,7 +80,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
TFOps[i] = DAG.getStore(Chain, dl, Loads[i], TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
DAG.getConstant(DstOff, dl, MVT::i32)), DAG.getConstant(DstOff, MVT::i32)),
DstPtrInfo.getWithOffset(DstOff), DstPtrInfo.getWithOffset(DstOff),
isVolatile, false, 0); isVolatile, false, 0);
DstOff += VTSize; DstOff += VTSize;
@ -108,7 +108,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
Loads[i] = DAG.getLoad(VT, dl, Chain, Loads[i] = DAG.getLoad(VT, dl, Chain,
DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
DAG.getConstant(SrcOff, dl, MVT::i32)), DAG.getConstant(SrcOff, MVT::i32)),
SrcPtrInfo.getWithOffset(SrcOff), SrcPtrInfo.getWithOffset(SrcOff),
false, false, false, 0); false, false, false, 0);
TFOps[i] = Loads[i].getValue(1); TFOps[i] = Loads[i].getValue(1);
@ -132,7 +132,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
TFOps[i] = DAG.getStore(Chain, dl, Loads[i], TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
DAG.getConstant(DstOff, dl, MVT::i32)), DAG.getConstant(DstOff, MVT::i32)),
DstPtrInfo.getWithOffset(DstOff), false, false, 0); DstPtrInfo.getWithOffset(DstOff), false, false, 0);
++i; ++i;
DstOff += VTSize; DstOff += VTSize;

98
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -108,24 +108,24 @@ public:
// XformMskToBitPosU5Imm - Returns the bit position which // XformMskToBitPosU5Imm - Returns the bit position which
// the single bit 32 bit mask represents. // the single bit 32 bit mask represents.
// Used in Clr and Set bit immediate memops. // Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) { SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
int32_t bitPos; int32_t bitPos;
bitPos = Log2_32(Imm); bitPos = Log2_32(Imm);
assert(bitPos >= 0 && bitPos < 32 && assert(bitPos >= 0 && bitPos < 32 &&
"Constant out of range for 32 BitPos Memops"); "Constant out of range for 32 BitPos Memops");
return CurDAG->getTargetConstant(bitPos, DL, MVT::i32); return CurDAG->getTargetConstant(bitPos, MVT::i32);
} }
// XformMskToBitPosU4Imm - Returns the bit position which the single-bit // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
// 16 bit mask represents. Used in Clr and Set bit immediate memops. // 16 bit mask represents. Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) { SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
return XformMskToBitPosU5Imm(Imm, DL); return XformMskToBitPosU5Imm(Imm);
} }
// XformMskToBitPosU3Imm - Returns the bit position which the single-bit // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
// 8 bit mask represents. Used in Clr and Set bit immediate memops. // 8 bit mask represents. Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) { SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
return XformMskToBitPosU5Imm(Imm, DL); return XformMskToBitPosU5Imm(Imm);
} }
// Return true if there is exactly one bit set in V, i.e., if V is one of the // Return true if there is exactly one bit set in V, i.e., if V is one of the
@ -137,37 +137,37 @@ public:
// XformM5ToU5Imm - Return a target constant with the specified value, of // XformM5ToU5Imm - Return a target constant with the specified value, of
// type i32 where the negative literal is transformed into a positive literal // type i32 where the negative literal is transformed into a positive literal
// for use in -= memops. // for use in -= memops.
inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) { inline SDValue XformM5ToU5Imm(signed Imm) {
assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops"); assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
return CurDAG->getTargetConstant( - Imm, DL, MVT::i32); return CurDAG->getTargetConstant( - Imm, MVT::i32);
} }
// XformU7ToU7M1Imm - Return a target constant decremented by 1, in range // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
// [1..128], used in cmpb.gtu instructions. // [1..128], used in cmpb.gtu instructions.
inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) { inline SDValue XformU7ToU7M1Imm(signed Imm) {
assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op"); assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8); return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
} }
// XformS8ToS8M1Imm - Return a target constant decremented by 1. // XformS8ToS8M1Imm - Return a target constant decremented by 1.
inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) { inline SDValue XformSToSM1Imm(signed Imm) {
return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32); return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
} }
// XformU8ToU8M1Imm - Return a target constant decremented by 1. // XformU8ToU8M1Imm - Return a target constant decremented by 1.
inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) { inline SDValue XformUToUM1Imm(unsigned Imm) {
assert((Imm >= 1) && "Cannot decrement unsigned int less than 1"); assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32); return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
} }
// XformSToSM2Imm - Return a target constant decremented by 2. // XformSToSM2Imm - Return a target constant decremented by 2.
inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) { inline SDValue XformSToSM2Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32); return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
} }
// XformSToSM3Imm - Return a target constant decremented by 3. // XformSToSM3Imm - Return a target constant decremented by 3.
inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) { inline SDValue XformSToSM3Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32); return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
@ -259,7 +259,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
const HexagonInstrInfo &TII = *HST->getInstrInfo(); const HexagonInstrInfo &TII = *HST->getInstrInfo();
if (TII.isValidAutoIncImm(LoadedVT, Val)) { if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
MVT::Other, Base, TargetConst, MVT::Other, Base, TargetConst,
Chain); Chain);
@ -278,8 +278,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
return Result_2; return Result_2;
} }
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
Base, TargetConst0, Chain); Base, TargetConst0, Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64, SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
@ -313,8 +313,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
const HexagonInstrInfo &TII = *HST->getInstrInfo(); const HexagonInstrInfo &TII = *HST->getInstrInfo();
if (TII.isValidAutoIncImm(LoadedVT, Val)) { if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::i32, MVT::Other, Base, MVT::i32, MVT::Other, Base,
TargetConstVal, Chain); TargetConstVal, Chain);
@ -336,8 +336,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
} }
// Generate an indirect load. // Generate an indirect load.
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, Base, TargetConst0, MVT::Other, Base, TargetConst0,
Chain); Chain);
@ -411,7 +411,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
return SelectIndexedLoadSignExtend64(LD, Opcode, dl); return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
if (TII.isValidAutoIncImm(LoadedVT, Val)) { if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
LD->getValueType(0), LD->getValueType(0),
MVT::i32, MVT::Other, Base, MVT::i32, MVT::Other, Base,
@ -430,8 +430,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
ReplaceUses(Froms, Tos, 3); ReplaceUses(Froms, Tos, 3);
return Result; return Result;
} else { } else {
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
LD->getValueType(0), LD->getValueType(0),
MVT::Other, Base, TargetConst0, MVT::Other, Base, TargetConst0,
@ -502,7 +502,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
dl, MVT::i32, Value); dl, MVT::i32, Value);
} }
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value, SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
Chain}; Chain};
// Build post increment store. // Build post increment store.
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32, SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
@ -520,7 +520,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
// def S2_storerd_io // def S2_storerd_io
// : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ... // : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
// and it differs for POST_ST* for instance. // and it differs for POST_ST* for instance.
SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value, SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
Chain}; Chain};
unsigned Opcode = 0; unsigned Opcode = 0;
@ -532,7 +532,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
else llvm_unreachable("unknown memory type"); else llvm_unreachable("unknown memory type");
// Build regular store. // Build regular store.
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
// Build splitted incriment instruction. // Build splitted incriment instruction.
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32, SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
@ -599,7 +599,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
} }
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), TargetConst0, LD->getBasePtr(), TargetConst0,
@ -625,7 +625,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
} }
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), TargetConst0, LD->getBasePtr(), TargetConst0,
@ -661,7 +661,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
int32_t MulConst = int32_t MulConst =
cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue(); cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
int32_t ValConst = MulConst << ShlConst; int32_t ValConst = MulConst << ShlConst;
SDValue Val = CurDAG->getTargetConstant(ValConst, dl, SDValue Val = CurDAG->getTargetConstant(ValConst,
MVT::i32); MVT::i32);
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode())) if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
if (isInt<9>(CN->getSExtValue())) { if (isInt<9>(CN->getSExtValue())) {
@ -689,8 +689,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
int32_t Shl2Const = int32_t Shl2Const =
cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue(); cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
int32_t ValConst = 1 << (ShlConst+Shl2Const); int32_t ValConst = 1 << (ShlConst+Shl2Const);
SDValue Val = CurDAG->getTargetConstant(-ValConst, dl, SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
MVT::i32);
if (ConstantSDNode *CN = if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(Val.getNode())) dyn_cast<ConstantSDNode>(Val.getNode()))
if (isInt<9>(CN->getSExtValue())) { if (isInt<9>(CN->getSExtValue())) {
@ -739,14 +738,13 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
MV |= Bit; MV |= Bit;
Bit <<= ES; Bit <<= ES;
} }
SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64); SDValue Ones = CurDAG->getTargetConstant(MV, MVT::i64);
SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl, SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
MVT::i64, Ones); MVT::i64, Ones);
if (ExVT.getSizeInBits() == 32) { if (ExVT.getSizeInBits() == 32) {
SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64, SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
SDValue(Mask,0), SDValue(OnesReg,0)); SDValue(Mask,0), SDValue(OnesReg,0));
SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl, SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, MVT::i32);
MVT::i32);
return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT, return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
SDValue(And,0), SubR); SDValue(And,0), SubR);
} }
@ -762,7 +760,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
// Now we need to differentiate target data types. // Now we need to differentiate target data types.
if (N->getValueType(0) == MVT::i64) { if (N->getValueType(0) == MVT::i64) {
// Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs). // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl, SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
MVT::i32, MVT::i32,
SDValue(IsIntrinsic, 0)); SDValue(IsIntrinsic, 0));
@ -869,7 +867,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
Ops.push_back(Load); Ops.push_back(Load);
Ops.push_back(ModifierExpr); Ops.push_back(ModifierExpr);
int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(Val, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops); SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
@ -1024,11 +1022,11 @@ SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
APFloat APF = CN->getValueAPF(); APFloat APF = CN->getValueAPF();
if (N->getValueType(0) == MVT::f32) { if (N->getValueType(0) == MVT::f32) {
return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32, return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32)); CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
} }
else if (N->getValueType(0) == MVT::f64) { else if (N->getValueType(0) == MVT::f64) {
return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64, return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64)); CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
} }
return SelectCode(N); return SelectCode(N);
@ -1168,7 +1166,7 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
SDNode *Result; SDNode *Result;
// Get the right SDVal for the opcode. // Get the right SDVal for the opcode.
SDValue SDVal = CurDAG->getTargetConstant(bitpos, dl, MVT::i32); SDValue SDVal = CurDAG->getTargetConstant(bitpos, MVT::i32);
if (ValueVT == MVT::i32 || ValueVT == MVT::f32) { if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT, Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
@ -1183,11 +1181,11 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
SDNode *Reg = N->getOperand(0).getNode(); SDNode *Reg = N->getOperand(0).getNode();
SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
dl, MVT::i64); MVT::i64);
SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl, SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg,
MVT::i32); MVT::i32);
SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl, SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg,
MVT::i32); MVT::i32);
SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl, SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
@ -1206,7 +1204,7 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
dl, ValueVT, Ops); dl, ValueVT, Ops);
} else { } else {
if (Opc != ISD::FABS && Opc != ISD::FNEG) if (Opc != ISD::FABS && Opc != ISD::FNEG)
SDVal = CurDAG->getTargetConstant(bitpos - 32, dl, MVT::i32); SDVal = CurDAG->getTargetConstant(bitpos-32, MVT::i32);
SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT, SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
SubregHI, SDVal); SubregHI, SDVal);
const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx, const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
@ -1228,8 +1226,8 @@ SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
unsigned StkA = HFI->getStackAlignment(); unsigned StkA = HFI->getStackAlignment();
unsigned MaxA = MFI->getMaxAlignment(); unsigned MaxA = MFI->getMaxAlignment();
SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32); SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
SDLoc DL(N); SDLoc DL(N);
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
SDNode *R = 0; SDNode *R = 0;
// Use TFR_FI when: // Use TFR_FI when:
@ -1323,7 +1321,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
break; break;
} }
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
} }

77
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -344,7 +344,7 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG, ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
SDLoc dl) { SDLoc dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*isVolatile=*/false, /*AlwaysInline=*/false, /*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false, /*isTailCall=*/false,
@ -542,8 +542,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (VA.isMemLoc()) { if (VA.isMemLoc()) {
unsigned LocMemOffset = VA.getLocMemOffset(); unsigned LocMemOffset = VA.getLocMemOffset();
SDValue MemAddr = DAG.getConstant(LocMemOffset, dl, SDValue MemAddr = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
StackPtr.getValueType());
MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
if (Flags.isByVal()) { if (Flags.isByVal()) {
// The argument is a struct passed by value. According to LLVM, "Arg" // The argument is a struct passed by value. According to LLVM, "Arg"
@ -571,7 +570,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
if (!isTailCall) { if (!isTailCall) {
SDValue C = DAG.getConstant(NumBytes, dl, getPointerTy(), true); SDValue C = DAG.getConstant(NumBytes, getPointerTy(), true);
Chain = DAG.getCALLSEQ_START(Chain, C, dl); Chain = DAG.getCALLSEQ_START(Chain, C, dl);
} }
@ -645,8 +644,8 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node. // Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true), Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
DAG.getIntPtrConstant(0, dl, true), InFlag, dl); DAG.getIntPtrConstant(0, true), InFlag, dl);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we // Handle result values, copying them out of physregs into vregs that we
@ -809,7 +808,7 @@ LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl, SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl,
getPointerTy(), TargetJT); getPointerTy(), TargetJT);
SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
DAG.getConstant(2, dl, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
ShiftIndex); ShiftIndex);
SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
@ -842,7 +841,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
dbgs() << "\n"; dbgs() << "\n";
}); });
SDValue AC = DAG.getConstant(A, dl, MVT::i32); SDValue AC = DAG.getConstant(A, MVT::i32);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC); return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
} }
@ -995,7 +994,7 @@ SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
SDValue InpVal = Op.getOperand(0); SDValue InpVal = Op.getOperand(0);
if (isa<ConstantSDNode>(InpVal)) { if (isa<ConstantSDNode>(InpVal)) {
uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue(); uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64); return DAG.getTargetConstant(countPopulation(V), MVT::i64);
} }
SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal); SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut); return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
@ -1096,7 +1095,7 @@ SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadNode->isInvariant(), LoadNode->isInvariant(),
Alignment); Alignment);
// Base+2 load. // Base+2 load.
SDValue Increment = DAG.getConstant(2, DL, MVT::i32); SDValue Increment = DAG.getConstant(2, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment); Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr, Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16, LoadNode->getPointerInfo(), MVT::i16,
@ -1105,11 +1104,11 @@ SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadNode->isInvariant(), LoadNode->isInvariant(),
Alignment); Alignment);
// SHL 16, then OR base and base+2. // SHL 16, then OR base and base+2.
SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32); SDValue ShiftAmount = DAG.getConstant(16, MVT::i32);
SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]); SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
// Base + 4. // Base + 4.
Increment = DAG.getConstant(4, DL, MVT::i32); Increment = DAG.getConstant(4, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment); Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr, Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16, LoadNode->getPointerInfo(), MVT::i16,
@ -1118,7 +1117,7 @@ SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadNode->isInvariant(), LoadNode->isInvariant(),
Alignment); Alignment);
// Base + 6. // Base + 6.
Increment = DAG.getConstant(6, DL, MVT::i32); Increment = DAG.getConstant(6, MVT::i32);
Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment); Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr, Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
LoadNode->getPointerInfo(), MVT::i16, LoadNode->getPointerInfo(), MVT::i16,
@ -1184,7 +1183,7 @@ HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
if (Depth) { if (Depth) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset = DAG.getConstant(4, dl, MVT::i32); SDValue Offset = DAG.getConstant(4, MVT::i32);
return DAG.getLoad(VT, dl, DAG.getEntryNode(), return DAG.getLoad(VT, dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
@ -1823,7 +1822,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (IsScalarToVector) if (IsScalarToVector)
return createSplat(DAG, dl, VT, V1.getOperand(0)); return createSplat(DAG, dl, VT, V1.getOperand(0));
} }
return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32)); return createSplat(DAG, dl, VT, DAG.getConstant(Lane, MVT::i32));
} }
// FIXME: We need to support more general vector shuffles. See // FIXME: We need to support more general vector shuffles. See
@ -1931,7 +1930,7 @@ HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
unsigned SplatBits = APSplatBits.getZExtValue(); unsigned SplatBits = APSplatBits.getZExtValue();
int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >> int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
(32 - SplatBitSize)); (32 - SplatBitSize));
return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32)); return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, MVT::i32));
} }
// Try to generate COMBINE to build v2i32 vectors. // Try to generate COMBINE to build v2i32 vectors.
@ -1940,9 +1939,9 @@ HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
SDValue V1 = BVN->getOperand(1); SDValue V1 = BVN->getOperand(1);
if (V0.getOpcode() == ISD::UNDEF) if (V0.getOpcode() == ISD::UNDEF)
V0 = DAG.getConstant(0, dl, MVT::i32); V0 = DAG.getConstant(0, MVT::i32);
if (V1.getOpcode() == ISD::UNDEF) if (V1.getOpcode() == ISD::UNDEF)
V1 = DAG.getConstant(0, dl, MVT::i32); V1 = DAG.getConstant(0, MVT::i32);
ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0); ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1); ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
@ -2003,17 +2002,17 @@ HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
} }
if (Size == 64) if (Size == 64)
ConstVal = DAG.getConstant(Res, dl, MVT::i64); ConstVal = DAG.getConstant(Res, MVT::i64);
else else
ConstVal = DAG.getConstant(Res, dl, MVT::i32); ConstVal = DAG.getConstant(Res, MVT::i32);
// When there are non constant operands, add them with INSERT_VECTOR_ELT to // When there are non constant operands, add them with INSERT_VECTOR_ELT to
// ConstVal, the constant part of the vector. // ConstVal, the constant part of the vector.
if (HasNonConstantElements) { if (HasNonConstantElements) {
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64); SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), MVT::i64);
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
for (unsigned i = 0, e = NElts; i != e; ++i) { for (unsigned i = 0, e = NElts; i != e; ++i) {
// LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
@ -2026,11 +2025,11 @@ HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (VT.getSizeInBits() == 64 && if (VT.getSizeInBits() == 64 &&
Operand.getValueType().getSizeInBits() == 32) { Operand.getValueType().getSizeInBits() == 32) {
SDValue C = DAG.getConstant(0, dl, MVT::i32); SDValue C = DAG.getConstant(0, MVT::i32);
Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand); Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
} }
SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64); SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width); SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {ConstVal, Operand, Combined}; const SDValue Ops[] = {ConstVal, Operand, Combined};
@ -2053,10 +2052,10 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
unsigned NElts = Op.getNumOperands(); unsigned NElts = Op.getNumOperands();
SDValue Vec = Op.getOperand(0); SDValue Vec = Op.getOperand(0);
EVT VecVT = Vec.getValueType(); EVT VecVT = Vec.getValueType();
SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), dl, MVT::i64); SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), MVT::i64);
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue ConstVal = DAG.getConstant(0, dl, MVT::i64); SDValue ConstVal = DAG.getConstant(0, MVT::i64);
ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width); ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted); ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
@ -2085,11 +2084,11 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
if (VT.getSizeInBits() == 64 && if (VT.getSizeInBits() == 64 &&
Operand.getValueType().getSizeInBits() == 32) { Operand.getValueType().getSizeInBits() == 32) {
SDValue C = DAG.getConstant(0, dl, MVT::i32); SDValue C = DAG.getConstant(0, MVT::i32);
Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand); Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
} }
SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64); SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width); SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {ConstVal, Operand, Combined}; const SDValue Ops[] = {ConstVal, Operand, Combined};
@ -2115,12 +2114,12 @@ HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
EVT EltVT = VecVT.getVectorElementType(); EVT EltVT = VecVT.getVectorElementType();
int EltSize = EltVT.getSizeInBits(); int EltSize = EltVT.getSizeInBits();
SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ? SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
EltSize : VTN * EltSize, dl, MVT::i64); EltSize : VTN * EltSize, MVT::i64);
// Constant element number. // Constant element number.
if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) { if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
uint64_t X = CI->getZExtValue(); uint64_t X = CI->getZExtValue();
SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32); SDValue Offset = DAG.getConstant(X * EltSize, MVT::i32);
const SDValue Ops[] = {Vec, Width, Offset}; const SDValue Ops[] = {Vec, Width, Offset};
ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width); ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
@ -2159,9 +2158,9 @@ HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
// Variable element number. // Variable element number.
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx, SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
DAG.getConstant(EltSize, dl, MVT::i32)); DAG.getConstant(EltSize, MVT::i32));
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
const SDValue Ops[] = {Vec, Combined}; const SDValue Ops[] = {Vec, Combined};
@ -2190,10 +2189,10 @@ HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
EVT EltVT = VecVT.getVectorElementType(); EVT EltVT = VecVT.getVectorElementType();
int EltSize = EltVT.getSizeInBits(); int EltSize = EltVT.getSizeInBits();
SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ? SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
EltSize : VTN * EltSize, dl, MVT::i64); EltSize : VTN * EltSize, MVT::i64);
if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) { if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32); SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, MVT::i32);
const SDValue Ops[] = {Vec, Val, Width, Offset}; const SDValue Ops[] = {Vec, Val, Width, Offset};
SDValue N; SDValue N;
@ -2207,14 +2206,14 @@ HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
// Variable element number. // Variable element number.
SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx, SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
DAG.getConstant(EltSize, dl, MVT::i32)); DAG.getConstant(EltSize, MVT::i32));
SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
if (VT.getSizeInBits() == 64 && if (VT.getSizeInBits() == 64 &&
Val.getValueType().getSizeInBits() == 32) { Val.getValueType().getSizeInBits() == 32) {
SDValue C = DAG.getConstant(0, dl, MVT::i32); SDValue C = DAG.getConstant(0, MVT::i32);
Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val); Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
} }
@ -2258,7 +2257,7 @@ HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
DAG.getRegister(Hexagon::R30, getPointerTy()), DAG.getRegister(Hexagon::R30, getPointerTy()),
DAG.getIntPtrConstant(4, dl)); DAG.getIntPtrConstant(4));
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
false, false, 0); false, false, 0);
Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);

8
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -36,28 +36,28 @@ def HiReg: OutPatFrag<(ops node:$Rs),
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{ def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode. // Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformSToSM1Imm(imm, SDLoc(N)); return XformSToSM1Imm(imm);
}]>; }]>;
// SDNode for converting immediate C to C-2. // SDNode for converting immediate C to C-2.
def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{ def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-2 as an SDNode. // Return the byte immediate const-2 as an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformSToSM2Imm(imm, SDLoc(N)); return XformSToSM2Imm(imm);
}]>; }]>;
// SDNode for converting immediate C to C-3. // SDNode for converting immediate C to C-3.
def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{ def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-3 as an SDNode. // Return the byte immediate const-3 as an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformSToSM3Imm(imm, SDLoc(N)); return XformSToSM3Imm(imm);
}]>; }]>;
// SDNode for converting immediate C to C-1. // SDNode for converting immediate C to C-1.
def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{ def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode. // Return the byte immediate const-1 as an SDNode.
uint32_t imm = N->getZExtValue(); uint32_t imm = N->getZExtValue();
return XformUToUM1Imm(imm, SDLoc(N)); return XformUToUM1Imm(imm);
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

28
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -57,7 +57,7 @@ def BITPOS32 : SDNodeXForm<imm, [{
// Return the bit position we will set [0-31]. // Return the bit position we will set [0-31].
// As an SDNode. // As an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformMskToBitPosU5Imm(imm, SDLoc(N)); return XformMskToBitPosU5Imm(imm);
}]>; }]>;
@ -1153,14 +1153,14 @@ def IMM_BYTE : SDNodeXForm<imm, [{
// -1 etc is represented as 255 etc // -1 etc is represented as 255 etc
// assigning to a byte restores our desired signed value. // assigning to a byte restores our desired signed value.
int8_t imm = N->getSExtValue(); int8_t imm = N->getSExtValue();
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(imm, MVT::i32);
}]>; }]>;
def IMM_HALF : SDNodeXForm<imm, [{ def IMM_HALF : SDNodeXForm<imm, [{
// -1 etc is represented as 65535 etc // -1 etc is represented as 65535 etc
// assigning to a short restores our desired signed value. // assigning to a short restores our desired signed value.
int16_t imm = N->getSExtValue(); int16_t imm = N->getSExtValue();
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(imm, MVT::i32);
}]>; }]>;
def IMM_WORD : SDNodeXForm<imm, [{ def IMM_WORD : SDNodeXForm<imm, [{
@ -1169,7 +1169,7 @@ def IMM_WORD : SDNodeXForm<imm, [{
// might convert -1 to a large +ve number. // might convert -1 to a large +ve number.
// assigning to a word restores our desired signed value. // assigning to a word restores our desired signed value.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(imm, MVT::i32);
}]>; }]>;
def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
@ -2805,7 +2805,7 @@ def MEMOPIMM : SDNodeXForm<imm, [{
// Call the transformation function XformM5ToU5Imm to get the negative // Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart. // immediate's positive counterpart.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformM5ToU5Imm(imm, SDLoc(N)); return XformM5ToU5Imm(imm);
}]>; }]>;
def MEMOPIMM_HALF : SDNodeXForm<imm, [{ def MEMOPIMM_HALF : SDNodeXForm<imm, [{
@ -2814,7 +2814,7 @@ def MEMOPIMM_HALF : SDNodeXForm<imm, [{
// Call the transformation function XformM5ToU5Imm to get the negative // Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart. // immediate's positive counterpart.
int16_t imm = N->getSExtValue(); int16_t imm = N->getSExtValue();
return XformM5ToU5Imm(imm, SDLoc(N)); return XformM5ToU5Imm(imm);
}]>; }]>;
def MEMOPIMM_BYTE : SDNodeXForm<imm, [{ def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
@ -2823,14 +2823,14 @@ def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
// Call the transformation function XformM5ToU5Imm to get the negative // Call the transformation function XformM5ToU5Imm to get the negative
// immediate's positive counterpart. // immediate's positive counterpart.
int8_t imm = N->getSExtValue(); int8_t imm = N->getSExtValue();
return XformM5ToU5Imm(imm, SDLoc(N)); return XformM5ToU5Imm(imm);
}]>; }]>;
def SETMEMIMM : SDNodeXForm<imm, [{ def SETMEMIMM : SDNodeXForm<imm, [{
// Return the bit position we will set [0-31]. // Return the bit position we will set [0-31].
// As an SDNode. // As an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformMskToBitPosU5Imm(imm, SDLoc(N)); return XformMskToBitPosU5Imm(imm);
}]>; }]>;
def CLRMEMIMM : SDNodeXForm<imm, [{ def CLRMEMIMM : SDNodeXForm<imm, [{
@ -2838,14 +2838,14 @@ def CLRMEMIMM : SDNodeXForm<imm, [{
// As an SDNode. // As an SDNode.
// we bit negate the value first // we bit negate the value first
int32_t imm = ~(N->getSExtValue()); int32_t imm = ~(N->getSExtValue());
return XformMskToBitPosU5Imm(imm, SDLoc(N)); return XformMskToBitPosU5Imm(imm);
}]>; }]>;
def SETMEMIMM_SHORT : SDNodeXForm<imm, [{ def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
// Return the bit position we will set [0-15]. // Return the bit position we will set [0-15].
// As an SDNode. // As an SDNode.
int16_t imm = N->getSExtValue(); int16_t imm = N->getSExtValue();
return XformMskToBitPosU4Imm(imm, SDLoc(N)); return XformMskToBitPosU4Imm(imm);
}]>; }]>;
def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{ def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
@ -2853,14 +2853,14 @@ def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
// As an SDNode. // As an SDNode.
// we bit negate the value first // we bit negate the value first
int16_t imm = ~(N->getSExtValue()); int16_t imm = ~(N->getSExtValue());
return XformMskToBitPosU4Imm(imm, SDLoc(N)); return XformMskToBitPosU4Imm(imm);
}]>; }]>;
def SETMEMIMM_BYTE : SDNodeXForm<imm, [{ def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
// Return the bit position we will set [0-7]. // Return the bit position we will set [0-7].
// As an SDNode. // As an SDNode.
int8_t imm = N->getSExtValue(); int8_t imm = N->getSExtValue();
return XformMskToBitPosU3Imm(imm, SDLoc(N)); return XformMskToBitPosU3Imm(imm);
}]>; }]>;
def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{ def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
@ -2868,7 +2868,7 @@ def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
// As an SDNode. // As an SDNode.
// we bit negate the value first // we bit negate the value first
int8_t imm = ~(N->getSExtValue()); int8_t imm = ~(N->getSExtValue());
return XformMskToBitPosU3Imm(imm, SDLoc(N)); return XformMskToBitPosU3Imm(imm);
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -3202,7 +3202,7 @@ def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
def DEC_CONST_BYTE : SDNodeXForm<imm, [{ def DEC_CONST_BYTE : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode. // Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue(); int32_t imm = N->getSExtValue();
return XformU7ToU7M1Imm(imm, SDLoc(N)); return XformU7ToU7M1Imm(imm);
}]>; }]>;
// For the sequence // For the sequence

10
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -274,7 +274,7 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0, Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
0/*AM.SymbolFlags*/); 0/*AM.SymbolFlags*/);
else else
Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16); Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
return true; return true;
} }
@ -401,10 +401,10 @@ SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
int FI = cast<FrameIndexSDNode>(Node)->getIndex(); int FI = cast<FrameIndexSDNode>(Node)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16); SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
if (Node->hasOneUse()) if (Node->hasOneUse())
return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, TFI, return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
CurDAG->getTargetConstant(0, dl, MVT::i16)); TFI, CurDAG->getTargetConstant(0, MVT::i16));
return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16, TFI, return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
CurDAG->getTargetConstant(0, dl, MVT::i16)); TFI, CurDAG->getTargetConstant(0, MVT::i16));
} }
case ISD::LOAD: case ISD::LOAD:
if (SDNode *ResNode = SelectIndexedLoad(Node)) if (SDNode *ResNode = SelectIndexedLoad(Node))

30
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -593,7 +593,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
// Get a count of how many bytes are to be pushed on the stack. // Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset(); unsigned NumBytes = CCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, dl, Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
getPointerTy(), true), getPointerTy(), true),
dl); dl);
@ -634,14 +634,13 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
StackPtr, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DAG.getIntPtrConstant(VA.getLocMemOffset()));
dl));
SDValue MemOp; SDValue MemOp;
ISD::ArgFlagsTy Flags = Outs[i].Flags; ISD::ArgFlagsTy Flags = Outs[i].Flags;
if (Flags.isByVal()) { if (Flags.isByVal()) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
Flags.getByValAlign(), Flags.getByValAlign(),
/*isVolatile*/false, /*isVolatile*/false,
@ -701,9 +700,8 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
// Create the CALLSEQ_END node. // Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, dl, getPointerTy(), DAG.getConstant(NumBytes, getPointerTy(), true),
true), DAG.getConstant(0, getPointerTy(), true),
DAG.getConstant(0, dl, getPointerTy(), true),
InFlag, dl); InFlag, dl);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -845,7 +843,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
// fold constant into instruction. // fold constant into instruction.
if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
LHS = RHS; LHS = RHS;
RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
TCC = MSP430CC::COND_LO; TCC = MSP430CC::COND_LO;
break; break;
} }
@ -858,7 +856,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
// fold constant into instruction. // fold constant into instruction.
if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
LHS = RHS; LHS = RHS;
RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
TCC = MSP430CC::COND_HS; TCC = MSP430CC::COND_HS;
break; break;
} }
@ -871,7 +869,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
// fold constant into instruction. // fold constant into instruction.
if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
LHS = RHS; LHS = RHS;
RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
TCC = MSP430CC::COND_L; TCC = MSP430CC::COND_L;
break; break;
} }
@ -884,7 +882,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
// fold constant into instruction. // fold constant into instruction.
if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
LHS = RHS; LHS = RHS;
RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
TCC = MSP430CC::COND_GE; TCC = MSP430CC::COND_GE;
break; break;
} }
@ -892,7 +890,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
break; break;
} }
TargetCC = DAG.getConstant(TCC, dl, MVT::i8); TargetCC = DAG.getConstant(TCC, MVT::i8);
return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
} }
@ -969,7 +967,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
break; break;
} }
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue One = DAG.getConstant(1, dl, VT); SDValue One = DAG.getConstant(1, VT);
if (Convert) { if (Convert) {
SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
MVT::i16, Flag); MVT::i16, Flag);
@ -981,7 +979,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
return SR; return SR;
} else { } else {
SDValue Zero = DAG.getConstant(0, dl, VT); SDValue Zero = DAG.getConstant(0, VT);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {One, Zero, TargetCC, Flag}; SDValue Ops[] = {One, Zero, TargetCC, Flag};
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
@ -1050,7 +1048,7 @@ SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
if (Depth > 0) { if (Depth > 0) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset = SDValue Offset =
DAG.getConstant(getDataLayout()->getPointerSize(), dl, MVT::i16); DAG.getConstant(getDataLayout()->getPointerSize(), MVT::i16);
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, getPointerTy(), DAG.getNode(ISD::ADD, dl, getPointerTy(),
FrameAddr, Offset), FrameAddr, Offset),
@ -1131,7 +1129,7 @@ bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
return false; return false;
Base = Op->getOperand(0); Base = Op->getOperand(0);
Offset = DAG.getConstant(RHSC, SDLoc(N), VT); Offset = DAG.getConstant(RHSC, VT);
AM = ISD::POST_INC; AM = ISD::POST_INC;
return true; return true;
} }

9
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
View File

@ -163,15 +163,14 @@ void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
bool Mips16DAGToDAGISel::selectAddr16( bool Mips16DAGToDAGISel::selectAddr16(
SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset, SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
SDValue &Alias) { SDValue &Alias) {
SDLoc DL(Addr);
EVT ValTy = Addr.getValueType(); EVT ValTy = Addr.getValueType();
Alias = CurDAG->getTargetConstant(0, DL, ValTy); Alias = CurDAG->getTargetConstant(0, ValTy);
// if Address is FI, get the TargetFrameIndex. // if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
Offset = CurDAG->getTargetConstant(0, DL, ValTy); Offset = CurDAG->getTargetConstant(0, ValTy);
getMips16SPRefReg(Parent, Alias); getMips16SPRefReg(Parent, Alias);
return true; return true;
} }
@ -200,7 +199,7 @@ bool Mips16DAGToDAGISel::selectAddr16(
else else
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), DL, ValTy); Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
return true; return true;
} }
} }
@ -236,7 +235,7 @@ bool Mips16DAGToDAGISel::selectAddr16(
} }
} }
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, DL, ValTy); Offset = CurDAG->getTargetConstant(0, ValTy);
return true; return true;
} }

2
llvm/lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -119,7 +119,7 @@ private:
// getImm - Return a target constant with the specified value. // getImm - Return a target constant with the specified value.
inline SDValue getImm(const SDNode *Node, uint64_t Imm) { inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
} }
virtual void processFunctionAfterISel(MachineFunction &MF) = 0; virtual void processFunctionAfterISel(MachineFunction &MF) = 0;

140
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -544,7 +544,7 @@ static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); DAG.getConstant(condCodeToFCC(CC), MVT::i32));
} }
// Creates and returns a CMovFPT/F node. // Creates and returns a CMovFPT/F node.
@ -699,11 +699,9 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
return SDValue(); return SDValue();
SDLoc DL(N); return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
return DAG.getNode(MipsISD::Ext, DL, ValTy, ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
ShiftRight.getOperand(0), DAG.getConstant(SMSize, MVT::i32));
DAG.getConstant(Pos, DL, MVT::i32),
DAG.getConstant(SMSize, DL, MVT::i32));
} }
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
@ -755,11 +753,9 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
return SDValue(); return SDValue();
SDLoc DL(N); return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), DAG.getConstant(SMPos0, MVT::i32),
DAG.getConstant(SMPos0, DL, MVT::i32), DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
DAG.getConstant(SMSize0, DL, MVT::i32),
And0.getOperand(0));
} }
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
@ -1560,7 +1556,7 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
Index = DAG.getNode(ISD::MUL, DL, PTy, Index, Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
DAG.getConstant(EntrySize, DL, PTy)); DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
@ -1598,7 +1594,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
Mips::CondCode CC = Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
FCC0, Dest, CondRes); FCC0, Dest, CondRes);
@ -1639,11 +1635,10 @@ SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
assert(Cond.getOpcode() == MipsISD::FPCmp && assert(Cond.getOpcode() == MipsISD::FPCmp &&
"Floating point operand expected."); "Floating point operand expected.");
SDLoc DL(Op); SDValue True = DAG.getConstant(1, MVT::i32);
SDValue True = DAG.getConstant(1, DL, MVT::i32); SDValue False = DAG.getConstant(0, MVT::i32);
SDValue False = DAG.getConstant(0, DL, MVT::i32);
return createCMovFP(DAG, Cond, True, False, DL); return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
} }
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
@ -1842,19 +1837,19 @@ SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
DAG.getConstant(Align - 1, DL, VAList.getValueType())); DAG.getConstant(Align - 1,
VAList.getValueType()));
VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
DAG.getConstant(-(int64_t)Align, DL, DAG.getConstant(-(int64_t)Align,
VAList.getValueType())); VAList.getValueType()));
} }
// Increment the pointer, VAList, to the next vaarg. // Increment the pointer, VAList, to the next vaarg.
unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
ArgSlotSizeInBytes), VAList.getValueType()));
DL, VAList.getValueType()));
// Store the incremented VAList to the legalized pointer // Store the incremented VAList to the legalized pointer
Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
MachinePointerInfo(SV), false, false, 0); MachinePointerInfo(SV), false, false, 0);
@ -1867,7 +1862,7 @@ SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
DAG.getIntPtrConstant(Adjustment, DL)); DAG.getIntPtrConstant(Adjustment));
} }
// Load the actual argument out of the pointer VAList // Load the actual argument out of the pointer VAList
return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false, return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
@ -1878,9 +1873,9 @@ static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
bool HasExtractInsert) { bool HasExtractInsert) {
EVT TyX = Op.getOperand(0).getValueType(); EVT TyX = Op.getOperand(0).getValueType();
EVT TyY = Op.getOperand(1).getValueType(); EVT TyY = Op.getOperand(1).getValueType();
SDValue Const1 = DAG.getConstant(1, MVT::i32);
SDValue Const31 = DAG.getConstant(31, MVT::i32);
SDLoc DL(Op); SDLoc DL(Op);
SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
SDValue Res; SDValue Res;
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
@ -1916,8 +1911,7 @@ static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Op.getOperand(0), Op.getOperand(0), DAG.getConstant(0, MVT::i32));
DAG.getConstant(0, DL, MVT::i32));
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
} }
@ -1926,8 +1920,8 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
SDValue Const1 = DAG.getConstant(1, MVT::i32);
SDLoc DL(Op); SDLoc DL(Op);
SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
// Bitcast to integer nodes. // Bitcast to integer nodes.
SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
@ -1937,7 +1931,7 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); DAG.getConstant(WidthY - 1, MVT::i32), Const1);
if (WidthX > WidthY) if (WidthX > WidthY)
E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
@ -1945,8 +1939,7 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
X);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
} }
@ -1958,7 +1951,7 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
DAG.getConstant(WidthY - 1, DL, MVT::i32)); DAG.getConstant(WidthY - 1, MVT::i32));
if (WidthX > WidthY) if (WidthX > WidthY)
SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
@ -1966,7 +1959,7 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
DAG.getConstant(WidthX - 1, DL, MVT::i32)); DAG.getConstant(WidthX - 1, MVT::i32));
SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
} }
@ -2049,7 +2042,7 @@ SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
unsigned SType = 0; unsigned SType = 0;
SDLoc DL(Op); SDLoc DL(Op);
return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
DAG.getConstant(SType, DL, MVT::i32)); DAG.getConstant(SType, MVT::i32));
} }
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
@ -2066,17 +2059,17 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
// lo = 0 // lo = 0
// hi = (shl lo, shamt[4:0]) // hi = (shl lo, shamt[4:0])
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
DAG.getConstant(-1, DL, MVT::i32)); DAG.getConstant(-1, MVT::i32));
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, VT));
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32)); DAG.getConstant(0x20, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
DAG.getConstant(0, DL, VT), ShiftLeftLo); DAG.getConstant(0, VT), ShiftLeftLo);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
SDValue Ops[2] = {Lo, Hi}; SDValue Ops[2] = {Lo, Hi};
@ -2104,21 +2097,20 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
// lo = (srl hi, shamt[4:0]) // lo = (srl hi, shamt[4:0])
// hi = 0 // hi = 0
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
DAG.getConstant(-1, DL, MVT::i32)); DAG.getConstant(-1, MVT::i32));
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, VT));
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
DL, VT, Hi, Shamt); DL, VT, Hi, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32)); DAG.getConstant(0x20, MVT::i32));
SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
DAG.getConstant(31, DL, VT));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
IsSRA ? Shift31 : DAG.getConstant(0, DL, VT), ShiftRightHi); IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
SDValue Ops[2] = {Lo, Hi}; SDValue Ops[2] = {Lo, Hi};
return DAG.getMergeValues(Ops, DL); return DAG.getMergeValues(Ops, DL);
@ -2134,7 +2126,7 @@ static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
if (Offset) if (Offset)
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
DAG.getConstant(Offset, DL, BasePtrVT)); DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Ptr, Src }; SDValue Ops[] = { Chain, Ptr, Src };
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
@ -2199,7 +2191,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
// (set tmp2, (shl tmp1, 32)) // (set tmp2, (shl tmp1, 32))
// (set dst, (srl tmp2, 32)) // (set dst, (srl tmp2, 32))
SDLoc DL(LD); SDLoc DL(LD);
SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); SDValue Const32 = DAG.getConstant(32, MVT::i32);
SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
SDValue Ops[] = { SRL, LWR.getValue(1) }; SDValue Ops[] = { SRL, LWR.getValue(1) };
@ -2215,7 +2207,7 @@ static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
if (Offset) if (Offset)
Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
DAG.getConstant(Offset, DL, BasePtrVT)); DAG.getConstant(Offset, BasePtrVT));
SDValue Ops[] = { Chain, Value, Ptr }; SDValue Ops[] = { Chain, Value, Ptr };
return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
@ -2297,9 +2289,8 @@ SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
EVT ValTy = Op->getValueType(0); EVT ValTy = Op->getValueType(0);
int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
SDLoc DL(Op); return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr, DAG.getConstant(0, ValTy));
DAG.getConstant(0, DL, ValTy));
} }
SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
@ -2456,7 +2447,7 @@ MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
bool IsTailCall, SelectionDAG &DAG) const { bool IsTailCall, SelectionDAG &DAG) const {
if (!IsTailCall) { if (!IsTailCall) {
SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
DAG.getIntPtrConstant(Offset, DL)); DAG.getIntPtrConstant(Offset));
return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
false, 0); false, 0);
} }
@ -2582,7 +2573,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// byval arguments to the stack. // byval arguments to the stack.
unsigned StackAlignment = TFL->getStackAlignment(); unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
if (!IsTailCall) if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
@ -2634,9 +2625,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
else if (ValVT == MVT::f64 && LocVT == MVT::i32) { else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Arg, DAG.getConstant(0, DL, MVT::i32)); Arg, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Arg, DAG.getConstant(1, DL, MVT::i32)); Arg, DAG.getConstant(1, MVT::i32));
if (!Subtarget.isLittle()) if (!Subtarget.isLittle())
std::swap(Lo, Hi); std::swap(Lo, Hi);
unsigned LocRegLo = VA.getLocReg(); unsigned LocRegLo = VA.getLocReg();
@ -2675,7 +2666,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
Arg = DAG.getNode( Arg = DAG.getNode(
ISD::SHL, DL, VA.getLocVT(), Arg, ISD::SHL, DL, VA.getLocVT(), Arg,
DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
} }
// Arguments that can be passed on register must be kept at // Arguments that can be passed on register must be kept at
@ -2764,7 +2755,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Create the CALLSEQ_END node. // Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
DAG.getIntPtrConstant(0, DL, true), InFlag, DL); DAG.getIntPtrConstant(0, true), InFlag, DL);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we // Handle result values, copying them out of physregs into vregs that we
@ -2803,7 +2794,7 @@ SDValue MipsTargetLowering::LowerCallResult(
VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
Val = DAG.getNode( Val = DAG.getNode(
Shift, DL, VA.getLocVT(), Val, Shift, DL, VA.getLocVT(), Val,
DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
} }
switch (VA.getLocInfo()) { switch (VA.getLocInfo()) {
@ -2856,7 +2847,7 @@ static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
Val = DAG.getNode( Val = DAG.getNode(
Opcode, DL, VA.getLocVT(), Val, Opcode, DL, VA.getLocVT(), Val,
DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
break; break;
} }
} }
@ -3130,7 +3121,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
Val = DAG.getNode( Val = DAG.getNode(
ISD::SHL, DL, VA.getLocVT(), Val, ISD::SHL, DL, VA.getLocVT(), Val,
DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
} }
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
@ -3432,7 +3423,6 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint, std::string &Constraint,
std::vector<SDValue>&Ops, std::vector<SDValue>&Ops,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue Result; SDValue Result;
// Only support length 1 constraints for now. // Only support length 1 constraints for now.
@ -3447,7 +3437,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue(); int64_t Val = C->getSExtValue();
if (isInt<16>(Val)) { if (isInt<16>(Val)) {
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3457,7 +3447,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getZExtValue(); int64_t Val = C->getZExtValue();
if (Val == 0) { if (Val == 0) {
Result = DAG.getTargetConstant(0, DL, Type); Result = DAG.getTargetConstant(0, Type);
break; break;
} }
} }
@ -3467,7 +3457,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
uint64_t Val = (uint64_t)C->getZExtValue(); uint64_t Val = (uint64_t)C->getZExtValue();
if (isUInt<16>(Val)) { if (isUInt<16>(Val)) {
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3477,7 +3467,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue(); int64_t Val = C->getSExtValue();
if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3487,7 +3477,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue(); int64_t Val = C->getSExtValue();
if ((Val >= -65535) && (Val <= -1)) { if ((Val >= -65535) && (Val <= -1)) {
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3497,7 +3487,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue(); int64_t Val = C->getSExtValue();
if ((isInt<15>(Val))) { if ((isInt<15>(Val))) {
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3507,7 +3497,7 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
EVT Type = Op.getValueType(); EVT Type = Op.getValueType();
int64_t Val = C->getSExtValue(); int64_t Val = C->getSExtValue();
if ((Val <= 65535) && (Val >= 1)) { if ((Val <= 65535) && (Val >= 1)) {
Result = DAG.getTargetConstant(Val, DL, Type); Result = DAG.getTargetConstant(Val, Type);
break; break;
} }
} }
@ -3613,7 +3603,7 @@ void MipsTargetLowering::copyByValRegs(
unsigned VReg = addLiveIn(MF, ArgReg, RC); unsigned VReg = addLiveIn(MF, ArgReg, RC);
unsigned Offset = I * GPRSizeInBytes; unsigned Offset = I * GPRSizeInBytes;
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
DAG.getConstant(Offset, DL, PtrTy)); DAG.getConstant(Offset, PtrTy));
SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
StorePtr, MachinePointerInfo(FuncArg, Offset), StorePtr, MachinePointerInfo(FuncArg, Offset),
false, false, 0); false, false, 0);
@ -3644,7 +3634,7 @@ void MipsTargetLowering::passByValArg(
// Copy words to registers. // Copy words to registers.
for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
DAG.getConstant(OffsetInBytes, DL, PtrTy)); DAG.getConstant(OffsetInBytes, PtrTy));
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
MachinePointerInfo(), false, false, false, MachinePointerInfo(), false, false, false,
Alignment); Alignment);
@ -3670,8 +3660,7 @@ void MipsTargetLowering::passByValArg(
// Load subword. // Load subword.
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
DAG.getConstant(OffsetInBytes, DL, DAG.getConstant(OffsetInBytes, PtrTy));
PtrTy));
SDValue LoadVal = DAG.getExtLoad( SDValue LoadVal = DAG.getExtLoad(
ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false, MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
@ -3687,7 +3676,7 @@ void MipsTargetLowering::passByValArg(
Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
DAG.getConstant(Shamt, DL, MVT::i32)); DAG.getConstant(Shamt, MVT::i32));
if (Val.getNode()) if (Val.getNode())
Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
@ -3708,11 +3697,10 @@ void MipsTargetLowering::passByValArg(
// Copy remainder of byval arg to it with memcpy. // Copy remainder of byval arg to it with memcpy.
unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
DAG.getConstant(OffsetInBytes, DL, PtrTy)); DAG.getConstant(OffsetInBytes, PtrTy));
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); DAG.getIntPtrConstant(VA.getLocMemOffset()));
Chain = DAG.getMemcpy(Chain, DL, Dst, Src, Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
DAG.getConstant(MemCpySize, DL, PtrTy),
Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false, /*isTailCall=*/false,
MachinePointerInfo(), MachinePointerInfo()); MachinePointerInfo(), MachinePointerInfo());

46
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -253,10 +253,9 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
// that SLTu64 produces an i32. We need to fix this in the long run but for // that SLTu64 produces an i32. We need to fix this in the long run but for
// now, just make the DAG type-correct by asserting the upper bits are zero. // now, just make the DAG type-correct by asserting the upper bits are zero.
Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT, Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
CurDAG->getTargetConstant(0, DL, VT), CurDAG->getTargetConstant(0, VT),
SDValue(Carry, 0), SDValue(Carry, 0),
CurDAG->getTargetConstant(Mips::sub_32, DL, CurDAG->getTargetConstant(Mips::sub_32, VT));
VT));
} }
// Generate a second addition only if we know that RHS is not a // Generate a second addition only if we know that RHS is not a
@ -277,7 +276,7 @@ bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
EVT ValTy = Addr.getValueType(); EVT ValTy = Addr.getValueType();
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy); Offset = CurDAG->getTargetConstant(0, ValTy);
return true; return true;
} }
return false; return false;
@ -299,8 +298,7 @@ bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
else else
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
ValTy);
return true; return true;
} }
} }
@ -374,7 +372,7 @@ bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const { SDValue &Offset) const {
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType()); Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
return true; return true;
} }
@ -525,7 +523,7 @@ selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
ImmValue.getBitWidth() == EltTy.getSizeInBits()) { ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) || if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
(!Signed && ImmValue.isIntN(ImmBitSize))) { (!Signed && ImmValue.isIntN(ImmBitSize))) {
Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy); Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
return true; return true;
} }
} }
@ -601,7 +599,7 @@ bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
int32_t Log2 = ImmValue.exactLogBase2(); int32_t Log2 = ImmValue.exactLogBase2();
if (Log2 != -1) { if (Log2 != -1) {
Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy); Imm = CurDAG->getTargetConstant(Log2, EltTy);
return true; return true;
} }
} }
@ -634,8 +632,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
// as the original value. // as the original value.
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) { if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N), Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
EltTy);
return true; return true;
} }
} }
@ -666,8 +663,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
// Extract the run of set bits starting with bit zero, and test that the // Extract the run of set bits starting with bit zero, and test that the
// result is the same as the original value // result is the same as the original value
if (ImmValue == (ImmValue & ~(ImmValue + 1))) { if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N), Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
EltTy);
return true; return true;
} }
} }
@ -688,7 +684,7 @@ bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
int32_t Log2 = (~ImmValue).exactLogBase2(); int32_t Log2 = (~ImmValue).exactLogBase2();
if (Log2 != -1) { if (Log2 != -1) {
Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy); Imm = CurDAG->getTargetConstant(Log2, EltTy);
return true; return true;
} }
} }
@ -766,7 +762,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
SDLoc DL(CN); SDLoc DL(CN);
SDNode *RegOpnd; SDNode *RegOpnd;
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
DL, MVT::i64); MVT::i64);
// The first instruction can be a LUi which is different from other // The first instruction can be a LUi which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register // instructions (ADDiu, ORI and SLL) in that it does not have a register
@ -781,7 +777,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
// The remaining instructions in the sequence are handled here. // The remaining instructions in the sequence are handled here.
for (++Inst; Inst != Seq.end(); ++Inst) { for (++Inst; Inst != Seq.end(); ++Inst) {
ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL, ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
MVT::i64); MVT::i64);
RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
SDValue(RegOpnd, 0), ImmOpnd); SDValue(RegOpnd, 0), ImmOpnd);
@ -852,7 +848,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
} }
SDNode *Rdhwr = SDNode *Rdhwr =
CurDAG->getMachineNode(RdhwrOpc, DL, CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
Node->getValueType(0), Node->getValueType(0),
CurDAG->getRegister(Mips::HWR29, MVT::i32)); CurDAG->getRegister(Mips::HWR29, MVT::i32));
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg, SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
@ -915,10 +911,10 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
if (!SplatValue.isSignedIntN(10)) if (!SplatValue.isSignedIntN(10))
return std::make_pair(false, nullptr); return std::make_pair(false, nullptr);
SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL, SDValue Imm = CurDAG->getTargetConstant(SplatValue,
ViaVecTy.getVectorElementType()); ViaVecTy.getVectorElementType());
SDNode *Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm); SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
if (ResVecTy != ViaVecTy) { if (ResVecTy != ViaVecTy) {
// If LdiOp is writing to a different register class to ResVecTy, then // If LdiOp is writing to a different register class to ResVecTy, then
@ -928,9 +924,9 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
const TargetLowering *TLI = getTargetLowering(); const TargetLowering *TLI = getTargetLowering();
MVT ResVecTySimple = ResVecTy.getSimpleVT(); MVT ResVecTySimple = ResVecTy.getSimpleVT();
const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL, Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
ResVecTy, SDValue(Res, 0), ResVecTy, SDValue(Res, 0),
CurDAG->getTargetConstant(RC->getID(), DL, CurDAG->getTargetConstant(RC->getID(),
MVT::i32)); MVT::i32));
} }
@ -953,7 +949,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
// All memory constraints can at least accept raw pointers. // All memory constraints can at least accept raw pointers.
case InlineAsm::Constraint_i: case InlineAsm::Constraint_i:
OutOps.push_back(Op); OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
case InlineAsm::Constraint_m: case InlineAsm::Constraint_m:
if (selectAddrRegImm16(Op, Base, Offset)) { if (selectAddrRegImm16(Op, Base, Offset)) {
@ -962,7 +958,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
return false; return false;
} }
OutOps.push_back(Op); OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
case InlineAsm::Constraint_R: case InlineAsm::Constraint_R:
// The 'R' constraint is supposed to be much more complicated than this. // The 'R' constraint is supposed to be much more complicated than this.
@ -976,7 +972,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
return false; return false;
} }
OutOps.push_back(Op); OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
case InlineAsm::Constraint_ZC: case InlineAsm::Constraint_ZC:
// ZC matches whatever the pref, ll, and sc instructions can handle for the // ZC matches whatever the pref, ll, and sc instructions can handle for the
@ -1003,7 +999,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
} }
// In all cases, 0-bit offsets are acceptable. // In all cases, 0-bit offsets are acceptable.
OutOps.push_back(Op); OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
} }
return true; return true;

66
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -800,7 +800,7 @@ static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
// Return 0. // Return 0.
if (C == 0) if (C == 0)
return DAG.getConstant(0, DL, VT); return DAG.getConstant(0, VT);
// Return x. // Return x.
if (C == 1) if (C == 1)
@ -809,7 +809,7 @@ static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
// If c is power of 2, return (shl x, log2(c)). // If c is power of 2, return (shl x, log2(c)).
if (isPowerOf2_64(C)) if (isPowerOf2_64(C))
return DAG.getNode(ISD::SHL, DL, VT, X, return DAG.getNode(ISD::SHL, DL, VT, X,
DAG.getConstant(Log2_64(C), DL, ShiftTy)); DAG.getConstant(Log2_64(C), ShiftTy));
unsigned Log2Ceil = Log2_64_Ceil(C); unsigned Log2Ceil = Log2_64_Ceil(C);
uint64_t Floor = 1LL << Log2_64(C); uint64_t Floor = 1LL << Log2_64(C);
@ -864,9 +864,8 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
(SplatValue.getZExtValue() >= EltSize)) (SplatValue.getZExtValue() >= EltSize))
return SDValue(); return SDValue();
SDLoc DL(N); return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
return DAG.getNode(Opc, DL, Ty, N->getOperand(0), DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
} }
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
@ -1213,7 +1212,7 @@ SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
Nd.getAlignment()); Nd.getAlignment());
// i32 load from higher address. // i32 load from higher address.
Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
MachinePointerInfo(), Nd.isVolatile(), MachinePointerInfo(), Nd.isVolatile(),
Nd.isNonTemporal(), Nd.isInvariant(), Nd.isNonTemporal(), Nd.isInvariant(),
@ -1238,9 +1237,9 @@ SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
EVT PtrVT = Ptr.getValueType(); EVT PtrVT = Ptr.getValueType();
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Val, DAG.getConstant(0, DL, MVT::i32)); Val, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Val, DAG.getConstant(1, DL, MVT::i32)); Val, DAG.getConstant(1, MVT::i32));
if (!Subtarget.isLittle()) if (!Subtarget.isLittle())
std::swap(Lo, Hi); std::swap(Lo, Hi);
@ -1251,7 +1250,7 @@ SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
Nd.getAAInfo()); Nd.getAAInfo());
// i32 store to higher address. // i32 store to higher address.
Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
Nd.isVolatile(), Nd.isNonTemporal(), Nd.isVolatile(), Nd.isNonTemporal(),
std::min(Nd.getAlignment(), 4U), Nd.getAAInfo()); std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
@ -1284,9 +1283,9 @@ SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, MVT::i32));
return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
} }
@ -1382,7 +1381,7 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
SDValue LaneB = Op->getOperand(2); SDValue LaneB = Op->getOperand(2);
if (ResVecTy == MVT::v2i64) { if (ResVecTy == MVT::v2i64) {
LaneA = DAG.getConstant(0, DL, MVT::i32); LaneA = DAG.getConstant(0, MVT::i32);
ViaVecTy = MVT::v4i32; ViaVecTy = MVT::v4i32;
} else } else
LaneA = LaneB; LaneA = LaneB;
@ -1400,8 +1399,7 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
} }
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op), return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
Op->getValueType(0));
} }
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
@ -1417,7 +1415,7 @@ static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue); SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue, SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
DAG.getConstant(32, DL, MVT::i32)); DAG.getConstant(32, MVT::i32));
SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB); SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
} }
@ -1453,9 +1451,8 @@ static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) { if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
APInt BitImm = APInt(64, 1) << CImm->getAPIntValue(); APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL, SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
MVT::i32); SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
if (BigEndian) if (BigEndian)
std::swap(BitImmLoOp, BitImmHiOp); std::swap(BitImmLoOp, BitImmHiOp);
@ -1477,8 +1474,8 @@ static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG); Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy), Exp2Imm =
Exp2Imm); DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
} }
return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
@ -1487,7 +1484,7 @@ static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
EVT ResTy = Op->getValueType(0); EVT ResTy = Op->getValueType(0);
SDLoc DL(Op); SDLoc DL(Op);
SDValue One = DAG.getConstant(1, DL, ResTy); SDValue One = DAG.getConstant(1, ResTy);
SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
@ -1499,7 +1496,7 @@ static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
EVT ResTy = Op->getValueType(0); EVT ResTy = Op->getValueType(0);
APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1) APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
<< cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy); SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
} }
@ -1581,8 +1578,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3)); Op->getConstantOperandVal(3));
return DAG.getNode(ISD::VSELECT, DL, VecTy, return DAG.getNode(ISD::VSELECT, DL, VecTy,
DAG.getConstant(Mask, DL, VecTy, true), DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
Op->getOperand(2), Op->getOperand(1)); Op->getOperand(1));
} }
case Intrinsic::mips_binsri_b: case Intrinsic::mips_binsri_b:
case Intrinsic::mips_binsri_h: case Intrinsic::mips_binsri_h:
@ -1594,8 +1591,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3)); Op->getConstantOperandVal(3));
return DAG.getNode(ISD::VSELECT, DL, VecTy, return DAG.getNode(ISD::VSELECT, DL, VecTy,
DAG.getConstant(Mask, DL, VecTy, true), DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
Op->getOperand(2), Op->getOperand(1)); Op->getOperand(1));
} }
case Intrinsic::mips_bmnz_v: case Intrinsic::mips_bmnz_v:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
@ -1616,7 +1613,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_bneg_w: case Intrinsic::mips_bneg_w:
case Intrinsic::mips_bneg_d: { case Intrinsic::mips_bneg_d: {
EVT VecTy = Op->getValueType(0); EVT VecTy = Op->getValueType(0);
SDValue One = DAG.getConstant(1, DL, VecTy); SDValue One = DAG.getConstant(1, VecTy);
return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One, DAG.getNode(ISD::SHL, DL, VecTy, One,
@ -1652,7 +1649,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_bset_w: case Intrinsic::mips_bset_w:
case Intrinsic::mips_bset_d: { case Intrinsic::mips_bset_d: {
EVT VecTy = Op->getValueType(0); EVT VecTy = Op->getValueType(0);
SDValue One = DAG.getConstant(1, DL, VecTy); SDValue One = DAG.getConstant(1, VecTy);
return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One, DAG.getNode(ISD::SHL, DL, VecTy, One,
@ -1926,7 +1923,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_insve_d: case Intrinsic::mips_insve_d:
return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
case Intrinsic::mips_ldi_b: case Intrinsic::mips_ldi_b:
case Intrinsic::mips_ldi_h: case Intrinsic::mips_ldi_h:
case Intrinsic::mips_ldi_w: case Intrinsic::mips_ldi_w:
@ -2366,7 +2363,7 @@ SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
} }
// SelectionDAG::getConstant will promote SplatValue appropriately. // SelectionDAG::getConstant will promote SplatValue appropriately.
SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy); SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
// Bitcast to the type we originally wanted // Bitcast to the type we originally wanted
if (ViaVecTy != ResTy) if (ViaVecTy != ResTy)
@ -2388,7 +2385,7 @@ SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
Node->getOperand(i), Node->getOperand(i),
DAG.getConstant(i, DL, MVT::i32)); DAG.getConstant(i, MVT::i32));
} }
return Vector; return Vector;
} }
@ -2458,9 +2455,8 @@ static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
Imm |= Idx & 0x3; Imm |= Idx & 0x3;
} }
SDLoc DL(Op); return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
return DAG.getNode(MipsISD::SHF, DL, ResTy, DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
} }
// Lower VECTOR_SHUFFLE into ILVEV (if possible). // Lower VECTOR_SHUFFLE into ILVEV (if possible).
@ -2669,7 +2665,7 @@ static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
++I) ++I)
Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy)); Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops); SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);

130
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
View File

@ -703,9 +703,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
default: default:
return nullptr; return nullptr;
} }
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType, dl), getI32Imm(fromType, dl), getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth, dl), Addr, Chain }; getI32Imm(fromTypeWidth), Addr, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
} else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset) } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
: SelectADDRsi(N1.getNode(), N1, Base, Offset)) { : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
@ -731,9 +731,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
default: default:
return nullptr; return nullptr;
} }
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType, dl), getI32Imm(fromType, dl), getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth, dl), Base, Offset, Chain }; getI32Imm(fromTypeWidth), Base, Offset, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
} else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset) } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
: SelectADDRri(N1.getNode(), N1, Base, Offset)) { : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
@ -784,9 +784,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
return nullptr; return nullptr;
} }
} }
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType, dl), getI32Imm(fromType, dl), getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth, dl), Base, Offset, Chain }; getI32Imm(fromTypeWidth), Base, Offset, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
} else { } else {
if (TM.is64Bit()) { if (TM.is64Bit()) {
@ -836,9 +836,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
return nullptr; return nullptr;
} }
} }
SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl), SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType, dl), getI32Imm(fromType, dl), getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth, dl), N1, Chain }; getI32Imm(fromTypeWidth), N1, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
} }
@ -962,9 +962,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
break; break;
} }
SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL), SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
getI32Imm(VecType, DL), getI32Imm(FromType, DL), getI32Imm(VecType), getI32Imm(FromType),
getI32Imm(FromTypeWidth, DL), Addr, Chain }; getI32Imm(FromTypeWidth), Addr, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset) } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
: SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) { : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
@ -1015,9 +1015,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
break; break;
} }
SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL), SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
getI32Imm(VecType, DL), getI32Imm(FromType, DL), getI32Imm(VecType), getI32Imm(FromType),
getI32Imm(FromTypeWidth, DL), Base, Offset, Chain }; getI32Imm(FromTypeWidth), Base, Offset, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset) } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
: SelectADDRri(Op1.getNode(), Op1, Base, Offset)) { : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
@ -1117,9 +1117,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
} }
} }
SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL), SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
getI32Imm(VecType, DL), getI32Imm(FromType, DL), getI32Imm(VecType), getI32Imm(FromType),
getI32Imm(FromTypeWidth, DL), Base, Offset, Chain }; getI32Imm(FromTypeWidth), Base, Offset, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} else { } else {
@ -1219,9 +1219,9 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
} }
} }
SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL), SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
getI32Imm(VecType, DL), getI32Imm(FromType, DL), getI32Imm(VecType), getI32Imm(FromType),
getI32Imm(FromTypeWidth, DL), Op1, Chain }; getI32Imm(FromTypeWidth), Op1, Chain };
LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
} }
@ -2068,10 +2068,9 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
default: default:
return nullptr; return nullptr;
} }
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl), SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(vecType), getI32Imm(toType),
getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr, getI32Imm(toTypeWidth), Addr, Chain };
Chain };
NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
} else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset) } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
: SelectADDRsi(N2.getNode(), N2, Base, Offset)) { : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
@ -2097,10 +2096,9 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
default: default:
return nullptr; return nullptr;
} }
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl), SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(vecType), getI32Imm(toType),
getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base, getI32Imm(toTypeWidth), Base, Offset, Chain };
Offset, Chain };
NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
} else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset) } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
: SelectADDRri(N2.getNode(), N2, Base, Offset)) { : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
@ -2151,10 +2149,9 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
return nullptr; return nullptr;
} }
} }
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl), SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(vecType), getI32Imm(toType),
getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base, getI32Imm(toTypeWidth), Base, Offset, Chain };
Offset, Chain };
NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
} else { } else {
if (TM.is64Bit()) { if (TM.is64Bit()) {
@ -2204,10 +2201,9 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
return nullptr; return nullptr;
} }
} }
SDValue Ops[] = { N1, getI32Imm(isVolatile, dl), SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(vecType), getI32Imm(toType),
getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2, getI32Imm(toTypeWidth), N2, Chain };
Chain };
NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
} }
@ -2281,11 +2277,11 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
return nullptr; return nullptr;
} }
StOps.push_back(getI32Imm(IsVolatile, DL)); StOps.push_back(getI32Imm(IsVolatile));
StOps.push_back(getI32Imm(CodeAddrSpace, DL)); StOps.push_back(getI32Imm(CodeAddrSpace));
StOps.push_back(getI32Imm(VecType, DL)); StOps.push_back(getI32Imm(VecType));
StOps.push_back(getI32Imm(ToType, DL)); StOps.push_back(getI32Imm(ToType));
StOps.push_back(getI32Imm(ToTypeWidth, DL)); StOps.push_back(getI32Imm(ToTypeWidth));
if (SelectDirectAddr(N2, Addr)) { if (SelectDirectAddr(N2, Addr)) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
@ -2714,11 +2710,13 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue(); unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
SmallVector<SDValue, 2> Ops; SmallVector<SDValue, 2> Ops;
Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
Ops.push_back(Flag); Ops.push_back(Flag);
return CurDAG->getMachineNode(Opc, DL, VTs, Ops); SDNode *Ret =
CurDAG->getMachineNode(Opc, DL, VTs, Ops);
return Ret;
} }
SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) { SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
@ -2748,7 +2746,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
SmallVector<SDValue, 6> Ops; SmallVector<SDValue, 6> Ops;
for (unsigned i = 0; i < NumElts; ++i) for (unsigned i = 0; i < NumElts; ++i)
Ops.push_back(N->getOperand(i + 2)); Ops.push_back(N->getOperand(i + 2));
Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
// Determine target opcode // Determine target opcode
@ -2876,8 +2874,8 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i < NumElts; ++i) for (unsigned i = 0; i < NumElts; ++i)
Ops.push_back(N->getOperand(i + 3)); Ops.push_back(N->getOperand(i + 3));
Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
Ops.push_back(Chain); Ops.push_back(Chain);
Ops.push_back(Flag); Ops.push_back(Flag);
@ -2972,7 +2970,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
// the selected StoreParam node. // the selected StoreParam node.
case NVPTXISD::StoreParamU32: { case NVPTXISD::StoreParamU32: {
Opcode = NVPTX::StoreParamI32; Opcode = NVPTX::StoreParamI32;
SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL, SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
MVT::i32); MVT::i32);
SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL, SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
MVT::i32, Ops[0], CvtNone); MVT::i32, Ops[0], CvtNone);
@ -2981,7 +2979,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
} }
case NVPTXISD::StoreParamS32: { case NVPTXISD::StoreParamS32: {
Opcode = NVPTX::StoreParamI32; Opcode = NVPTX::StoreParamI32;
SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL, SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
MVT::i32); MVT::i32);
SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL, SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
MVT::i32, Ops[0], CvtNone); MVT::i32, Ops[0], CvtNone);
@ -4729,7 +4727,6 @@ SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
/// SelectBFE - Look for instruction sequences that can be made more efficient /// SelectBFE - Look for instruction sequences that can be made more efficient
/// by using the 'bfe' (bit-field extract) PTX instruction /// by using the 'bfe' (bit-field extract) PTX instruction
SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) { SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
SDLoc DL(N);
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
SDValue Len; SDValue Len;
@ -4761,7 +4758,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
// How many bits are in our mask? // How many bits are in our mask?
uint64_t NumBits = countTrailingOnes(MaskVal); uint64_t NumBits = countTrailingOnes(MaskVal);
Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32); Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) { if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
// We have a 'srl/and' pair, extract the effective start bit and length // We have a 'srl/and' pair, extract the effective start bit and length
@ -4779,7 +4776,7 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
// emitting the srl/and pair. // emitting the srl/and pair.
return NULL; return NULL;
} }
Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32); Start = CurDAG->getTargetConstant(StartVal, MVT::i32);
} else { } else {
// Do not handle the case where the shift amount (can be zero if no srl // Do not handle the case where the shift amount (can be zero if no srl
// was found) is not constant. We could handle this case, but it would // was found) is not constant. We could handle this case, but it would
@ -4844,8 +4841,8 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
} }
Val = AndLHS; Val = AndLHS;
Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32); Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32);
Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32); Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
} else if (LHS->getOpcode() == ISD::SHL) { } else if (LHS->getOpcode() == ISD::SHL) {
// Here, we have a pattern like: // Here, we have a pattern like:
// //
@ -4885,10 +4882,10 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
} }
Start = Start =
CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32); CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, MVT::i32);
Len = Len =
CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() - CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
OuterShiftAmt, DL, MVT::i32); OuterShiftAmt, MVT::i32);
if (N->getOpcode() == ISD::SRA) { if (N->getOpcode() == ISD::SRA) {
// If we have a arithmetic right shift, we need to use the signed bfe // If we have a arithmetic right shift, we need to use the signed bfe
@ -4929,7 +4926,10 @@ SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
Val, Start, Len Val, Start, Len
}; };
return CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops); SDNode *Ret =
CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
return Ret;
} }
// SelectDirectAddr - Match a direct address for DAG. // SelectDirectAddr - Match a direct address for DAG.
@ -4961,8 +4961,7 @@ bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
SDValue base = Addr.getOperand(0); SDValue base = Addr.getOperand(0);
if (SelectDirectAddr(base, Base)) { if (SelectDirectAddr(base, Base)) {
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode), Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
mvt);
return true; return true;
} }
} }
@ -4987,7 +4986,7 @@ bool NVPTXDAGToDAGISel::SelectADDRri_imp(
SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
Offset = CurDAG->getTargetConstant(0, SDLoc(OpNode), mvt); Offset = CurDAG->getTargetConstant(0, mvt);
return true; return true;
} }
if (Addr.getOpcode() == ISD::TargetExternalSymbol || if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
@ -5005,8 +5004,7 @@ bool NVPTXDAGToDAGISel::SelectADDRri_imp(
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
else else
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode), Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
mvt);
return true; return true;
} }
} }
@ -5051,7 +5049,7 @@ bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
case InlineAsm::Constraint_m: // memory case InlineAsm::Constraint_m: // memory
if (SelectDirectAddr(Op, Op0)) { if (SelectDirectAddr(Op, Op0)) {
OutOps.push_back(Op0); OutOps.push_back(Op0);
OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false; return false;
} }
if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) { if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {

4
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
View File

@ -71,8 +71,8 @@ private:
SDNode *SelectSurfaceIntrinsic(SDNode *N); SDNode *SelectSurfaceIntrinsic(SDNode *N);
SDNode *SelectBFE(SDNode *N); SDNode *SelectBFE(SDNode *N);
inline SDValue getI32Imm(unsigned Imm, SDLoc DL) { inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, DL, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
// Match direct address complex pattern. // Match direct address complex pattern.

169
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -1053,9 +1053,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
const Function *F = MF.getFunction(); const Function *F = MF.getFunction();
SDValue tempChain = Chain; SDValue tempChain = Chain;
Chain = DAG.getCALLSEQ_START(Chain, Chain =
DAG.getIntPtrConstant(uniqueCallSite, dl, true), DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
dl); dl);
SDValue InFlag = Chain.getValue(1); SDValue InFlag = Chain.getValue(1);
unsigned paramCount = 0; unsigned paramCount = 0;
@ -1086,11 +1086,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// declare .param .align <align> .b8 .param<n>[<size>]; // declare .param .align <align> .b8 .param<n>[<size>];
unsigned sz = TD->getTypeAllocSize(Ty); unsigned sz = TD->getTypeAllocSize(Ty);
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl, SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(sz, MVT::i32), InFlag };
DAG.getConstant(sz, dl, MVT::i32),
InFlag };
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
DeclareParamOps); DeclareParamOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1105,8 +1103,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
} }
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain,
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(Offsets[j], dl, MVT::i32), DAG.getConstant(Offsets[j], MVT::i32),
StVal, InFlag }; StVal, InFlag };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
CopyParamVTs, CopyParamOps, CopyParamVTs, CopyParamOps,
@ -1126,11 +1124,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// declare .param .align <align> .b8 .param<n>[<size>]; // declare .param .align <align> .b8 .param<n>[<size>];
unsigned sz = TD->getTypeAllocSize(Ty); unsigned sz = TD->getTypeAllocSize(Ty);
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareParamOps[] = { Chain, SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
DAG.getConstant(align, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(sz, MVT::i32), InFlag };
DAG.getConstant(sz, dl, MVT::i32),
InFlag };
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
DeclareParamOps); DeclareParamOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1151,8 +1147,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain,
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), Elt, DAG.getConstant(0, MVT::i32), Elt,
InFlag }; InFlag };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
CopyParamVTs, CopyParamOps, CopyParamVTs, CopyParamOps,
@ -1168,9 +1164,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain,
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), Elt0, DAG.getConstant(0, MVT::i32), Elt0, Elt1,
Elt1, InFlag }; InFlag };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
CopyParamVTs, CopyParamOps, CopyParamVTs, CopyParamOps,
MemVT, MachinePointerInfo()); MemVT, MachinePointerInfo());
@ -1200,8 +1196,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue StoreVal; SDValue StoreVal;
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain); Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32)); Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32)); Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
unsigned Opc = NVPTXISD::StoreParamV2; unsigned Opc = NVPTXISD::StoreParamV2;
@ -1268,9 +1264,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
} }
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareParamOps[] = { Chain, SDValue DeclareParamOps[] = { Chain,
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(sz, dl, MVT::i32), DAG.getConstant(sz, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InFlag }; DAG.getConstant(0, MVT::i32), InFlag };
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs, Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
DeclareParamOps); DeclareParamOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1283,10 +1279,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
OutV = DAG.getNode(opc, dl, MVT::i16, OutV); OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
} }
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(0, MVT::i32), OutV, InFlag };
DAG.getConstant(0, dl, MVT::i32), OutV,
InFlag };
unsigned opcode = NVPTXISD::StoreParam; unsigned opcode = NVPTXISD::StoreParam;
if (Outs[OIdx].Flags.isZExt()) if (Outs[OIdx].Flags.isZExt())
@ -1315,9 +1309,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// so we don't need to worry about natural alignment or not. // so we don't need to worry about natural alignment or not.
// See TargetLowering::LowerCallTo(). // See TargetLowering::LowerCallTo().
SDValue DeclareParamOps[] = { SDValue DeclareParamOps[] = {
Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32), Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
DAG.getConstant(sz, dl, MVT::i32), InFlag InFlag
}; };
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
DeclareParamOps); DeclareParamOps);
@ -1328,7 +1322,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset); unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
SDValue srcAddr = SDValue srcAddr =
DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx], DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
DAG.getConstant(curOffset, dl, getPointerTy())); DAG.getConstant(curOffset, getPointerTy()));
SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr, SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
MachinePointerInfo(), false, false, false, MachinePointerInfo(), false, false, false,
PartAlign); PartAlign);
@ -1336,10 +1330,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal); theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
} }
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
DAG.getConstant(paramCount, dl, MVT::i32), DAG.getConstant(curOffset, MVT::i32), theVal,
DAG.getConstant(curOffset, dl, MVT::i32), InFlag };
theVal, InFlag };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
CopyParamOps, elemtype, CopyParamOps, elemtype,
MachinePointerInfo()); MachinePointerInfo());
@ -1371,9 +1364,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (resultsz < 32) if (resultsz < 32)
resultsz = 32; resultsz = 32;
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32), SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(resultsz, dl, MVT::i32), DAG.getConstant(resultsz, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InFlag }; DAG.getConstant(0, MVT::i32), InFlag };
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs, Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
DeclareRetOps); DeclareRetOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1381,9 +1374,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
retAlignment = getArgumentAlignment(Callee, CS, retTy, 0); retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue DeclareRetOps[] = { Chain, SDValue DeclareRetOps[] = { Chain,
DAG.getConstant(retAlignment, dl, MVT::i32), DAG.getConstant(retAlignment, MVT::i32),
DAG.getConstant(resultsz / 8, dl, MVT::i32), DAG.getConstant(resultsz / 8, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InFlag }; DAG.getConstant(0, MVT::i32), InFlag };
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs, Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
DeclareRetOps); DeclareRetOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1411,7 +1404,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Op to just print "call" // Op to just print "call"
SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue PrintCallOps[] = { SDValue PrintCallOps[] = {
Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
}; };
Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall), Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
dl, PrintCallVTs, PrintCallOps); dl, PrintCallVTs, PrintCallOps);
@ -1437,22 +1430,20 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
else else
opcode = NVPTXISD::CallArg; opcode = NVPTXISD::CallArg;
SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32), SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(i, dl, MVT::i32), InFlag }; DAG.getConstant(i, MVT::i32), InFlag };
Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps); Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
} }
SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CallArgEndOps[] = { Chain, SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
InFlag }; InFlag };
Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps); Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
if (!Func) { if (!Func) {
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue PrototypeOps[] = { Chain, SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
DAG.getConstant(uniqueCallSite, dl, MVT::i32),
InFlag }; InFlag };
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps); Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1483,8 +1474,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
LoadRetVTs.push_back(EltVT); LoadRetVTs.push_back(EltVT);
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue); LoadRetVTs.push_back(MVT::Glue);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32), SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InFlag}; DAG.getConstant(0, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode( SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParam, dl, NVPTXISD::LoadParam, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo()); DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
@ -1510,8 +1501,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
} }
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue); LoadRetVTs.push_back(MVT::Glue);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32), SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(0, dl, MVT::i32), InFlag}; DAG.getConstant(0, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode( SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParamV2, dl, NVPTXISD::LoadParamV2, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo()); DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
@ -1553,8 +1544,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
} }
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue); LoadRetVTs.push_back(MVT::Glue);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32), SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(Ofst, dl, MVT::i32), InFlag}; DAG.getConstant(Ofst, MVT::i32), InFlag};
SDValue retval = DAG.getMemIntrinsicNode( SDValue retval = DAG.getMemIntrinsicNode(
Opc, dl, DAG.getVTList(LoadRetVTs), Opc, dl, DAG.getVTList(LoadRetVTs),
LoadRetOps, EltVT, MachinePointerInfo()); LoadRetOps, EltVT, MachinePointerInfo());
@ -1608,9 +1599,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Other);
LoadRetVTs.push_back(MVT::Glue); LoadRetVTs.push_back(MVT::Glue);
SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32), SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, MVT::i32),
DAG.getConstant(Offsets[i], dl, MVT::i32), DAG.getConstant(Offsets[i], MVT::i32), InFlag};
InFlag};
SDValue retval = DAG.getMemIntrinsicNode( SDValue retval = DAG.getMemIntrinsicNode(
NVPTXISD::LoadParam, dl, NVPTXISD::LoadParam, dl,
DAG.getVTList(LoadRetVTs), LoadRetOps, DAG.getVTList(LoadRetVTs), LoadRetOps,
@ -1625,10 +1615,8 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
} }
} }
Chain = DAG.getCALLSEQ_END(Chain, Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
DAG.getIntPtrConstant(uniqueCallSite, dl, true), DAG.getIntPtrConstant(uniqueCallSite + 1, true),
DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
true),
InFlag, dl); InFlag, dl);
uniqueCallSite++; uniqueCallSite++;
@ -1654,7 +1642,7 @@ NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
unsigned NumSubElem = VVT.getVectorNumElements(); unsigned NumSubElem = VVT.getVectorNumElements();
for (unsigned j = 0; j < NumSubElem; ++j) { for (unsigned j = 0; j < NumSubElem; ++j) {
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
DAG.getIntPtrConstant(j, dl))); DAG.getIntPtrConstant(j)));
} }
} }
return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops); return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
@ -1703,18 +1691,16 @@ SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
// dHi = aHi >> Amt // dHi = aHi >> Amt
SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
DAG.getConstant(VTBits, dl, MVT::i32), DAG.getConstant(VTBits, MVT::i32), ShAmt);
ShAmt);
SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32)); DAG.getConstant(VTBits, MVT::i32));
SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt, SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32), DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
ISD::SETGE);
SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal); SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
@ -1765,18 +1751,16 @@ SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
// dHi = (aHi << Amt) | (aLo >> (size-Amt)) // dHi = (aHi << Amt) | (aLo >> (size-Amt))
SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
DAG.getConstant(VTBits, dl, MVT::i32), DAG.getConstant(VTBits, MVT::i32), ShAmt);
ShAmt);
SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32)); DAG.getConstant(VTBits, MVT::i32));
SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt, SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
DAG.getConstant(VTBits, dl, MVT::i32), DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
ISD::SETGE);
SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal); SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
@ -1949,7 +1933,7 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
// Then the split values // Then the split values
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
DAG.getIntPtrConstant(i, DL)); DAG.getIntPtrConstant(i));
if (NeedExt) if (NeedExt)
ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Ops.push_back(ExtVal); Ops.push_back(ExtVal);
@ -2093,7 +2077,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
(theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent() (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
: nullptr))) { : nullptr))) {
assert(isKernel && "Only kernels can have image/sampler params"); assert(isKernel && "Only kernels can have image/sampler params");
InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32)); InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
continue; continue;
} }
@ -2155,7 +2139,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
llvm::ADDRESS_SPACE_PARAM)); llvm::ADDRESS_SPACE_PARAM));
SDValue srcAddr = SDValue srcAddr =
DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
DAG.getConstant(offsets[parti], dl, getPointerTy())); DAG.getConstant(offsets[parti], getPointerTy()));
unsigned partAlign = unsigned partAlign =
aggregateIsPacked ? 1 aggregateIsPacked ? 1
: TD->getABITypeAlignment( : TD->getABITypeAlignment(
@ -2220,9 +2204,9 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
P.getNode()->setIROrder(idx + 1); P.getNode()->setIROrder(idx + 1);
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0));
SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) { if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
@ -2255,7 +2239,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
llvm::ADDRESS_SPACE_PARAM)); llvm::ADDRESS_SPACE_PARAM));
SDValue SrcAddr = SDValue SrcAddr =
DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
DAG.getConstant(Ofst, dl, getPointerTy())); DAG.getConstant(Ofst, getPointerTy()));
SDValue P = DAG.getLoad( SDValue P = DAG.getLoad(
VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false, VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
false, true, false, true,
@ -2267,7 +2251,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
if (i + j >= NumElts) if (i + j >= NumElts)
break; break;
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
DAG.getIntPtrConstant(j, dl)); DAG.getIntPtrConstant(j));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt); Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
InVals.push_back(Elt); InVals.push_back(Elt);
@ -2325,7 +2309,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
else { else {
SDValue p2 = DAG.getNode( SDValue p2 = DAG.getNode(
ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT, ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p); DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
InVals.push_back(p2); InVals.push_back(p2);
} }
} }
@ -2379,7 +2363,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
// We only have one element, so just directly store it // We only have one element, so just directly store it
if (NeedExtend) if (NeedExtend)
StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal }; SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
DAG.getVTList(MVT::Other), Ops, DAG.getVTList(MVT::Other), Ops,
EltVT, MachinePointerInfo()); EltVT, MachinePointerInfo());
@ -2394,7 +2378,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1); StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
} }
SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0, SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
StoreVal1 }; StoreVal1 };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
DAG.getVTList(MVT::Other), Ops, DAG.getVTList(MVT::Other), Ops,
@ -2426,7 +2410,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
SDValue StoreVal; SDValue StoreVal;
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain); Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32)); Ops.push_back(DAG.getConstant(Offset, MVT::i32));
unsigned Opc = NVPTXISD::StoreRetvalV2; unsigned Opc = NVPTXISD::StoreRetvalV2;
EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType(); EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
@ -2491,7 +2475,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
if (TheValType.isVector()) if (TheValType.isVector())
TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
TheValType.getVectorElementType(), TmpVal, TheValType.getVectorElementType(), TmpVal,
DAG.getIntPtrConstant(j, dl)); DAG.getIntPtrConstant(j));
EVT TheStoreType = ValVTs[i]; EVT TheStoreType = ValVTs[i];
if (RetTy->isIntegerTy() && if (RetTy->isIntegerTy() &&
TD->getTypeAllocSizeInBits(RetTy) < 32) { TD->getTypeAllocSizeInBits(RetTy) < 32) {
@ -2505,7 +2489,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
SDValue Ops[] = { SDValue Ops[] = {
Chain, Chain,
DAG.getConstant(Offsets[i], dl, MVT::i32), DAG.getConstant(Offsets[i], MVT::i32),
TmpVal }; TmpVal };
Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl, Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
DAG.getVTList(MVT::Other), Ops, DAG.getVTList(MVT::Other), Ops,
@ -4127,7 +4111,6 @@ static SDValue TryMULWIDECombine(SDNode *N,
return SDValue(); return SDValue();
} }
SDLoc DL(N);
unsigned OptSize = MulType.getSizeInBits() >> 1; unsigned OptSize = MulType.getSizeInBits() >> 1;
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
@ -4150,7 +4133,7 @@ static SDValue TryMULWIDECombine(SDNode *N,
unsigned BitWidth = MulType.getSizeInBits(); unsigned BitWidth = MulType.getSizeInBits();
if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) { if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
RHS = DCI.DAG.getConstant(MulVal, DL, MulType); RHS = DCI.DAG.getConstant(MulVal, MulType);
} else { } else {
return SDValue(); return SDValue();
} }
@ -4172,9 +4155,9 @@ static SDValue TryMULWIDECombine(SDNode *N,
// Truncate the operands to the correct size. Note that these are just for // Truncate the operands to the correct size. Note that these are just for
// type consistency and will (likely) be eliminated in later phases. // type consistency and will (likely) be eliminated in later phases.
SDValue TruncLHS = SDValue TruncLHS =
DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS); DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
SDValue TruncRHS = SDValue TruncRHS =
DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS); DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
unsigned Opc; unsigned Opc;
if (Signed) { if (Signed) {
@ -4183,7 +4166,7 @@ static SDValue TryMULWIDECombine(SDNode *N,
Opc = NVPTXISD::MUL_WIDE_UNSIGNED; Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
} }
return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS); return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
} }
/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes. /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
@ -4311,7 +4294,7 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
// The select routine does not have access to the LoadSDNode instance, so // The select routine does not have access to the LoadSDNode instance, so
// pass along the extension information // pass along the extension information
OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL)); OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps, SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
LD->getMemoryVT(), LD->getMemoryVT(),

8
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
View File

@ -452,13 +452,13 @@ def Int4Const : PatLeaf<(imm), [{
def SHL2MUL32 : SDNodeXForm<imm, [{ def SHL2MUL32 : SDNodeXForm<imm, [{
const APInt &v = N->getAPIntValue(); const APInt &v = N->getAPIntValue();
APInt temp(32, 1); APInt temp(32, 1);
return CurDAG->getTargetConstant(temp.shl(v), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(temp.shl(v), MVT::i32);
}]>; }]>;
def SHL2MUL16 : SDNodeXForm<imm, [{ def SHL2MUL16 : SDNodeXForm<imm, [{
const APInt &v = N->getAPIntValue(); const APInt &v = N->getAPIntValue();
APInt temp(16, 1); APInt temp(16, 1);
return CurDAG->getTargetConstant(temp.shl(v), SDLoc(N), MVT::i16); return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
}]>; }]>;
def MULWIDES64 def MULWIDES64
@ -1138,7 +1138,7 @@ def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
[]>; []>;
def SUB_FRM_32 : SDNodeXForm<imm, [{ def SUB_FRM_32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(32-N->getZExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(32-N->getZExtValue(), MVT::i32);
}]>; }]>;
def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)), def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
@ -1189,7 +1189,7 @@ def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
[]>; []>;
def SUB_FRM_64 : SDNodeXForm<imm, [{ def SUB_FRM_64 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(64-N->getZExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(64-N->getZExtValue(), MVT::i32);
}]>; }]>;
def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)), def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)),

8
llvm/lib/Target/NVPTX/NVPTXVector.td
View File

@ -735,19 +735,19 @@ def VecShuffle_v2i64 : NVPTXVecInst<(outs V2I64Regs:$dst),
def ShuffleMask0 : SDNodeXForm<vector_shuffle, [{ def ShuffleMask0 : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
return CurDAG->getTargetConstant(SVOp->getMaskElt(0), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(SVOp->getMaskElt(0), MVT::i32);
}]>; }]>;
def ShuffleMask1 : SDNodeXForm<vector_shuffle, [{ def ShuffleMask1 : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
return CurDAG->getTargetConstant(SVOp->getMaskElt(1), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(SVOp->getMaskElt(1), MVT::i32);
}]>; }]>;
def ShuffleMask2 : SDNodeXForm<vector_shuffle, [{ def ShuffleMask2 : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
return CurDAG->getTargetConstant(SVOp->getMaskElt(2), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(SVOp->getMaskElt(2), MVT::i32);
}]>; }]>;
def ShuffleMask3 : SDNodeXForm<vector_shuffle, [{ def ShuffleMask3 : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
return CurDAG->getTargetConstant(SVOp->getMaskElt(3), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(SVOp->getMaskElt(3), MVT::i32);
}]>; }]>;
// The spurious call is here to silence a compiler warning about N being // The spurious call is here to silence a compiler warning about N being

218
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -90,19 +90,19 @@ namespace {
/// getI32Imm - Return a target constant with the specified value, of type /// getI32Imm - Return a target constant with the specified value, of type
/// i32. /// i32.
inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
/// getI64Imm - Return a target constant with the specified value, of type /// getI64Imm - Return a target constant with the specified value, of type
/// i64. /// i64.
inline SDValue getI64Imm(uint64_t Imm, SDLoc dl) { inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i64); return CurDAG->getTargetConstant(Imm, MVT::i64);
} }
/// getSmallIPtrImm - Return a target constant of pointer type. /// getSmallIPtrImm - Return a target constant of pointer type.
inline SDValue getSmallIPtrImm(unsigned Imm, SDLoc dl) { inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, PPCLowering->getPointerTy()); return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
} }
/// isRotateAndMask - Returns true if Mask and Shift can be folded into a /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
@ -197,11 +197,10 @@ namespace {
// (because we might end up lowering this as 0(%op)). // (because we might end up lowering this as 0(%op)).
const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo(); const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
SDLoc dl(Op); SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
SDValue NewOp = SDValue NewOp =
SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
dl, Op.getValueType(), SDLoc(Op), Op.getValueType(),
Op, RC), 0); Op, RC), 0);
OutOps.push_back(NewOp); OutOps.push_back(NewOp);
@ -407,9 +406,9 @@ SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (SN->hasOneUse()) if (SN->hasOneUse())
return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI, return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
getSmallIPtrImm(Offset, dl)); getSmallIPtrImm(Offset));
return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
getSmallIPtrImm(Offset, dl)); getSmallIPtrImm(Offset));
} }
bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
@ -524,8 +523,8 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
} }
SH &= 31; SH &= 31;
SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl), SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME, dl) }; getI32Imm(ME) };
return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
} }
} }
@ -653,8 +652,8 @@ static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
unsigned Lo = Imm & 0xFFFF; unsigned Lo = Imm & 0xFFFF;
unsigned Hi = (Imm >> 16) & 0xFFFF; unsigned Hi = (Imm >> 16) & 0xFFFF;
auto getI32Imm = [CurDAG, dl](unsigned Imm) { auto getI32Imm = [CurDAG](unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
}; };
// Simple value. // Simple value.
@ -744,8 +743,8 @@ static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
if (!RMin) if (!RMin)
return SelectInt64Direct(CurDAG, dl, Imm); return SelectInt64Direct(CurDAG, dl, Imm);
auto getI32Imm = [CurDAG, dl](unsigned Imm) { auto getI32Imm = [CurDAG](unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
}; };
SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0); SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
@ -1195,8 +1194,8 @@ class BitPermutationSelector {
} }
} }
SDValue getI32Imm(unsigned Imm, SDLoc dl) { SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
uint64_t getZerosMask() { uint64_t getZerosMask() {
@ -1268,8 +1267,7 @@ class BitPermutationSelector {
SDValue VRot; SDValue VRot;
if (VRI.RLAmt) { if (VRI.RLAmt) {
SDValue Ops[] = SDValue Ops[] =
{ VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl), { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
getI32Imm(31, dl) };
VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
Ops), 0); Ops), 0);
} else { } else {
@ -1279,10 +1277,10 @@ class BitPermutationSelector {
SDValue ANDIVal, ANDISVal; SDValue ANDIVal, ANDISVal;
if (ANDIMask != 0) if (ANDIMask != 0)
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32, ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
VRot, getI32Imm(ANDIMask, dl)), 0); VRot, getI32Imm(ANDIMask)), 0);
if (ANDISMask != 0) if (ANDISMask != 0)
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32, ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
VRot, getI32Imm(ANDISMask, dl)), 0); VRot, getI32Imm(ANDISMask)), 0);
SDValue TotalVal; SDValue TotalVal;
if (!ANDIVal) if (!ANDIVal)
@ -1328,10 +1326,8 @@ class BitPermutationSelector {
if (VRI.RLAmt) { if (VRI.RLAmt) {
if (InstCnt) *InstCnt += 1; if (InstCnt) *InstCnt += 1;
SDValue Ops[] = SDValue Ops[] =
{ VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl), { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
getI32Imm(31, dl) }; Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
0);
} else { } else {
Res = VRI.V; Res = VRI.V;
} }
@ -1351,15 +1347,13 @@ class BitPermutationSelector {
for (auto &BG : BitGroups) { for (auto &BG : BitGroups) {
if (!Res) { if (!Res) {
SDValue Ops[] = SDValue Ops[] =
{ BG.V, getI32Imm(BG.RLAmt, dl), { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
getI32Imm(Bits.size() - BG.EndIdx - 1, dl), getI32Imm(Bits.size() - BG.StartIdx - 1) };
getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
} else { } else {
SDValue Ops[] = SDValue Ops[] =
{ Res, BG.V, getI32Imm(BG.RLAmt, dl), { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
getI32Imm(Bits.size() - BG.EndIdx - 1, dl), getI32Imm(Bits.size() - BG.StartIdx - 1) };
getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0); Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
} }
} }
@ -1378,10 +1372,10 @@ class BitPermutationSelector {
SDValue ANDIVal, ANDISVal; SDValue ANDIVal, ANDISVal;
if (ANDIMask != 0) if (ANDIMask != 0)
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32, ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
Res, getI32Imm(ANDIMask, dl)), 0); Res, getI32Imm(ANDIMask)), 0);
if (ANDISMask != 0) if (ANDISMask != 0)
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32, ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
Res, getI32Imm(ANDISMask, dl)), 0); Res, getI32Imm(ANDISMask)), 0);
if (!ANDIVal) if (!ANDIVal)
Res = ANDISVal; Res = ANDISVal;
@ -1432,27 +1426,27 @@ class BitPermutationSelector {
assert(InstMaskStart >= 32 && "Mask cannot start out of range"); assert(InstMaskStart >= 32 && "Mask cannot start out of range");
assert(InstMaskEnd >= 32 && "Mask cannot end out of range"); assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
SDValue Ops[] = SDValue Ops[] =
{ V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl), { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
getI32Imm(InstMaskEnd - 32, dl) }; getI32Imm(InstMaskEnd - 32) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
Ops), 0); Ops), 0);
} }
if (InstMaskEnd == 63) { if (InstMaskEnd == 63) {
SDValue Ops[] = SDValue Ops[] =
{ V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) }; { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0); return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
} }
if (InstMaskStart == 0) { if (InstMaskStart == 0) {
SDValue Ops[] = SDValue Ops[] =
{ V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskEnd, dl) }; { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0); return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
} }
if (InstMaskEnd == 63 - RLAmt) { if (InstMaskEnd == 63 - RLAmt) {
SDValue Ops[] = SDValue Ops[] =
{ V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) }; { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0); return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
} }
@ -1493,15 +1487,15 @@ class BitPermutationSelector {
assert(InstMaskStart >= 32 && "Mask cannot start out of range"); assert(InstMaskStart >= 32 && "Mask cannot start out of range");
assert(InstMaskEnd >= 32 && "Mask cannot end out of range"); assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
SDValue Ops[] = SDValue Ops[] =
{ Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl), { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
getI32Imm(InstMaskEnd - 32, dl) }; getI32Imm(InstMaskEnd - 32) };
return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64, return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
Ops), 0); Ops), 0);
} }
if (InstMaskEnd == 63 - RLAmt) { if (InstMaskEnd == 63 - RLAmt) {
SDValue Ops[] = SDValue Ops[] =
{ Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) }; { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0); return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
} }
@ -1648,10 +1642,10 @@ class BitPermutationSelector {
SDValue ANDIVal, ANDISVal; SDValue ANDIVal, ANDISVal;
if (ANDIMask != 0) if (ANDIMask != 0)
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64, ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
VRot, getI32Imm(ANDIMask, dl)), 0); VRot, getI32Imm(ANDIMask)), 0);
if (ANDISMask != 0) if (ANDISMask != 0)
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64, ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
VRot, getI32Imm(ANDISMask, dl)), 0); VRot, getI32Imm(ANDISMask)), 0);
if (!ANDIVal) if (!ANDIVal)
TotalVal = ANDISVal; TotalVal = ANDISVal;
@ -1798,10 +1792,10 @@ class BitPermutationSelector {
SDValue ANDIVal, ANDISVal; SDValue ANDIVal, ANDISVal;
if (ANDIMask != 0) if (ANDIMask != 0)
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64, ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
Res, getI32Imm(ANDIMask, dl)), 0); Res, getI32Imm(ANDIMask)), 0);
if (ANDISMask != 0) if (ANDISMask != 0)
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64, ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
Res, getI32Imm(ANDISMask, dl)), 0); Res, getI32Imm(ANDISMask)), 0);
if (!ANDIVal) if (!ANDIVal)
Res = ANDISVal; Res = ANDISVal;
@ -1946,13 +1940,11 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// SETEQ/SETNE comparison with 16-bit immediate, fold it. // SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt<16>(Imm)) if (isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF, dl)), getI32Imm(Imm & 0xFFFF)), 0);
0);
// If this is a 16-bit signed immediate, fold it. // If this is a 16-bit signed immediate, fold it.
if (isInt<16>((int)Imm)) if (isInt<16>((int)Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF, dl)), getI32Imm(Imm & 0xFFFF)), 0);
0);
// For non-equality comparisons, the default code would materialize the // For non-equality comparisons, the default code would materialize the
// constant, then compare against it, like this: // constant, then compare against it, like this:
@ -1964,22 +1956,21 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// cmplwi cr0,r0,0x5678 // cmplwi cr0,r0,0x5678
// beq cr0,L6 // beq cr0,L6
SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
getI32Imm(Imm >> 16, dl)), 0); getI32Imm(Imm >> 16)), 0);
return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF, dl)), 0); getI32Imm(Imm & 0xFFFF)), 0);
} }
Opc = PPC::CMPLW; Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) { } else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF, dl)), 0); getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW; Opc = PPC::CMPLW;
} else { } else {
short SImm; short SImm;
if (isIntS16Immediate(RHS, SImm)) if (isIntS16Immediate(RHS, SImm))
return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF, getI32Imm((int)SImm & 0xFFFF)),
dl)),
0); 0);
Opc = PPC::CMPW; Opc = PPC::CMPW;
} }
@ -1990,13 +1981,11 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// SETEQ/SETNE comparison with 16-bit immediate, fold it. // SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt<16>(Imm)) if (isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF, dl)), getI32Imm(Imm & 0xFFFF)), 0);
0);
// If this is a 16-bit signed immediate, fold it. // If this is a 16-bit signed immediate, fold it.
if (isInt<16>(Imm)) if (isInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF, dl)), getI32Imm(Imm & 0xFFFF)), 0);
0);
// For non-equality comparisons, the default code would materialize the // For non-equality comparisons, the default code would materialize the
// constant, then compare against it, like this: // constant, then compare against it, like this:
@ -2009,23 +1998,22 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// beq cr0,L6 // beq cr0,L6
if (isUInt<32>(Imm)) { if (isUInt<32>(Imm)) {
SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
getI64Imm(Imm >> 16, dl)), 0); getI64Imm(Imm >> 16)), 0);
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF, dl)), getI64Imm(Imm & 0xFFFF)), 0);
0);
} }
} }
Opc = PPC::CMPLD; Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) { } else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF, dl)), 0); getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD; Opc = PPC::CMPLD;
} else { } else {
short SImm; short SImm;
if (isIntS16Immediate(RHS, SImm)) if (isIntS16Immediate(RHS, SImm))
return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF, dl)), getI64Imm(SImm & 0xFFFF)),
0); 0);
Opc = PPC::CMPD; Opc = PPC::CMPD;
} }
@ -2227,29 +2215,26 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
default: break; default: break;
case ISD::SETEQ: { case ISD::SETEQ: {
Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl), SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
getI32Imm(31, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
case ISD::SETNE: { case ISD::SETNE: {
if (isPPC64) break; if (isPPC64) break;
SDValue AD = SDValue AD =
SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(~0U, dl)), 0); Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1)); AD.getValue(1));
} }
case ISD::SETLT: { case ISD::SETLT: {
SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl), SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
getI32Imm(31, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
case ISD::SETGT: { case ISD::SETGT: {
SDValue T = SDValue T =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl), SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
getI32Imm(31, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
} }
@ -2260,35 +2245,34 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
case ISD::SETEQ: case ISD::SETEQ:
if (isPPC64) break; if (isPPC64) break;
Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(1, dl)), 0); Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(CurDAG->getMachineNode(PPC::LI, dl, SDValue(CurDAG->getMachineNode(PPC::LI, dl,
MVT::i32, MVT::i32,
getI32Imm(0, dl)), getI32Imm(0)), 0),
0), Op.getValue(1)); Op.getValue(1));
case ISD::SETNE: { case ISD::SETNE: {
if (isPPC64) break; if (isPPC64) break;
Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(~0U, dl)); Op, getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1)); Op, SDValue(AD, 1));
} }
case ISD::SETLT: { case ISD::SETLT: {
SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
getI32Imm(1, dl)), 0); getI32Imm(1)), 0);
SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
Op), 0); Op), 0);
SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl), SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
getI32Imm(31, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
case ISD::SETGT: { case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl), SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
getI32Imm(31, dl) }; Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1, dl)); getI32Imm(1));
} }
} }
} }
@ -2338,15 +2322,15 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0); CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl), SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31, dl), getI32Imm(31, dl) }; getI32Imm(31), getI32Imm(31) };
if (!Inv) if (!Inv)
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
// Get the specified bit. // Get the specified bit.
SDValue Tmp = SDValue Tmp =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl)); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
} }
SDNode *PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) { SDNode *PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
@ -2414,8 +2398,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDValue ShiftAmt = SDValue ShiftAmt =
CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))-> CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
getConstantIntValue(), dl, getConstantIntValue(), N->getValueType(0));
N->getValueType(0));
if (N->getValueType(0) == MVT::i64) { if (N->getValueType(0) == MVT::i64) {
SDNode *Op = SDNode *Op =
CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue, CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
@ -2530,8 +2513,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
if (isInt32Immediate(N->getOperand(1), Imm) && if (isInt32Immediate(N->getOperand(1), Imm) &&
isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
SDValue Val = N->getOperand(0).getOperand(0); SDValue Val = N->getOperand(0).getOperand(0);
SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl), SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
getI32Imm(ME, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
// If this is just a masked value where the input is not handled above, and // If this is just a masked value where the input is not handled above, and
@ -2540,8 +2522,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
isRunOfOnes(Imm, MB, ME) && isRunOfOnes(Imm, MB, ME) &&
N->getOperand(0).getOpcode() != ISD::ROTL) { N->getOperand(0).getOpcode() != ISD::ROTL) {
SDValue Val = N->getOperand(0); SDValue Val = N->getOperand(0);
SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl), SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
getI32Imm(ME, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
// If this is a 64-bit zero-extension mask, emit rldicl. // If this is a 64-bit zero-extension mask, emit rldicl.
@ -2563,7 +2544,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
SH = 64 - Imm; SH = 64 - Imm;
} }
SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) }; SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops); return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
} }
// AND X, 0 -> 0, not "rlwinm 32". // AND X, 0 -> 0, not "rlwinm 32".
@ -2581,8 +2562,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
if (isRunOfOnes(Imm, MB, ME)) { if (isRunOfOnes(Imm, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1), N->getOperand(0).getOperand(1),
getI32Imm(0, dl), getI32Imm(MB, dl), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
getI32Imm(ME, dl) };
return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
} }
} }
@ -2623,8 +2603,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) { isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH, dl), getI32Imm(MB, dl), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
getI32Imm(ME, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
@ -2636,8 +2615,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) { isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0), SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH, dl), getI32Imm(MB, dl), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
getI32Imm(ME, dl) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} }
@ -2657,12 +2635,11 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo; unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
N->getOperand(0), N->getOperand(0),
CurDAG->getTargetConstant(1, dl, InVT)), CurDAG->getTargetConstant(1, InVT)), 0);
0);
SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32); SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
SDValue SRIdxVal = SDValue SRIdxVal =
CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ? CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
PPC::sub_eq : PPC::sub_gt, dl, MVT::i32); PPC::sub_eq : PPC::sub_gt, MVT::i32);
return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
CR0Reg, SRIdxVal, CR0Reg, SRIdxVal,
@ -2689,7 +2666,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
N->getValueType(0) == MVT::i32) { N->getValueType(0) == MVT::i32) {
SDNode *Tmp = SDNode *Tmp =
CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
N->getOperand(0), getI32Imm(~0U, dl)); N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDValue(Tmp, 0), N->getOperand(0), SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1)); SDValue(Tmp, 1));
@ -2753,7 +2730,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
SelectCCOp = PPC::SELECT_CC_VRRC; SelectCCOp = PPC::SELECT_CC_VRRC;
SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
getI32Imm(BROpc, dl) }; getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops); return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
} }
case ISD::VSELECT: case ISD::VSELECT:
@ -2787,8 +2764,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
DM[1] = 1 - tmp; DM[1] = 1 - tmp;
} }
SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl, SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
MVT::i32);
if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 && if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
Op1.getOpcode() == ISD::SCALAR_TO_VECTOR && Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
@ -2827,7 +2803,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
// Op #4 is the Flag. // Op #4 is the Flag.
// Prevent PPC::PRED_* from being selected into LI. // Prevent PPC::PRED_* from being selected into LI.
SDValue Pred = SDValue Pred =
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(), dl); getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) }; N->getOperand(0), N->getOperand(4) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops); return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
@ -2857,7 +2833,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
} }
SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
SDValue Ops[] = { getI32Imm(PCC, dl), CondCode, SDValue Ops[] = { getI32Imm(PCC), CondCode,
N->getOperand(4), N->getOperand(0) }; N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops); return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
} }
@ -2960,7 +2936,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
// Into: tmp = VSPLTIS[BHW] elt // Into: tmp = VSPLTIS[BHW] elt
// VADDU[BHW]M tmp, tmp // VADDU[BHW]M tmp, tmp
// Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
SDValue EltVal = getI32Imm(Elt >> 1, dl); SDValue EltVal = getI32Imm(Elt >> 1);
SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
SDValue TmpVal = SDValue(Tmp, 0); SDValue TmpVal = SDValue(Tmp, 0);
return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
@ -2972,9 +2948,9 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
// Into: tmp1 = VSPLTIS[BHW] elt-16 // Into: tmp1 = VSPLTIS[BHW] elt-16
// tmp2 = VSPLTIS[BHW] -16 // tmp2 = VSPLTIS[BHW] -16
// VSUBU[BHW]M tmp1, tmp2 // VSUBU[BHW]M tmp1, tmp2
SDValue EltVal = getI32Imm(Elt - 16, dl); SDValue EltVal = getI32Imm(Elt - 16);
SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
EltVal = getI32Imm(-16, dl); EltVal = getI32Imm(-16);
SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
SDValue(Tmp2, 0)); SDValue(Tmp2, 0));
@ -2986,9 +2962,9 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
// Into: tmp1 = VSPLTIS[BHW] elt+16 // Into: tmp1 = VSPLTIS[BHW] elt+16
// tmp2 = VSPLTIS[BHW] -16 // tmp2 = VSPLTIS[BHW] -16
// VADDU[BHW]M tmp1, tmp2 // VADDU[BHW]M tmp1, tmp2
SDValue EltVal = getI32Imm(Elt + 16, dl); SDValue EltVal = getI32Imm(Elt + 16);
SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
EltVal = getI32Imm(-16, dl); EltVal = getI32Imm(-16);
SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
SDValue(Tmp2, 0)); SDValue(Tmp2, 0));
@ -3197,8 +3173,7 @@ SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1); bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
if (NonTrivialMask && !Alt) { if (NonTrivialMask && !Alt) {
// Res = Mask & CMPB // Res = Mask & CMPB
Res = CurDAG->getNode(ISD::AND, dl, VT, Res, Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
CurDAG->getConstant(Mask, dl, VT));
} else if (Alt) { } else if (Alt) {
// Res = (CMPB & Mask) | (~CMPB & Alt) // Res = (CMPB & Mask) | (~CMPB & Alt)
// Which, as suggested here: // Which, as suggested here:
@ -3207,9 +3182,8 @@ SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
// Res = Alt ^ ((Alt ^ Mask) & CMPB) // Res = Alt ^ ((Alt ^ Mask) & CMPB)
// useful because the (Alt ^ Mask) can be pre-computed. // useful because the (Alt ^ Mask) can be pre-computed.
Res = CurDAG->getNode(ISD::AND, dl, VT, Res, Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
CurDAG->getConstant(Mask ^ Alt, dl, VT)); CurDAG->getConstant(Mask ^ Alt, VT));
Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
CurDAG->getConstant(Alt, dl, VT));
} }
return Res; return Res;
@ -3241,20 +3215,20 @@ void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue Cond = N->getOperand(0); SDValue Cond = N->getOperand(0);
SDValue ConstTrue = SDValue ConstTrue =
CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT); CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, VT);
SDValue ConstFalse = CurDAG->getConstant(0, dl, VT); SDValue ConstFalse = CurDAG->getConstant(0, VT);
do { do {
SDNode *User = *N->use_begin(); SDNode *User = *N->use_begin();
if (User->getNumOperands() != 2) if (User->getNumOperands() != 2)
break; break;
auto TryFold = [this, N, User, dl](SDValue Val) { auto TryFold = [this, N, User](SDValue Val) {
SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1); SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
SDValue O0 = UserO0.getNode() == N ? Val : UserO0; SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
SDValue O1 = UserO1.getNode() == N ? Val : UserO1; SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl, return CurDAG->FoldConstantArithmetic(User->getOpcode(),
User->getValueType(0), User->getValueType(0),
O0.getNode(), O1.getNode()); O0.getNode(), O1.getNode());
}; };

318
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

9
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -56,23 +56,22 @@ def tlscall : Operand<i64> {
def SHL64 : SDNodeXForm<imm, [{ def SHL64 : SDNodeXForm<imm, [{
// Transformation function: 63 - imm // Transformation function: 63 - imm
return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); return getI32Imm(63 - N->getZExtValue());
}]>; }]>;
def SRL64 : SDNodeXForm<imm, [{ def SRL64 : SDNodeXForm<imm, [{
// Transformation function: 64 - imm // Transformation function: 64 - imm
return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
: getI32Imm(0, SDLoc(N));
}]>; }]>;
def HI32_48 : SDNodeXForm<imm, [{ def HI32_48 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
}]>; }]>;
def HI48_64 : SDNodeXForm<imm, [{ def HI48_64 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
}]>; }]>;

12
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -144,7 +144,7 @@ def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG));
}]>; }]>;
def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{
@ -155,7 +155,7 @@ def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
/// vector_shuffle(X,undef,mask) by the dag combiner. /// vector_shuffle(X,undef,mask) by the dag combiner.
def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG));
}]>; }]>;
def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{
@ -166,7 +166,7 @@ def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
/// VSLDOI_swapped* - These fragments are provided for little-endian, where /// VSLDOI_swapped* - These fragments are provided for little-endian, where
/// the inputs must be swapped for correct semantics. /// the inputs must be swapped for correct semantics.
def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG));
}]>; }]>;
def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{
@ -176,21 +176,21 @@ def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N)); return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
}]>; }]>;
def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
}], VSPLTB_get_imm>; }], VSPLTB_get_imm>;
def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N)); return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
}]>; }]>;
def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
}], VSPLTH_get_imm>; }], VSPLTH_get_imm>;
def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N)); return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
}]>; }]>;
def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{ (vector_shuffle node:$lhs, node:$rhs), [{

2
llvm/lib/Target/PowerPC/PPCInstrHTM.td
View File

@ -17,7 +17,7 @@
def HasHTM : Predicate<"PPCSubTarget->hasHTM()">; def HasHTM : Predicate<"PPCSubTarget->hasHTM()">;
def HTM_get_imm : SDNodeXForm<imm, [{ def HTM_get_imm : SDNodeXForm<imm, [{
return getI32Imm (N->getZExtValue(), SDLoc(N)); return getI32Imm (N->getZExtValue());
}]>; }]>;
let hasSideEffects = 1, usesCustomInserter = 1 in { let hasSideEffects = 1, usesCustomInserter = 1 in {

15
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -228,42 +228,41 @@ def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
def SHL32 : SDNodeXForm<imm, [{ def SHL32 : SDNodeXForm<imm, [{
// Transformation function: 31 - imm // Transformation function: 31 - imm
return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); return getI32Imm(31 - N->getZExtValue());
}]>; }]>;
def SRL32 : SDNodeXForm<imm, [{ def SRL32 : SDNodeXForm<imm, [{
// Transformation function: 32 - imm // Transformation function: 32 - imm
return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
: getI32Imm(0, SDLoc(N));
}]>; }]>;
def LO16 : SDNodeXForm<imm, [{ def LO16 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits. // Transformation function: get the low 16 bits.
return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); return getI32Imm((unsigned short)N->getZExtValue());
}]>; }]>;
def HI16 : SDNodeXForm<imm, [{ def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); return getI32Imm((unsigned)N->getZExtValue() >> 16);
}]>; }]>;
def HA16 : SDNodeXForm<imm, [{ def HA16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
signed int Val = N->getZExtValue(); signed int Val = N->getZExtValue();
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); return getI32Imm((Val - (signed short)Val) >> 16);
}]>; }]>;
def MB : SDNodeXForm<imm, [{ def MB : SDNodeXForm<imm, [{
// Transformation function: get the start bit of a mask // Transformation function: get the start bit of a mask
unsigned mb = 0, me; unsigned mb = 0, me;
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
return getI32Imm(mb, SDLoc(N)); return getI32Imm(mb);
}]>; }]>;
def ME : SDNodeXForm<imm, [{ def ME : SDNodeXForm<imm, [{
// Transformation function: get the end bit of a mask // Transformation function: get the end bit of a mask
unsigned mb, me = 0; unsigned mb, me = 0;
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
return getI32Imm(me, SDLoc(N)); return getI32Imm(me);
}]>; }]>;
def maskimm32 : PatLeaf<(imm), [{ def maskimm32 : PatLeaf<(imm), [{
// maskImm predicate - True if immediate is a run of ones. // maskImm predicate - True if immediate is a run of ones.

200
llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
View File

@ -50,6 +50,7 @@ public:
private: private:
bool isInlineImmediate(SDNode *N) const; bool isInlineImmediate(SDNode *N) const;
inline SDValue getSmallIPtrImm(unsigned Imm);
bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs, bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
const R600InstrInfo *TII); const R600InstrInfo *TII);
bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &); bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
@ -188,23 +189,27 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
} }
} }
SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
bool AMDGPUDAGToDAGISel::SelectADDRParam( bool AMDGPUDAGToDAGISel::SelectADDRParam(
SDValue Addr, SDValue& R1, SDValue& R2) { SDValue Addr, SDValue& R1, SDValue& R2) {
if (Addr.getOpcode() == ISD::FrameIndex) { if (Addr.getOpcode() == ISD::FrameIndex) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); R2 = CurDAG->getTargetConstant(0, MVT::i32);
} else { } else {
R1 = Addr; R1 = Addr;
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); R2 = CurDAG->getTargetConstant(0, MVT::i32);
} }
} else if (Addr.getOpcode() == ISD::ADD) { } else if (Addr.getOpcode() == ISD::ADD) {
R1 = Addr.getOperand(0); R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1); R2 = Addr.getOperand(1);
} else { } else {
R1 = Addr; R1 = Addr;
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); R2 = CurDAG->getTargetConstant(0, MVT::i32);
} }
return true; return true;
} }
@ -227,17 +232,17 @@ bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
if (Addr.getOpcode() == ISD::FrameIndex) { if (Addr.getOpcode() == ISD::FrameIndex) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64); R2 = CurDAG->getTargetConstant(0, MVT::i64);
} else { } else {
R1 = Addr; R1 = Addr;
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64); R2 = CurDAG->getTargetConstant(0, MVT::i64);
} }
} else if (Addr.getOpcode() == ISD::ADD) { } else if (Addr.getOpcode() == ISD::ADD) {
R1 = Addr.getOperand(0); R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1); R2 = Addr.getOperand(1);
} else { } else {
R1 = Addr; R1 = Addr;
R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64); R2 = CurDAG->getTargetConstant(0, MVT::i64);
} }
return true; return true;
} }
@ -321,8 +326,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
} }
} }
SDLoc DL(N); SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
if (NumVectorElts == 1) { if (NumVectorElts == 1) {
return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
@ -336,7 +340,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
// 1 = Vector Register Class // 1 = Vector Register Class
SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1); SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
bool IsRegSeq = true; bool IsRegSeq = true;
unsigned NOps = N->getNumOperands(); unsigned NOps = N->getNumOperands();
for (unsigned i = 0; i < NOps; i++) { for (unsigned i = 0; i < NOps; i++) {
@ -347,8 +351,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
} }
RegSeqArgs[1 + (2 * i)] = N->getOperand(i); RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
RegSeqArgs[1 + (2 * i) + 1] = RegSeqArgs[1 + (2 * i) + 1] =
CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
MVT::i32);
} }
if (NOps != NumVectorElts) { if (NOps != NumVectorElts) {
@ -356,11 +359,11 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
DL, EltVT); SDLoc(N), EltVT);
for (unsigned i = NOps; i < NumVectorElts; ++i) { for (unsigned i = NOps; i < NumVectorElts; ++i) {
RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
RegSeqArgs[1 + (2 * i) + 1] = RegSeqArgs[1 + (2 * i) + 1] =
CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
} }
} }
@ -374,22 +377,21 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
break; break;
} }
SDLoc DL(N);
if (N->getValueType(0) == MVT::i128) { if (N->getValueType(0) == MVT::i128) {
RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32); RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
} else if (N->getValueType(0) == MVT::i64) { } else if (N->getValueType(0) == MVT::i64) {
RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32); RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
} else { } else {
llvm_unreachable("Unhandled value type for BUILD_PAIR"); llvm_unreachable("Unhandled value type for BUILD_PAIR");
} }
const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
N->getOperand(1), SubReg1 }; N->getOperand(1), SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
DL, N->getValueType(0), Ops); SDLoc(N), N->getValueType(0), Ops);
} }
case ISD::Constant: case ISD::Constant:
@ -406,19 +408,17 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
Imm = C->getZExtValue(); Imm = C->getZExtValue();
} }
SDLoc DL(N); SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
CurDAG->getConstant(Imm & 0xFFFFFFFF, DL, SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
MVT::i32)); CurDAG->getConstant(Imm >> 32, MVT::i32));
SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
const SDValue Ops[] = { const SDValue Ops[] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32) SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
}; };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
N->getValueType(0), Ops); N->getValueType(0), Ops);
} }
@ -474,17 +474,15 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
break; break;
SDValue Addr, Offset; SDValue Addr, Offset;
SDLoc DL(N);
SelectADDRIndirect(N->getOperand(1), Addr, Offset); SelectADDRIndirect(N->getOperand(1), Addr, Offset);
const SDValue Ops[] = { const SDValue Ops[] = {
Addr, Addr,
Offset, Offset,
CurDAG->getTargetConstant(0, DL, MVT::i32), CurDAG->getTargetConstant(0, MVT::i32),
N->getOperand(0), N->getOperand(0),
}; };
return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, DL, return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
CurDAG->getVTList(MVT::i32, MVT::i64, CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
MVT::Other),
Ops); Ops);
} }
case AMDGPUISD::REGISTER_STORE: { case AMDGPUISD::REGISTER_STORE: {
@ -492,15 +490,14 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
break; break;
SDValue Addr, Offset; SDValue Addr, Offset;
SelectADDRIndirect(N->getOperand(2), Addr, Offset); SelectADDRIndirect(N->getOperand(2), Addr, Offset);
SDLoc DL(N);
const SDValue Ops[] = { const SDValue Ops[] = {
N->getOperand(1), N->getOperand(1),
Addr, Addr,
Offset, Offset,
CurDAG->getTargetConstant(0, DL, MVT::i32), CurDAG->getTargetConstant(0, MVT::i32),
N->getOperand(0), N->getOperand(0),
}; };
return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, DL, return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
CurDAG->getVTList(MVT::Other), CurDAG->getVTList(MVT::Other),
Ops); Ops);
} }
@ -685,8 +682,7 @@ const char *AMDGPUDAGToDAGISel::getPassName() const {
bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr, bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
SDValue& IntPtr) { SDValue& IntPtr) {
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) { if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr), IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
true);
return true; return true;
} }
return false; return false;
@ -696,7 +692,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
SDValue& BaseReg, SDValue &Offset) { SDValue& BaseReg, SDValue &Offset) {
if (!isa<ConstantSDNode>(Addr)) { if (!isa<ConstantSDNode>(Addr)) {
BaseReg = Addr; BaseReg = Addr;
Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true); Offset = CurDAG->getIntPtrConstant(0, true);
return true; return true;
} }
return false; return false;
@ -711,8 +707,7 @@ bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
&& isInt<16>(IMMOffset->getZExtValue())) { && isInt<16>(IMMOffset->getZExtValue())) {
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
MVT::i32);
return true; return true;
// If the pointer address is constant, we can move it to the offset field. // If the pointer address is constant, we can move it to the offset field.
} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr)) } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
@ -720,32 +715,30 @@ bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDLoc(CurDAG->getEntryNode()), SDLoc(CurDAG->getEntryNode()),
AMDGPU::ZERO, MVT::i32); AMDGPU::ZERO, MVT::i32);
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
MVT::i32);
return true; return true;
} }
// Default case, no offset // Default case, no offset
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
SDValue &Offset) { SDValue &Offset) {
ConstantSDNode *C; ConstantSDNode *C;
SDLoc DL(Addr);
if ((C = dyn_cast<ConstantSDNode>(Addr))) { if ((C = dyn_cast<ConstantSDNode>(Addr))) {
Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32); Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) && } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
(C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) { (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32); Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
} else { } else {
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, DL, MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
} }
return true; return true;
@ -758,8 +751,8 @@ SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
bool IsAdd = (N->getOpcode() == ISD::ADD); bool IsAdd = (N->getOpcode() == ISD::ADD);
SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
DL, MVT::i32, LHS, Sub0); DL, MVT::i32, LHS, Sub0);
@ -785,7 +778,7 @@ SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
SDValue(Hi0, 0), SDValue(Hi1, 0), Carry); SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
SDValue Args[5] = { SDValue Args[5] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
SDValue(AddLo,0), SDValue(AddLo,0),
Sub0, Sub0,
SDValue(AddHi,0), SDValue(AddHi,0),
@ -842,17 +835,15 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
} }
} }
SDLoc DL(Addr);
// If we have a constant address, prefer to put the constant into the // If we have a constant address, prefer to put the constant into the
// offset. This can save moves to load the constant address since multiple // offset. This can save moves to load the constant address since multiple
// operations can share the zero base address register, and enables merging // operations can share the zero base address register, and enables merging
// into read2 / write2 instructions. // into read2 / write2 instructions.
if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) { if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
if (isUInt<16>(CAddr->getZExtValue())) { if (isUInt<16>(CAddr->getZExtValue())) {
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
DL, MVT::i32, Zero); SDLoc(Addr), MVT::i32, Zero);
Base = SDValue(MovZero, 0); Base = SDValue(MovZero, 0);
Offset = Addr; Offset = Addr;
return true; return true;
@ -861,15 +852,13 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
// default case // default case
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); Offset = CurDAG->getTargetConstant(0, MVT::i16);
return true; return true;
} }
bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
SDValue &Offset0, SDValue &Offset0,
SDValue &Offset1) const { SDValue &Offset1) const {
SDLoc DL(Addr);
if (CurDAG->isBaseWithConstantOffset(Addr)) { if (CurDAG->isBaseWithConstantOffset(Addr)) {
SDValue N0 = Addr.getOperand(0); SDValue N0 = Addr.getOperand(0);
SDValue N1 = Addr.getOperand(1); SDValue N1 = Addr.getOperand(1);
@ -879,8 +868,8 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
// (add n0, c0) // (add n0, c0)
if (isDSOffsetLegal(N0, DWordOffset1, 8)) { if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
Base = N0; Base = N0;
Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
return true; return true;
} }
} }
@ -891,21 +880,21 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
assert(4 * DWordOffset0 == CAddr->getZExtValue()); assert(4 * DWordOffset0 == CAddr->getZExtValue());
if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) { if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
MachineSDNode *MovZero MachineSDNode *MovZero
= CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
DL, MVT::i32, Zero); SDLoc(Addr), MVT::i32, Zero);
Base = SDValue(MovZero, 0); Base = SDValue(MovZero, 0);
Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
return true; return true;
} }
} }
// default case // default case
Base = Addr; Base = Addr;
Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8); Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
return true; return true;
} }
@ -921,14 +910,14 @@ void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
SDValue &TFE) const { SDValue &TFE) const {
SDLoc DL(Addr); SDLoc DL(Addr);
GLC = CurDAG->getTargetConstant(0, DL, MVT::i1); GLC = CurDAG->getTargetConstant(0, MVT::i1);
SLC = CurDAG->getTargetConstant(0, DL, MVT::i1); SLC = CurDAG->getTargetConstant(0, MVT::i1);
TFE = CurDAG->getTargetConstant(0, DL, MVT::i1); TFE = CurDAG->getTargetConstant(0, MVT::i1);
Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1); Idxen = CurDAG->getTargetConstant(0, MVT::i1);
Offen = CurDAG->getTargetConstant(0, DL, MVT::i1); Offen = CurDAG->getTargetConstant(0, MVT::i1);
Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1); Addr64 = CurDAG->getTargetConstant(0, MVT::i1);
SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); SOffset = CurDAG->getTargetConstant(0, MVT::i32);
if (CurDAG->isBaseWithConstantOffset(Addr)) { if (CurDAG->isBaseWithConstantOffset(Addr)) {
SDValue N0 = Addr.getOperand(0); SDValue N0 = Addr.getOperand(0);
@ -939,25 +928,24 @@ void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
// (add (add N2, N3), C1) -> addr64 // (add (add N2, N3), C1) -> addr64
SDValue N2 = N0.getOperand(0); SDValue N2 = N0.getOperand(0);
SDValue N3 = N0.getOperand(1); SDValue N3 = N0.getOperand(1);
Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1); Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
Ptr = N2; Ptr = N2;
VAddr = N3; VAddr = N3;
} else { } else {
// (add N0, C1) -> offset // (add N0, C1) -> offset
VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32); VAddr = CurDAG->getTargetConstant(0, MVT::i32);
Ptr = N0; Ptr = N0;
} }
if (isLegalMUBUFImmOffset(C1)) { if (isLegalMUBUFImmOffset(C1)) {
Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
return; return;
} else if (isUInt<32>(C1->getZExtValue())) { } else if (isUInt<32>(C1->getZExtValue())) {
// Illegal offset, store it in soffset. // Illegal offset, store it in soffset.
Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); Offset = CurDAG->getTargetConstant(0, MVT::i16);
SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)), CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i32)), 0);
0);
return; return;
} }
} }
@ -966,17 +954,17 @@ void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
// (add N0, N1) -> addr64 // (add N0, N1) -> addr64
SDValue N0 = Addr.getOperand(0); SDValue N0 = Addr.getOperand(0);
SDValue N1 = Addr.getOperand(1); SDValue N1 = Addr.getOperand(1);
Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1); Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
Ptr = N0; Ptr = N0;
VAddr = N1; VAddr = N1;
Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); Offset = CurDAG->getTargetConstant(0, MVT::i16);
return; return;
} }
// default case -> offset // default case -> offset
VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32); VAddr = CurDAG->getTargetConstant(0, MVT::i32);
Ptr = Addr; Ptr = Addr;
Offset = CurDAG->getTargetConstant(0, DL, MVT::i16); Offset = CurDAG->getTargetConstant(0, MVT::i16);
} }
@ -1007,7 +995,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset, SDValue &VAddr, SDValue &SOffset,
SDValue &Offset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1); SLC = CurDAG->getTargetConstant(0, MVT::i1);
SDValue GLC, TFE; SDValue GLC, TFE;
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE); return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
@ -1038,11 +1026,11 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0); SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
const SDValue RsrcOps[] = { const SDValue RsrcOps[] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
ScratchRsrcDword0, ScratchRsrcDword0,
CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
ScratchRsrcDword1, ScratchRsrcDword1,
CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
}; };
SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
MVT::v2i32, RsrcOps), 0); MVT::v2i32, RsrcOps), 0);
@ -1057,14 +1045,14 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
if (isLegalMUBUFImmOffset(C1)) { if (isLegalMUBUFImmOffset(C1)) {
VAddr = Addr.getOperand(0); VAddr = Addr.getOperand(0);
ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
return true; return true;
} }
} }
// (node) // (node)
VAddr = Addr; VAddr = Addr;
ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
return true; return true;
} }
@ -1137,7 +1125,7 @@ SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
DL, DL,
DestVT, DestVT,
Src, Src,
CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32)); CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
} }
@ -1146,20 +1134,19 @@ SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
// FIXME: This is probably wrong, we should never be defining // FIXME: This is probably wrong, we should never be defining
// a register class with both VGPRs and SGPRs // a register class with both VGPRs and SGPRs
SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, DL, SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, MVT::i32);
MVT::i32);
const SDValue Ops[] = { const SDValue Ops[] = {
RC, RC,
Src, Src,
CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
CurDAG->getConstant(0, DL, MVT::i32)), 0), CurDAG->getConstant(0, MVT::i32)), 0),
CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32) CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
}; };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
DL, N->getValueType(0), Ops); SDLoc(N), N->getValueType(0), Ops);
} }
assert(SrcSize == 64 && DestSize == 64); assert(SrcSize == 64 && DestSize == 64);
@ -1172,7 +1159,7 @@ SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
// the format expected by the S_BFE_I32 / S_BFE_U32. In the second // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
// source, bits [5:0] contain the offset and bits [22:16] the width. // source, bits [5:0] contain the offset and bits [22:16] the width.
uint32_t PackedVal = Offset | (Width << 16); uint32_t PackedVal = Offset | (Width << 16);
SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32); SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, MVT::i32);
return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst); return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
} }
@ -1272,7 +1259,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
Src = Src.getOperand(0); Src = Src.getOperand(0);
} }
SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32); SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
return true; return true;
} }
@ -1280,10 +1267,9 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src, bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
SDValue &SrcMods, SDValue &Clamp, SDValue &SrcMods, SDValue &Clamp,
SDValue &Omod) const { SDValue &Omod) const {
SDLoc DL(In);
// FIXME: Handle Clamp and Omod // FIXME: Handle Clamp and Omod
Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32); Clamp = CurDAG->getTargetConstant(0, MVT::i32);
Omod = CurDAG->getTargetConstant(0, DL, MVT::i32); Omod = CurDAG->getTargetConstant(0, MVT::i32);
return SelectVOP3Mods(In, Src, SrcMods); return SelectVOP3Mods(In, Src, SrcMods);
} }
@ -1292,7 +1278,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
SDValue &SrcMods, SDValue &SrcMods,
SDValue &Omod) const { SDValue &Omod) const {
// FIXME: Handle Omod // FIXME: Handle Omod
Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32); Omod = CurDAG->getTargetConstant(0, MVT::i32);
return SelectVOP3Mods(In, Src, SrcMods); return SelectVOP3Mods(In, Src, SrcMods);
} }
@ -1301,7 +1287,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
SDValue &SrcMods, SDValue &SrcMods,
SDValue &Clamp, SDValue &Clamp,
SDValue &Omod) const { SDValue &Omod) const {
Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32); Clamp = Omod = CurDAG->getTargetConstant(0, MVT::i32);
return SelectVOP3Mods(In, Src, SrcMods); return SelectVOP3Mods(In, Src, SrcMods);
} }

208
llvm/lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -680,7 +680,7 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) { if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
EVT VT = EVT::getEVT(InitTy); EVT VT = EVT::getEVT(InitTy);
PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS); PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr, return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
MachinePointerInfo(UndefValue::get(PtrTy)), false, false, MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
TD->getPrefTypeAlignment(InitTy)); TD->getPrefTypeAlignment(InitTy));
} }
@ -688,7 +688,7 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) { if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
EVT VT = EVT::getEVT(CFP->getType()); EVT VT = EVT::getEVT(CFP->getType());
PointerType *PtrTy = PointerType::get(CFP->getType(), 0); PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr, return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
MachinePointerInfo(UndefValue::get(PtrTy)), false, false, MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
TD->getPrefTypeAlignment(CFP->getType())); TD->getPrefTypeAlignment(CFP->getType()));
} }
@ -700,7 +700,7 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
SmallVector<SDValue, 8> Chains; SmallVector<SDValue, 8> Chains;
for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) { for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT); SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
Constant *Elt = Init->getAggregateElement(I); Constant *Elt = Init->getAggregateElement(I);
@ -724,7 +724,7 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType()); unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
SmallVector<SDValue, 8> Chains; SmallVector<SDValue, 8> Chains;
for (unsigned i = 0; i < NumElements; ++i) { for (unsigned i = 0; i < NumElements; ++i) {
SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT); SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
Constant *Elt = Init->getAggregateElement(i); Constant *Elt = Init->getAggregateElement(i);
@ -786,8 +786,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
Offset = MFI->LocalMemoryObjects[GV]; Offset = MFI->LocalMemoryObjects[GV];
} }
return DAG.getConstant(Offset, SDLoc(Op), return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
} }
case AMDGPUAS::CONSTANT_ADDRESS: { case AMDGPUAS::CONSTANT_ADDRESS: {
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
@ -869,7 +868,7 @@ SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
unsigned FrameIndex = FIN->getIndex(); unsigned FrameIndex = FIN->getIndex();
unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex); unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op), return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
Op.getValueType()); Op.getValueType());
} }
@ -944,9 +943,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
DAG.getConstantFP(Max, DL, VT)); DAG.getConstantFP(Max, VT));
return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
DAG.getConstantFP(Min, DL, VT)); DAG.getConstantFP(Min, VT));
} else { } else {
return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1)); return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
} }
@ -1041,8 +1040,8 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
Op.getOperand(1)); Op.getOperand(1));
return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
} }
@ -1054,7 +1053,7 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
SDLoc DL(Op); SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
DAG.getConstantFP(1.0f, DL, MVT::f32), DAG.getConstantFP(1.0f, MVT::f32),
Op.getOperand(1)); Op.getOperand(1));
SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
Op.getOperand(3)); Op.getOperand(3));
@ -1202,7 +1201,7 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(), SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
DAG.getConstant(i * MemEltSize, SL, PtrVT)); DAG.getConstant(i * MemEltSize, PtrVT));
SDValue NewLoad SDValue NewLoad
= DAG.getExtLoad(Load->getExtensionType(), SL, EltVT, = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
@ -1253,8 +1252,7 @@ SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
Load->isInvariant(), Load->getAlignment()); Load->isInvariant(), Load->getAlignment());
SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
DAG.getConstant(LoMemVT.getStoreSize(), SL, DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
PtrVT));
SDValue HiLoad SDValue HiLoad
= DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
@ -1294,18 +1292,18 @@ SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
unsigned MemEltBits = MemEltVT.getSizeInBits(); unsigned MemEltBits = MemEltVT.getSizeInBits();
unsigned MemNumElements = MemVT.getVectorNumElements(); unsigned MemNumElements = MemVT.getVectorNumElements();
unsigned PackedSize = MemVT.getStoreSizeInBits(); unsigned PackedSize = MemVT.getStoreSizeInBits();
SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32); SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
assert(Value.getValueType().getScalarSizeInBits() >= 32); assert(Value.getValueType().getScalarSizeInBits() >= 32);
SDValue PackedValue; SDValue PackedValue;
for (unsigned i = 0; i < MemNumElements; ++i) { for (unsigned i = 0; i < MemNumElements; ++i) {
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
DAG.getConstant(i, DL, MVT::i32)); DAG.getConstant(i, MVT::i32));
Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32); Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32); SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift); Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
if (i == 0) { if (i == 0) {
@ -1347,9 +1345,9 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
for (unsigned i = 0, e = NumElts; i != e; ++i) { for (unsigned i = 0, e = NumElts; i != e; ++i) {
SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
Store->getValue(), Store->getValue(),
DAG.getConstant(i, SL, MVT::i32)); DAG.getConstant(i, MVT::i32));
SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT); SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset); SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
SDValue NewStore = SDValue NewStore =
DAG.getTruncStore(Store->getChain(), SL, Val, Ptr, DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
@ -1388,8 +1386,7 @@ SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
EVT PtrVT = BasePtr.getValueType(); EVT PtrVT = BasePtr.getValueType();
SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
DAG.getConstant(LoMemVT.getStoreSize(), SL, DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
PtrVT));
MachinePointerInfo SrcValue(Store->getMemOperand()->getValue()); MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
SDValue LoStore SDValue LoStore
@ -1447,16 +1444,16 @@ SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(), SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
Load->getChain(), Ptr, Load->getChain(), Ptr,
DAG.getTargetConstant(0, DL, MVT::i32), DAG.getTargetConstant(0, MVT::i32),
Op.getOperand(2)); Op.getOperand(2));
SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
Load->getBasePtr(), Load->getBasePtr(),
DAG.getConstant(0x3, DL, MVT::i32)); DAG.getConstant(0x3, MVT::i32));
SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
DAG.getConstant(3, DL, MVT::i32)); DAG.getConstant(3, MVT::i32));
Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt); Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
@ -1506,16 +1503,15 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
} }
SDValue BasePtr = Store->getBasePtr(); SDValue BasePtr = Store->getBasePtr();
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr, SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32, SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
Chain, Ptr, Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
DAG.getTargetConstant(0, DL, MVT::i32));
SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr, SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
DAG.getConstant(0x3, DL, MVT::i32)); DAG.getConstant(0x3, MVT::i32));
SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
DAG.getConstant(3, DL, MVT::i32)); DAG.getConstant(3, MVT::i32));
SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
Store->getValue()); Store->getValue());
@ -1525,17 +1521,15 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
MaskedValue, ShiftAmt); MaskedValue, ShiftAmt);
SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
DAG.getConstant(Mask, DL, MVT::i32),
ShiftAmt); ShiftAmt);
DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask, DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
DAG.getConstant(0xffffffff, DL, MVT::i32)); DAG.getConstant(0xffffffff, MVT::i32));
Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
Chain, Value, Ptr, Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
DAG.getTargetConstant(0, DL, MVT::i32));
} }
return SDValue(); return SDValue();
} }
@ -1562,18 +1556,17 @@ SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool
unsigned BitSize = VT.getScalarType().getSizeInBits(); unsigned BitSize = VT.getScalarType().getSizeInBits();
SDValue jq = DAG.getConstant(1, DL, IntVT); SDValue jq = DAG.getConstant(1, IntVT);
if (sign) { if (sign) {
// char|short jq = ia ^ ib; // char|short jq = ia ^ ib;
jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS); jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
// jq = jq >> (bitsize - 2) // jq = jq >> (bitsize - 2)
jq = DAG.getNode(ISD::SRA, DL, VT, jq, jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
DAG.getConstant(BitSize - 2, DL, VT));
// jq = jq | 0x1 // jq = jq | 0x1
jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
// jq = (int)jq // jq = (int)jq
jq = DAG.getSExtOrTrunc(jq, DL, IntVT); jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
@ -1622,7 +1615,7 @@ SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool
SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
// jq = (cv ? jq : 0); // jq = (cv ? jq : 0);
jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT)); jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
// dst = trunc/extend to legal type // dst = trunc/extend to legal type
iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT); iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
@ -1650,8 +1643,8 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
SDValue one = DAG.getConstant(1, DL, HalfVT); SDValue one = DAG.getConstant(1, HalfVT);
SDValue zero = DAG.getConstant(0, DL, HalfVT); SDValue zero = DAG.getConstant(0, HalfVT);
//HiLo split //HiLo split
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
@ -1690,18 +1683,18 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
for (unsigned i = 0; i < halfBitWidth; ++i) { for (unsigned i = 0; i < halfBitWidth; ++i) {
const unsigned bitPos = halfBitWidth - i - 1; const unsigned bitPos = halfBitWidth - i - 1;
SDValue POS = DAG.getConstant(bitPos, DL, HalfVT); SDValue POS = DAG.getConstant(bitPos, HalfVT);
// Get value of high bit // Get value of high bit
SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one); HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
// Shift // Shift
REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, VT));
// Add LHS high bit // Add LHS high bit
REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT); SDValue BIT = DAG.getConstant(1 << bitPos, HalfVT);
SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE); SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT); DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
@ -1751,11 +1744,11 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
// NEG_RCP_LO = -RCP_LO // NEG_RCP_LO = -RCP_LO
SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
RCP_LO); RCP_LO);
// ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO) // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
NEG_RCP_LO, RCP_LO, NEG_RCP_LO, RCP_LO,
ISD::SETEQ); ISD::SETEQ);
// Calculate the rounding error from the URECIP instruction // Calculate the rounding error from the URECIP instruction
@ -1769,7 +1762,7 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
// Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E) // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
RCP_A_E, RCP_S_E, RCP_A_E, RCP_S_E,
ISD::SETEQ); ISD::SETEQ);
// Quotient = mulhu(Tmp0, Num) // Quotient = mulhu(Tmp0, Num)
@ -1783,14 +1776,14 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
// Remainder_GE_Den = (Remainder >= Den ? -1 : 0) // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den, SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
DAG.getConstant(-1, DL, VT), DAG.getConstant(-1, VT),
DAG.getConstant(0, DL, VT), DAG.getConstant(0, VT),
ISD::SETUGE); ISD::SETUGE);
// Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0) // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num, SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
Num_S_Remainder, Num_S_Remainder,
DAG.getConstant(-1, DL, VT), DAG.getConstant(-1, VT),
DAG.getConstant(0, DL, VT), DAG.getConstant(0, VT),
ISD::SETUGE); ISD::SETUGE);
// Tmp1 = Remainder_GE_Den & Remainder_GE_Zero // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
@ -1800,18 +1793,18 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
// Quotient_A_One = Quotient + 1 // Quotient_A_One = Quotient + 1
SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient, SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, VT));
// Quotient_S_One = Quotient - 1 // Quotient_S_One = Quotient - 1
SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, VT));
// Div = (Tmp1 == 0 ? Quotient : Quotient_A_One) // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
Quotient, Quotient_A_One, ISD::SETEQ); Quotient, Quotient_A_One, ISD::SETEQ);
// Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div) // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT), Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
Quotient_S_One, Div, ISD::SETEQ); Quotient_S_One, Div, ISD::SETEQ);
// Calculate Rem result: // Calculate Rem result:
@ -1823,11 +1816,11 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den); SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
// Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den) // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
Remainder, Remainder_S_Den, ISD::SETEQ); Remainder, Remainder_S_Den, ISD::SETEQ);
// Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem) // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT), Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
Remainder_A_Den, Rem, ISD::SETEQ); Remainder_A_Den, Rem, ISD::SETEQ);
SDValue Ops[2] = { SDValue Ops[2] = {
Div, Div,
@ -1844,8 +1837,8 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant(0, DL, VT); SDValue Zero = DAG.getConstant(0, VT);
SDValue NegOne = DAG.getConstant(-1, DL, VT); SDValue NegOne = DAG.getConstant(-1, VT);
if (VT == MVT::i32 && if (VT == MVT::i32 &&
DAG.ComputeNumSignBits(LHS) > 8 && DAG.ComputeNumSignBits(LHS) > 8 &&
@ -1920,8 +1913,8 @@ SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
@ -1939,10 +1932,10 @@ static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
Hi, Hi,
DAG.getConstant(FractBits - 32, SL, MVT::i32), DAG.getConstant(FractBits - 32, MVT::i32),
DAG.getConstant(ExpBits, SL, MVT::i32)); DAG.getConstant(ExpBits, MVT::i32));
SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
DAG.getConstant(1023, SL, MVT::i32)); DAG.getConstant(1023, MVT::i32));
return Exp; return Exp;
} }
@ -1953,8 +1946,8 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::f64); assert(Op.getValueType() == MVT::f64);
const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); const SDValue Zero = DAG.getConstant(0, MVT::i32);
const SDValue One = DAG.getConstant(1, SL, MVT::i32); const SDValue One = DAG.getConstant(1, MVT::i32);
SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
@ -1967,7 +1960,7 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
const unsigned FractBits = 52; const unsigned FractBits = 52;
// Extract the sign bit. // Extract the sign bit.
const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
// Extend back to to 64-bits. // Extend back to to 64-bits.
@ -1977,7 +1970,7 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
const SDValue FractMask const SDValue FractMask
= DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
@ -1985,7 +1978,7 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
@ -2003,7 +1996,7 @@ SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::f64); assert(Op.getValueType() == MVT::f64);
APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52"); APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
@ -2012,7 +2005,7 @@ SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51"); APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
@ -2038,9 +2031,9 @@ SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const
SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff); SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32); const SDValue Zero = DAG.getConstantFP(0.0, MVT::f32);
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); const SDValue One = DAG.getConstantFP(1.0, MVT::f32);
const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32); const SDValue Half = DAG.getConstantFP(0.5, MVT::f32);
SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X); SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
@ -2059,10 +2052,10 @@ SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X); SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); const SDValue Zero = DAG.getConstant(0, MVT::i32);
const SDValue One = DAG.getConstant(1, SL, MVT::i32); const SDValue One = DAG.getConstant(1, MVT::i32);
const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32); const SDValue NegOne = DAG.getConstant(-1, MVT::i32);
const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32); const SDValue FiftyOne = DAG.getConstant(51, MVT::i32);
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
@ -2072,22 +2065,20 @@ SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue Exp = extractF64Exponent(Hi, SL, DAG); SDValue Exp = extractF64Exponent(Hi, SL, DAG);
const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL, const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), MVT::i64);
MVT::i64);
SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
DAG.getConstant(INT64_C(0x0008000000000000), SL, DAG.getConstant(INT64_C(0x0008000000000000), MVT::i64),
MVT::i64),
Exp); Exp);
SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
DAG.getConstant(0, SL, MVT::i64), Tmp0, DAG.getConstant(0, MVT::i64), Tmp0,
ISD::SETNE); ISD::SETNE);
SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
D, DAG.getConstant(0, SL, MVT::i64)); D, DAG.getConstant(0, MVT::i64));
SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2); SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64)); K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
@ -2099,8 +2090,8 @@ SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64, SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
ExpEqNegOne, ExpEqNegOne,
DAG.getConstantFP(1.0, SL, MVT::f64), DAG.getConstantFP(1.0, MVT::f64),
DAG.getConstantFP(0.0, SL, MVT::f64)); DAG.getConstantFP(0.0, MVT::f64));
SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X); SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
@ -2132,8 +2123,8 @@ SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
@ -2153,9 +2144,9 @@ SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
DAG.getConstant(0, SL, MVT::i32)); DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
DAG.getConstant(1, SL, MVT::i32)); DAG.getConstant(1, MVT::i32));
SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
SL, MVT::f64, Hi); SL, MVT::f64, Hi);
@ -2163,7 +2154,7 @@ SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi, SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
DAG.getConstant(32, SL, MVT::i32)); DAG.getConstant(32, MVT::i32));
return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
} }
@ -2184,13 +2175,13 @@ SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
// f32 uint_to_fp i64 // f32 uint_to_fp i64
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, MVT::i32));
SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi); SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi, FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi); return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
} }
@ -2211,10 +2202,10 @@ SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL, SDValue K0
MVT::f64); = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL, SDValue K1
MVT::f64); = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0); SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
@ -2313,14 +2304,14 @@ static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
template <typename IntTy> template <typename IntTy>
static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
uint32_t Offset, uint32_t Width, SDLoc DL) { uint32_t Offset, uint32_t Width) {
if (Width + Offset < 32) { if (Width + Offset < 32) {
uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width); uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width); IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
return DAG.getConstant(Result, DL, MVT::i32); return DAG.getConstant(Result, MVT::i32);
} }
return DAG.getConstant(Src0 >> Offset, DL, MVT::i32); return DAG.getConstant(Src0 >> Offset, MVT::i32);
} }
static bool usesAllNormalStores(SDNode *LoadVal) { static bool usesAllNormalStores(SDNode *LoadVal) {
@ -2425,6 +2416,7 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SELECT: { case ISD::SELECT: {
SDValue Cond = N->getOperand(0); SDValue Cond = N->getOperand(0);
if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) { if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue LHS = Cond.getOperand(0); SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1); SDValue RHS = Cond.getOperand(1);
@ -2455,7 +2447,7 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
uint32_t WidthVal = Width->getZExtValue() & 0x1f; uint32_t WidthVal = Width->getZExtValue() & 0x1f;
if (WidthVal == 0) if (WidthVal == 0)
return DAG.getConstant(0, DL, MVT::i32); return DAG.getConstant(0, MVT::i32);
ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (!Offset) if (!Offset)
@ -2494,19 +2486,17 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
return constantFoldBFE<int32_t>(DAG, return constantFoldBFE<int32_t>(DAG,
CVal->getSExtValue(), CVal->getSExtValue(),
OffsetVal, OffsetVal,
WidthVal, WidthVal);
DL);
} }
return constantFoldBFE<uint32_t>(DAG, return constantFoldBFE<uint32_t>(DAG,
CVal->getZExtValue(), CVal->getZExtValue(),
OffsetVal, OffsetVal,
WidthVal, WidthVal);
DL);
} }
if ((OffsetVal + WidthVal) >= 32) { if ((OffsetVal + WidthVal) >= 32) {
SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
BitsFrom, ShiftVal); BitsFrom, ShiftVal);
} }

2
llvm/lib/Target/R600/AMDGPUInstructions.td
View File

@ -583,7 +583,7 @@ def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
}]>; }]>;
def IMMPopCount : SDNodeXForm<imm, [{ def IMMPopCount : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()),
MVT::i32); MVT::i32);
}]>; }]>;

202
llvm/lib/Target/R600/R600ISelLowering.cpp
View File

@ -611,18 +611,17 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2)); return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
} }
case AMDGPUIntrinsic::R600_store_swizzle: { case AMDGPUIntrinsic::R600_store_swizzle: {
SDLoc DL(Op);
const SDValue Args[8] = { const SDValue Args[8] = {
Chain, Chain,
Op.getOperand(2), // Export Value Op.getOperand(2), // Export Value
Op.getOperand(3), // ArrayBase Op.getOperand(3), // ArrayBase
Op.getOperand(4), // Type Op.getOperand(4), // Type
DAG.getConstant(0, DL, MVT::i32), // SWZ_X DAG.getConstant(0, MVT::i32), // SWZ_X
DAG.getConstant(1, DL, MVT::i32), // SWZ_Y DAG.getConstant(1, MVT::i32), // SWZ_Y
DAG.getConstant(2, DL, MVT::i32), // SWZ_Z DAG.getConstant(2, MVT::i32), // SWZ_Z
DAG.getConstant(3, DL, MVT::i32) // SWZ_W DAG.getConstant(3, MVT::i32) // SWZ_W
}; };
return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
} }
// default for switch(IntrinsicID) // default for switch(IntrinsicID)
@ -656,7 +655,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
const R600InstrInfo *TII = const R600InstrInfo *TII =
static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo()); static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32)); MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
return DAG.getTargetExtractSubreg( return DAG.getTargetExtractSubreg(
TII->getRegisterInfo().getSubRegFromChannel(slot % 4), TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
DL, MVT::f32, SDValue(interp, 0)); DL, MVT::f32, SDValue(interp, 0));
@ -674,11 +673,11 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
if (slot % 4 < 2) if (slot % 4 < 2)
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
RegisterJNode, RegisterINode); RegisterJNode, RegisterINode);
else else
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
RegisterJNode, RegisterINode); RegisterJNode, RegisterINode);
return SDValue(interp, slot % 2); return SDValue(interp, slot % 2);
} }
@ -691,11 +690,11 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy) if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
RegisterJNode, RegisterINode); RegisterJNode, RegisterINode);
else else
interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
RegisterJNode, RegisterINode); RegisterJNode, RegisterINode);
return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
SDValue(interp, 0), SDValue(interp, 1)); SDValue(interp, 0), SDValue(interp, 1));
@ -751,19 +750,19 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
} }
SDValue TexArgs[19] = { SDValue TexArgs[19] = {
DAG.getConstant(TextureOp, DL, MVT::i32), DAG.getConstant(TextureOp, MVT::i32),
Op.getOperand(1), Op.getOperand(1),
DAG.getConstant(0, DL, MVT::i32), DAG.getConstant(0, MVT::i32),
DAG.getConstant(1, DL, MVT::i32), DAG.getConstant(1, MVT::i32),
DAG.getConstant(2, DL, MVT::i32), DAG.getConstant(2, MVT::i32),
DAG.getConstant(3, DL, MVT::i32), DAG.getConstant(3, MVT::i32),
Op.getOperand(2), Op.getOperand(2),
Op.getOperand(3), Op.getOperand(3),
Op.getOperand(4), Op.getOperand(4),
DAG.getConstant(0, DL, MVT::i32), DAG.getConstant(0, MVT::i32),
DAG.getConstant(1, DL, MVT::i32), DAG.getConstant(1, MVT::i32),
DAG.getConstant(2, DL, MVT::i32), DAG.getConstant(2, MVT::i32),
DAG.getConstant(3, DL, MVT::i32), DAG.getConstant(3, MVT::i32),
Op.getOperand(5), Op.getOperand(5),
Op.getOperand(6), Op.getOperand(6),
Op.getOperand(7), Op.getOperand(7),
@ -776,21 +775,21 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
case AMDGPUIntrinsic::AMDGPU_dp4: { case AMDGPUIntrinsic::AMDGPU_dp4: {
SDValue Args[8] = { SDValue Args[8] = {
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
DAG.getConstant(0, DL, MVT::i32)), DAG.getConstant(0, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
DAG.getConstant(0, DL, MVT::i32)), DAG.getConstant(0, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
DAG.getConstant(1, DL, MVT::i32)), DAG.getConstant(1, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
DAG.getConstant(1, DL, MVT::i32)), DAG.getConstant(1, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
DAG.getConstant(2, DL, MVT::i32)), DAG.getConstant(2, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
DAG.getConstant(2, DL, MVT::i32)), DAG.getConstant(2, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
DAG.getConstant(3, DL, MVT::i32)), DAG.getConstant(3, MVT::i32)),
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
DAG.getConstant(3, DL, MVT::i32)) DAG.getConstant(3, MVT::i32))
}; };
return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
} }
@ -932,8 +931,8 @@ SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
for (unsigned i = 0, e = VecVT.getVectorNumElements(); for (unsigned i = 0, e = VecVT.getVectorNumElements();
i != e; ++i) { i != e; ++i) {
Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
DAG.getConstant(i, DL, getVectorIdxTy()))); Vector, DAG.getConstant(i, getVectorIdxTy())));
} }
return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
@ -977,12 +976,11 @@ SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
// Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5) // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue Arg = Op.getOperand(0); SDValue Arg = Op.getOperand(0);
SDLoc DL(Op); SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, DAG.getNode(ISD::FADD, SDLoc(Op), VT,
DAG.getNode(ISD::FADD, DL, VT, DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
DAG.getNode(ISD::FMUL, DL, VT, Arg, DAG.getConstantFP(0.15915494309, MVT::f32)),
DAG.getConstantFP(0.15915494309, DL, MVT::f32)), DAG.getConstantFP(0.5, MVT::f32)));
DAG.getConstantFP(0.5, DL, MVT::f32)));
unsigned TrigNode; unsigned TrigNode;
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::FCOS: case ISD::FCOS:
@ -994,14 +992,14 @@ SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
default: default:
llvm_unreachable("Wrong trig opcode"); llvm_unreachable("Wrong trig opcode");
} }
SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
DAG.getNode(ISD::FADD, DL, VT, FractPart, DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
DAG.getConstantFP(-0.5, DL, MVT::f32))); DAG.getConstantFP(-0.5, MVT::f32)));
if (Gen >= AMDGPUSubtarget::R700) if (Gen >= AMDGPUSubtarget::R700)
return TrigVal; return TrigVal;
// On R600 hw, COS/SIN input must be between -Pi and Pi. // On R600 hw, COS/SIN input must be between -Pi and Pi.
return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
DAG.getConstantFP(3.14159265359, DL, MVT::f32)); DAG.getConstantFP(3.14159265359, MVT::f32));
} }
SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const { SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
@ -1011,11 +1009,11 @@ SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
SDValue Lo = Op.getOperand(0); SDValue Lo = Op.getOperand(0);
SDValue Hi = Op.getOperand(1); SDValue Hi = Op.getOperand(1);
SDValue Shift = Op.getOperand(2); SDValue Shift = Op.getOperand(2);
SDValue Zero = DAG.getConstant(0, DL, VT); SDValue Zero = DAG.getConstant(0, VT);
SDValue One = DAG.getConstant(1, DL, VT); SDValue One = DAG.getConstant(1, VT);
SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
@ -1047,13 +1045,13 @@ SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
SDValue Lo = Op.getOperand(0); SDValue Lo = Op.getOperand(0);
SDValue Hi = Op.getOperand(1); SDValue Hi = Op.getOperand(1);
SDValue Shift = Op.getOperand(2); SDValue Shift = Op.getOperand(2);
SDValue Zero = DAG.getConstant(0, DL, VT); SDValue Zero = DAG.getConstant(0, VT);
SDValue One = DAG.getConstant(1, DL, VT); SDValue One = DAG.getConstant(1, VT);
const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
@ -1079,12 +1077,11 @@ SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
} }
SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const { SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
return DAG.getNode( return DAG.getNode(
ISD::SETCC, ISD::SETCC,
DL, SDLoc(Op),
MVT::i1, MVT::i1,
Op, DAG.getConstantFP(0.0f, DL, MVT::f32), Op, DAG.getConstantFP(0.0f, MVT::f32),
DAG.getCondCode(ISD::SETNE) DAG.getCondCode(ISD::SETNE)
); );
} }
@ -1100,7 +1097,7 @@ SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
assert(isInt<16>(ByteOffset)); assert(isInt<16>(ByteOffset));
return DAG.getLoad(VT, DL, DAG.getEntryNode(), return DAG.getLoad(VT, DL, DAG.getEntryNode(),
DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR DAG.getConstant(ByteOffset, MVT::i32), // PTR
MachinePointerInfo(ConstantPointerNull::get(PtrType)), MachinePointerInfo(ConstantPointerNull::get(PtrType)),
false, false, false, 0); false, false, false, 0);
} }
@ -1237,11 +1234,11 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue HWTrue, HWFalse; SDValue HWTrue, HWFalse;
if (CompareVT == MVT::f32) { if (CompareVT == MVT::f32) {
HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); HWTrue = DAG.getConstantFP(1.0f, CompareVT);
HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); HWFalse = DAG.getConstantFP(0.0f, CompareVT);
} else if (CompareVT == MVT::i32) { } else if (CompareVT == MVT::i32) {
HWTrue = DAG.getConstant(-1, DL, CompareVT); HWTrue = DAG.getConstant(-1, CompareVT);
HWFalse = DAG.getConstant(0, DL, CompareVT); HWFalse = DAG.getConstant(0, CompareVT);
} }
else { else {
llvm_unreachable("Unhandled value type in LowerSELECT_CC"); llvm_unreachable("Unhandled value type in LowerSELECT_CC");
@ -1279,9 +1276,8 @@ SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
default: llvm_unreachable("Invalid stack width"); default: llvm_unreachable("Invalid stack width");
} }
SDLoc DL(Ptr); return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, DAG.getConstant(SRLPad, MVT::i32));
DAG.getConstant(SRLPad, DL, MVT::i32));
} }
void R600TargetLowering::getStackAddress(unsigned StackWidth, void R600TargetLowering::getStackAddress(unsigned StackWidth,
@ -1332,26 +1328,26 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
EVT MemVT = StoreNode->getMemoryVT(); EVT MemVT = StoreNode->getMemoryVT();
SDValue MaskConstant; SDValue MaskConstant;
if (MemVT == MVT::i8) { if (MemVT == MVT::i8) {
MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); MaskConstant = DAG.getConstant(0xFF, MVT::i32);
} else { } else {
assert(MemVT == MVT::i16); assert(MemVT == MVT::i16);
MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
} }
SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr, SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
DAG.getConstant(0x00000003, DL, VT)); DAG.getConstant(0x00000003, VT));
SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
DAG.getConstant(3, DL, VT)); DAG.getConstant(3, VT));
SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift); SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
// XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
// vector instead. // vector instead.
SDValue Src[4] = { SDValue Src[4] = {
ShiftedValue, ShiftedValue,
DAG.getConstant(0, DL, MVT::i32), DAG.getConstant(0, MVT::i32),
DAG.getConstant(0, DL, MVT::i32), DAG.getConstant(0, MVT::i32),
Mask Mask
}; };
SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src); SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
@ -1364,7 +1360,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
// Convert pointer from byte address to dword address. // Convert pointer from byte address to dword address.
Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(), Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
Ptr, DAG.getConstant(2, DL, MVT::i32))); Ptr, DAG.getConstant(2, MVT::i32)));
if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) { if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
llvm_unreachable("Truncated and indexed stores not supported yet"); llvm_unreachable("Truncated and indexed stores not supported yet");
@ -1406,13 +1402,13 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
unsigned Channel, PtrIncr; unsigned Channel, PtrIncr;
getStackAddress(StackWidth, i, Channel, PtrIncr); getStackAddress(StackWidth, i, Channel, PtrIncr);
Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
DAG.getConstant(PtrIncr, DL, MVT::i32)); DAG.getConstant(PtrIncr, MVT::i32));
SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
Value, DAG.getConstant(i, DL, MVT::i32)); Value, DAG.getConstant(i, MVT::i32));
Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
Chain, Elem, Ptr, Chain, Elem, Ptr,
DAG.getTargetConstant(Channel, DL, MVT::i32)); DAG.getTargetConstant(Channel, MVT::i32));
} }
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
} else { } else {
@ -1420,7 +1416,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
} }
Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr, Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
DAG.getTargetConstant(0, DL, MVT::i32)); // Channel DAG.getTargetConstant(0, MVT::i32)); // Channel
} }
return Chain; return Chain;
@ -1493,11 +1489,10 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
SDValue Ptr = DAG.getZExtOrTrunc(LoadNode->getBasePtr(), DL, SDValue Ptr = DAG.getZExtOrTrunc(LoadNode->getBasePtr(), DL,
getPointerTy(AMDGPUAS::PRIVATE_ADDRESS)); getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, MVT::i32));
return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(), return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
LoadNode->getChain(), Ptr, LoadNode->getChain(), Ptr,
DAG.getTargetConstant(0, DL, MVT::i32), DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
Op.getOperand(2));
} }
if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) { if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
@ -1524,7 +1519,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
// Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
// then div by 4 at the ISel step // then div by 4 at the ISel step
SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
} }
EVT NewVT = MVT::v4i32; EVT NewVT = MVT::v4i32;
@ -1538,16 +1533,15 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
} else { } else {
// non-constant ptr can't be folded, keeps it as a v4f32 load // non-constant ptr can't be folded, keeps it as a v4f32 load
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
DAG.getConstant(4, DL, MVT::i32)), DAG.getConstant(LoadNode->getAddressSpace() -
DAG.getConstant(LoadNode->getAddressSpace() - AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
); );
} }
if (!VT.isVector()) { if (!VT.isVector()) {
Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
} }
SDValue MergedValues[2] = { SDValue MergedValues[2] = {
@ -1568,8 +1562,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
EVT MemVT = LoadNode->getMemoryVT(); EVT MemVT = LoadNode->getMemoryVT();
assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
SDValue ShiftAmount = SDValue ShiftAmount =
DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), DL, DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
MVT::i32);
SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
LoadNode->getPointerInfo(), MemVT, LoadNode->getPointerInfo(), MemVT,
LoadNode->isVolatile(), LoadNode->isVolatile(),
@ -1607,10 +1600,10 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
unsigned Channel, PtrIncr; unsigned Channel, PtrIncr;
getStackAddress(StackWidth, i, Channel, PtrIncr); getStackAddress(StackWidth, i, Channel, PtrIncr);
Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
DAG.getConstant(PtrIncr, DL, MVT::i32)); DAG.getConstant(PtrIncr, MVT::i32));
Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT, Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
Chain, Ptr, Chain, Ptr,
DAG.getTargetConstant(Channel, DL, MVT::i32), DAG.getTargetConstant(Channel, MVT::i32),
Op.getOperand(2)); Op.getOperand(2));
} }
for (unsigned i = NumElemVT; i < 4; ++i) { for (unsigned i = NumElemVT; i < 4; ++i) {
@ -1621,7 +1614,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
} else { } else {
LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT, LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
Chain, Ptr, Chain, Ptr,
DAG.getTargetConstant(0, DL, MVT::i32), // Channel DAG.getTargetConstant(0, MVT::i32), // Channel
Op.getOperand(2)); Op.getOperand(2));
} }
@ -1710,7 +1703,7 @@ SDValue R600TargetLowering::LowerFormalArguments(
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase); MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
DAG.getConstant(Offset, DL, MVT::i32), DAG.getConstant(Offset, MVT::i32),
DAG.getUNDEF(MVT::i32), DAG.getUNDEF(MVT::i32),
PtrInfo, PtrInfo,
MemVT, false, true, true, 4); MemVT, false, true, true, 4);
@ -1811,8 +1804,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
SDValue Swz[4], SelectionDAG &DAG, SDValue Swz[4], SelectionDAG &DAG) const {
SDLoc DL) const {
assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
// Old -> New swizzle values // Old -> New swizzle values
DenseMap<unsigned, unsigned> SwizzleRemap; DenseMap<unsigned, unsigned> SwizzleRemap;
@ -1821,7 +1813,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue(); unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
if (SwizzleRemap.find(Idx) != SwizzleRemap.end()) if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
} }
SwizzleRemap.clear(); SwizzleRemap.clear();
@ -1829,7 +1821,7 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue(); unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
if (SwizzleRemap.find(Idx) != SwizzleRemap.end()) if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
} }
return BuildVector; return BuildVector;
@ -1875,12 +1867,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(); return SDValue();
} }
SDLoc dl(N); return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0),
SelectCC.getOperand(0), // LHS SelectCC.getOperand(0), // LHS
SelectCC.getOperand(1), // RHS SelectCC.getOperand(1), // RHS
DAG.getConstant(-1, dl, MVT::i32), // True DAG.getConstant(-1, MVT::i32), // True
DAG.getConstant(0, dl, MVT::i32), // False DAG.getConstant(0, MVT::i32), // False
SelectCC.getOperand(4)); // CC SelectCC.getOperand(4)); // CC
break; break;
@ -2023,7 +2014,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(7) // SWZ_W N->getOperand(7) // SWZ_W
}; };
SDLoc DL(N); SDLoc DL(N);
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs); return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
} }
case AMDGPUISD::TEXTURE_FETCH: { case AMDGPUISD::TEXTURE_FETCH: {
@ -2052,9 +2043,9 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(17), N->getOperand(17),
N->getOperand(18), N->getOperand(18),
}; };
SDLoc DL(N); NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); NewArgs);
} }
} }
@ -2073,13 +2064,13 @@ FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
if (!Neg.getNode()) if (!Neg.getNode())
return false; return false;
Src = Src.getOperand(0); Src = Src.getOperand(0);
Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); Neg = DAG.getTargetConstant(1, MVT::i32);
return true; return true;
case AMDGPU::FABS_R600: case AMDGPU::FABS_R600:
if (!Abs.getNode()) if (!Abs.getNode())
return false; return false;
Src = Src.getOperand(0); Src = Src.getOperand(0);
Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); Abs = DAG.getTargetConstant(1, MVT::i32);
return true; return true;
case AMDGPU::CONST_COPY: { case AMDGPU::CONST_COPY: {
unsigned Opcode = ParentNode->getMachineOpcode(); unsigned Opcode = ParentNode->getMachineOpcode();
@ -2175,7 +2166,7 @@ FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
assert(C); assert(C);
if (C->getZExtValue()) if (C->getZExtValue())
return false; return false;
Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
} }
Src = DAG.getRegister(ImmReg, MVT::i32); Src = DAG.getRegister(ImmReg, MVT::i32);
return true; return true;
@ -2258,11 +2249,10 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
AMDGPU::OpName::clamp); AMDGPU::OpName::clamp);
if (ClampIdx < 0) if (ClampIdx < 0)
return Node; return Node;
SDLoc DL(Node);
std::vector<SDValue> Ops(Src->op_begin(), Src->op_end()); std::vector<SDValue> Ops(Src->op_begin(), Src->op_end());
Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32); Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
return DAG.getMachineNode(Src.getMachineOpcode(), DL, return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
Node->getVTList(), Ops); Node->getVTList(), Ops);
} else { } else {
if (!TII->hasInstrModifiers(Opcode)) if (!TII->hasInstrModifiers(Opcode))
return Node; return Node;

3
llvm/lib/Target/R600/R600ISelLowering.h
View File

@ -50,8 +50,7 @@ private:
void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB, void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
MachineRegisterInfo & MRI, unsigned dword_offset) const; MachineRegisterInfo & MRI, unsigned dword_offset) const;
SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG, SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
SDLoc DL) const;
SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const; SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;

90
llvm/lib/Target/R600/SIISelLowering.cpp
View File

@ -384,7 +384,7 @@ SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
SDValue BasePtr = DAG.getCopyFromReg(Chain, SL, SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
MRI.getLiveInVirtReg(InputPtrReg), MVT::i64); MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr, SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
DAG.getConstant(Offset, SL, MVT::i64)); DAG.getConstant(Offset, MVT::i64));
SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS)); SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy)); MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
@ -826,14 +826,14 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32); SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr, SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr, SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, MVT::i32));
SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue), SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
PtrLo, GA); PtrLo, GA);
SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue), SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
PtrHi, DAG.getConstant(0, DL, MVT::i32), PtrHi, DAG.getConstant(0, MVT::i32),
SDValue(Lo.getNode(), 1)); SDValue(Lo.getNode(), 1));
return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
} }
@ -1018,8 +1018,8 @@ SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
SDValue Cond = Op.getOperand(0); SDValue Cond = Op.getOperand(0);
SDValue Zero = DAG.getConstant(0, DL, MVT::i32); SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue One = DAG.getConstant(1, DL, MVT::i32); SDValue One = DAG.getConstant(1, MVT::i32);
SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1)); SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2)); SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
@ -1094,12 +1094,12 @@ SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
const APFloat K0Val(BitsToFloat(0x6f800000)); const APFloat K0Val(BitsToFloat(0x6f800000));
const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32); const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
const APFloat K1Val(BitsToFloat(0x2f800000)); const APFloat K1Val(BitsToFloat(0x2f800000));
const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32); const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); const SDValue One = DAG.getConstantFP(1.0, MVT::f32);
EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32); EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
@ -1124,7 +1124,7 @@ SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
SDValue X = Op.getOperand(0); SDValue X = Op.getOperand(0);
SDValue Y = Op.getOperand(1); SDValue Y = Op.getOperand(1);
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1); SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
@ -1154,7 +1154,7 @@ SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
// Workaround a hardware bug on SI where the condition output from div_scale // Workaround a hardware bug on SI where the condition output from div_scale
// is not usable. // is not usable.
const SDValue Hi = DAG.getConstant(1, SL, MVT::i32); const SDValue Hi = DAG.getConstant(1, MVT::i32);
// Figure out if the scale to use for div_fmas. // Figure out if the scale to use for div_fmas.
SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
@ -1223,13 +1223,11 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
} }
SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const { SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue Arg = Op.getOperand(0); SDValue Arg = Op.getOperand(0);
SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
DAG.getNode(ISD::FMUL, DL, VT, Arg, DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
DAG.getConstantFP(0.5/M_PI, DL, DAG.getConstantFP(0.5 / M_PI, VT)));
VT)));
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::FCOS: case ISD::FCOS:
@ -1419,7 +1417,7 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32); SDValue COffset = DAG.getConstant(Offset, MVT::i32);
return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset); return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
} }
@ -1468,9 +1466,8 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask, SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
"mask not equal"); "mask not equal");
SDLoc DL(N); return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, X, DAG.getConstant(Mask, MVT::i32));
X, DAG.getConstant(Mask, DL, MVT::i32));
} }
} }
} }
@ -1500,9 +1497,8 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
static const uint32_t MaxMask = 0x3ff; static const uint32_t MaxMask = 0x3ff;
uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask; uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
SDLoc DL(N); return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, Src, DAG.getConstant(NewMask, MVT::i32));
Src, DAG.getConstant(NewMask, DL, MVT::i32));
} }
return SDValue(); return SDValue();
@ -1516,7 +1512,7 @@ SDValue SITargetLowering::performClassCombine(SDNode *N,
// fp_class x, 0 -> false // fp_class x, 0 -> false
if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) { if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
if (CMask->isNullValue()) if (CMask->isNullValue())
return DAG.getConstant(0, SDLoc(N), MVT::i1); return DAG.getConstant(0, MVT::i1);
} }
return SDValue(); return SDValue();
@ -1600,8 +1596,8 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
const APFloat &APF = CRHS->getValueAPF(); const APFloat &APF = CRHS->getValueAPF();
if (APF.isInfinity() && !APF.isNegative()) { if (APF.isInfinity() && !APF.isNegative()) {
unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY; unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0), return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1,
DAG.getConstant(Mask, SL, MVT::i32)); LHS.getOperand(0), DAG.getConstant(Mask, MVT::i32));
} }
} }
@ -1678,7 +1674,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
if (LHS.getOpcode() == ISD::FADD) { if (LHS.getOpcode() == ISD::FADD) {
SDValue A = LHS.getOperand(0); SDValue A = LHS.getOperand(0);
if (A == LHS.getOperand(1)) { if (A == LHS.getOperand(1)) {
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
} }
} }
@ -1687,7 +1683,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
if (RHS.getOpcode() == ISD::FADD) { if (RHS.getOpcode() == ISD::FADD) {
SDValue A = RHS.getOperand(0); SDValue A = RHS.getOperand(0);
if (A == RHS.getOperand(1)) { if (A == RHS.getOperand(1)) {
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
} }
} }
@ -1714,7 +1710,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
SDValue A = LHS.getOperand(0); SDValue A = LHS.getOperand(0);
if (A == LHS.getOperand(1)) { if (A == LHS.getOperand(1)) {
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS); SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
@ -1726,7 +1722,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
SDValue A = RHS.getOperand(0); SDValue A = RHS.getOperand(0);
if (A == RHS.getOperand(1)) { if (A == RHS.getOperand(1)) {
const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32); const SDValue NegTwo = DAG.getConstantFP(-2.0, MVT::f32);
return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
} }
} }
@ -1869,15 +1865,14 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// Adjust the writemask in the node // Adjust the writemask in the node
std::vector<SDValue> Ops; std::vector<SDValue> Ops;
Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32)); Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end()); Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops); Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
// If we only got one lane, replace it with a copy // If we only got one lane, replace it with a copy
// (if NewDmask has only one bit set...) // (if NewDmask has only one bit set...)
if (NewDmask && (NewDmask & (NewDmask-1)) == 0) { if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(), SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, MVT::i32);
MVT::i32);
SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
SDLoc(), Users[Lane]->getValueType(0), SDLoc(), Users[Lane]->getValueType(0),
SDValue(Node, 0), RC); SDValue(Node, 0), RC);
@ -1892,7 +1887,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
if (!User) if (!User)
continue; continue;
SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32); SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
DAG.UpdateNodeOperands(User, User->getOperand(0), Op); DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
switch (Idx) { switch (Idx) {
@ -1987,7 +1982,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
} }
static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) { static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32); SDValue K = DAG.getTargetConstant(Val, MVT::i32);
return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0); return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
} }
@ -2002,11 +1997,11 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
// Build the half of the subregister with the constants. // Build the half of the subregister with the constants.
const SDValue Ops0[] = { const SDValue Ops0[] = {
DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, MVT::i32),
buildSMovImm32(DAG, DL, 0), buildSMovImm32(DAG, DL, 0),
DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32), buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32) DAG.getTargetConstant(AMDGPU::sub1, MVT::i32)
}; };
SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
@ -2014,11 +2009,11 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
// Combine the constants and the pointer. // Combine the constants and the pointer.
const SDValue Ops1[] = { const SDValue Ops1[] = {
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
Ptr, Ptr,
DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
SubRegHi, SubRegHi,
DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32) DAG.getTargetConstant(AMDGPU::sub2_sub3, MVT::i32)
}; };
return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
@ -2051,8 +2046,7 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
if (RsrcDword1) { if (RsrcDword1) {
PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi, PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
DAG.getConstant(RsrcDword1, DL, MVT::i32)), DAG.getConstant(RsrcDword1, MVT::i32)), 0);
0);
} }
SDValue DataLo = buildSMovImm32(DAG, DL, SDValue DataLo = buildSMovImm32(DAG, DL,
@ -2060,15 +2054,15 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32); SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
const SDValue Ops[] = { const SDValue Ops[] = {
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
PtrLo, PtrLo,
DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
PtrHi, PtrHi,
DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::sub1, MVT::i32),
DataLo, DataLo,
DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32), DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
DataHi, DataHi,
DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32) DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
}; };
return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);

24
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -126,8 +126,7 @@ def SIconstdata_ptr : SDNode<
// Transformation function, extract the lower 32bit of a 64bit immediate // Transformation function, extract the lower 32bit of a 64bit immediate
def LO32 : SDNodeXForm<imm, [{ def LO32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N), return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
MVT::i32);
}]>; }]>;
def LO32f : SDNodeXForm<fpimm, [{ def LO32f : SDNodeXForm<fpimm, [{
@ -137,13 +136,12 @@ def LO32f : SDNodeXForm<fpimm, [{
// Transformation function, extract the upper 32bit of a 64bit immediate // Transformation function, extract the upper 32bit of a 64bit immediate
def HI32 : SDNodeXForm<imm, [{ def HI32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
}]>; }]>;
def HI32f : SDNodeXForm<fpimm, [{ def HI32f : SDNodeXForm<fpimm, [{
APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32); APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N), return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
MVT::f32);
}]>; }]>;
def IMM8bitDWORD : PatLeaf <(imm), def IMM8bitDWORD : PatLeaf <(imm),
@ -151,39 +149,39 @@ def IMM8bitDWORD : PatLeaf <(imm),
>; >;
def as_dword_i32imm : SDNodeXForm<imm, [{ def as_dword_i32imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
}]>; }]>;
def as_i1imm : SDNodeXForm<imm, [{ def as_i1imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1); return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
}]>; }]>;
def as_i8imm : SDNodeXForm<imm, [{ def as_i8imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8); return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
}]>; }]>;
def as_i16imm : SDNodeXForm<imm, [{ def as_i16imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16); return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
}]>; }]>;
def as_i32imm: SDNodeXForm<imm, [{ def as_i32imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
}]>; }]>;
def as_i64imm: SDNodeXForm<imm, [{ def as_i64imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
}]>; }]>;
// Copied from the AArch64 backend: // Copied from the AArch64 backend:
def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant( return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
}]>; }]>;
// Copied from the AArch64 backend: // Copied from the AArch64 backend:
def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant( return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
}]>; }]>;
def IMM8bit : PatLeaf <(imm), def IMM8bit : PatLeaf <(imm),

10
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -74,7 +74,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
SDValue &Base, SDValue &Offset) { SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy()); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
if (Addr.getOpcode() == ISD::TargetExternalSymbol || if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
@ -93,8 +93,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
} else { } else {
Base = Addr.getOperand(0); Base = Addr.getOperand(0);
} }
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
MVT::i32);
return true; return true;
} }
} }
@ -110,7 +109,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
} }
} }
Base = Addr; Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
@ -163,8 +162,7 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
SDValue TopPart; SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) { if (N->getOpcode() == ISD::SDIV) {
TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, dl, MVT::i32)), CurDAG->getTargetConstant(31, MVT::i32)), 0);
0);
} else { } else {
TopPart = CurDAG->getRegister(SP::G0, MVT::i32); TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
} }

133
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -229,7 +229,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain,
} }
RetOps[0] = Chain; // Update chain. RetOps[0] = Chain; // Update chain.
RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32); RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
// Add the flag if we have it. // Add the flag if we have it.
if (Flag.getNode()) if (Flag.getNode())
@ -261,7 +261,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
// The second operand on the return instruction is the return address offset. // The second operand on the return instruction is the return address offset.
// The return address is always %i7+8 with the 64-bit ABI. // The return address is always %i7+8 with the 64-bit ABI.
RetOps.push_back(DAG.getConstant(8, DL, MVT::i32)); RetOps.push_back(DAG.getConstant(8, MVT::i32));
// Copy the result values into the output registers. // Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) { for (unsigned i = 0; i != RVLocs.size(); ++i) {
@ -289,7 +289,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
// in the high bits of the register. // in the high bits of the register.
if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
DAG.getConstant(32, DL, MVT::i32)); DAG.getConstant(32, MVT::i32));
// The next value may go in the low bits of the same register. // The next value may go in the low bits of the same register.
// Handle both at once. // Handle both at once.
@ -471,7 +471,7 @@ LowerFormalArguments_32(SDValue Chain,
// Sparc is big endian, so add an offset based on the ObjectVT. // Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
DAG.getConstant(Offset, dl, MVT::i32)); DAG.getConstant(Offset, MVT::i32));
Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
MachinePointerInfo(), MachinePointerInfo(),
VA.getValVT(), false, false, false,0); VA.getValVT(), false, false, false,0);
@ -570,7 +570,7 @@ LowerFormalArguments_64(SDValue Chain,
// Get the high bits for i32 struct elements. // Get the high bits for i32 struct elements.
if (VA.getValVT() == MVT::i32 && VA.needsCustom()) if (VA.getValVT() == MVT::i32 && VA.needsCustom())
Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
DAG.getConstant(32, DL, MVT::i32)); DAG.getConstant(32, MVT::i32));
// The caller promoted the argument, so insert an Assert?ext SDNode so we // The caller promoted the argument, so insert an Assert?ext SDNode so we
// won't promote the value again in this function. // won't promote the value again in this function.
@ -723,7 +723,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
int FI = MFI->CreateStackObject(Size, Align, false); int FI = MFI->CreateStackObject(Size, Align, false);
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
false, // isVolatile, false, // isVolatile,
@ -733,7 +733,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
ByValArgs.push_back(FIPtr); ByValArgs.push_back(FIPtr);
} }
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true), Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
dl); dl);
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
@ -776,7 +776,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
assert(VA.needsCustom()); assert(VA.needsCustom());
// store SRet argument in %sp+64 // store SRet argument in %sp+64
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(64, dl); SDValue PtrOff = DAG.getIntPtrConstant(64);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -793,7 +793,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// if it is double-word aligned, just store. // if it is double-word aligned, just store.
if (Offset % 8 == 0) { if (Offset % 8 == 0) {
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); SDValue PtrOff = DAG.getIntPtrConstant(Offset);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -811,7 +811,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
// Increment the pointer to the other half. // Increment the pointer to the other half.
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getIntPtrConstant(4, dl)); DAG.getIntPtrConstant(4));
// Load the low part. // Load the low part.
SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
@ -826,7 +826,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// Store the low part in stack. // Store the low part in stack.
unsigned Offset = NextVA.getLocMemOffset() + StackOffset; unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); SDValue PtrOff = DAG.getIntPtrConstant(Offset);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -836,13 +836,13 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
unsigned Offset = VA.getLocMemOffset() + StackOffset; unsigned Offset = VA.getLocMemOffset() + StackOffset;
// Store the high part. // Store the high part.
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); SDValue PtrOff = DAG.getIntPtrConstant(Offset);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
false, false, 0)); false, false, 0));
// Store the low part. // Store the low part.
PtrOff = DAG.getIntPtrConstant(Offset + 4, dl); PtrOff = DAG.getIntPtrConstant(Offset+4);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -867,8 +867,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// Create a store off the stack pointer for this argument. // Create a store off the stack pointer for this argument.
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
dl);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -910,7 +909,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
Ops.push_back(Chain); Ops.push_back(Chain);
Ops.push_back(Callee); Ops.push_back(Callee);
if (hasStructRetAttr) if (hasStructRetAttr)
Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32)); Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
RegsToPass[i].second.getValueType())); RegsToPass[i].second.getValueType()));
@ -930,8 +929,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops); Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true), Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
DAG.getIntPtrConstant(0, dl, true), InFlag, dl); DAG.getIntPtrConstant(0, true), InFlag, dl);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
@ -1083,7 +1082,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
// Adjust the stack pointer to make room for the arguments. // Adjust the stack pointer to make room for the arguments.
// FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
// with more than 6 arguments. // with more than 6 arguments.
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true), Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
DL); DL);
// Collect the set of registers to pass to the function and their values. // Collect the set of registers to pass to the function and their values.
@ -1131,10 +1130,10 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
unsigned Offset = 8 * (VA.getLocReg() - SP::I0); unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL); SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
HiPtrOff); HiPtrOff);
SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL); SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
LoPtrOff); LoPtrOff);
@ -1160,7 +1159,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
// passed in the high bits of the register. // passed in the high bits of the register.
if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
DAG.getConstant(32, DL, MVT::i32)); DAG.getConstant(32, MVT::i32));
// The next value may go in the low bits of the same register. // The next value may go in the low bits of the same register.
// Handle both at once. // Handle both at once.
@ -1185,7 +1184,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
// %sp+BIAS+128 in ours. // %sp+BIAS+128 in ours.
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
Subtarget->getStackPointerBias() + Subtarget->getStackPointerBias() +
128, DL); 128);
PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
MachinePointerInfo(), MachinePointerInfo(),
@ -1248,8 +1247,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
InGlue = Chain.getValue(1); InGlue = Chain.getValue(1);
// Revert the stack pointer immediately after the call. // Revert the stack pointer immediately after the call.
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true), Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
DAG.getIntPtrConstant(0, DL, true), InGlue, DL); DAG.getIntPtrConstant(0, true), InGlue, DL);
InGlue = Chain.getValue(1); InGlue = Chain.getValue(1);
// Now extract the return values. This is more or less the same as // Now extract the return values. This is more or less the same as
@ -1290,7 +1289,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
// Get the high bits for i32 struct elements. // Get the high bits for i32 struct elements.
if (VA.getValVT() == MVT::i32 && VA.needsCustom()) if (VA.getValVT() == MVT::i32 && VA.needsCustom())
RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
DAG.getConstant(32, DL, MVT::i32)); DAG.getConstant(32, MVT::i32));
// The callee promoted the return value, so insert an Assert?ext SDNode so // The callee promoted the return value, so insert an Assert?ext SDNode so
// we won't promote the value again in this function. // we won't promote the value again in this function.
@ -1832,7 +1831,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
// abs44. // abs44.
SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44, SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
SparcMCExpr::VK_Sparc_M44, DAG); SparcMCExpr::VK_Sparc_M44, DAG);
H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG); SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
return DAG.getNode(ISD::ADD, DL, VT, H44, L44); return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
@ -1841,7 +1840,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
// abs64. // abs64.
SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH, SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
SparcMCExpr::VK_Sparc_HM, DAG); SparcMCExpr::VK_Sparc_HM, DAG);
Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
SparcMCExpr::VK_Sparc_LO, DAG); SparcMCExpr::VK_Sparc_LO, DAG);
return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
@ -1896,7 +1895,7 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SDValue Chain = DAG.getEntryNode(); SDValue Chain = DAG.getEntryNode();
SDValue InFlag; SDValue InFlag;
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL); Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
@ -1915,8 +1914,8 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
Ops.push_back(InFlag); Ops.push_back(InFlag);
Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops); Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true), Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
DAG.getIntPtrConstant(0, DL, true), InFlag, DL); DAG.getIntPtrConstant(0, true), InFlag, DL);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
@ -2099,54 +2098,54 @@ SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
switch(SPCC) { switch(SPCC) {
default: { default: {
SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_UL : { case SPCC::FCC_UL : {
SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType()); SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_ULE: { case SPCC::FCC_ULE: {
SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_UG : { case SPCC::FCC_UG : {
SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
SPCC = SPCC::ICC_G; SPCC = SPCC::ICC_G;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_UGE: { case SPCC::FCC_UGE: {
SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_U : { case SPCC::FCC_U : {
SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
SPCC = SPCC::ICC_E; SPCC = SPCC::ICC_E;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_O : { case SPCC::FCC_O : {
SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_LG : { case SPCC::FCC_LG : {
SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType()); SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
SPCC = SPCC::ICC_NE; SPCC = SPCC::ICC_NE;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
case SPCC::FCC_UE : { case SPCC::FCC_UE : {
SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType()); SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
SPCC = SPCC::ICC_E; SPCC = SPCC::ICC_E;
return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
} }
@ -2318,7 +2317,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
} }
} }
return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); DAG.getConstant(SPCC, MVT::i32), CompareFlag);
} }
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
@ -2354,7 +2353,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
} }
} }
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); DAG.getConstant(SPCC, MVT::i32), CompareFlag);
} }
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
@ -2371,7 +2370,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
SDValue Offset = SDValue Offset =
DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
DAG.getRegister(SP::I6, TLI.getPointerTy()), DAG.getRegister(SP::I6, TLI.getPointerTy()),
DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL)); DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
MachinePointerInfo(SV), false, false, 0); MachinePointerInfo(SV), false, false, 0);
@ -2389,8 +2388,7 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
MachinePointerInfo(SV), false, false, false, 0); MachinePointerInfo(SV), false, false, false, 0);
// Increment the pointer, VAList, to the next vaarg. // Increment the pointer, VAList, to the next vaarg.
SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getIntPtrConstant(VT.getSizeInBits()/8, DAG.getIntPtrConstant(VT.getSizeInBits()/8));
DL));
// Store the incremented VAList to the legalized pointer. // Store the incremented VAList to the legalized pointer.
InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
VAListPtr, MachinePointerInfo(SV), false, false, 0); VAListPtr, MachinePointerInfo(SV), false, false, 0);
@ -2419,7 +2417,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
regSpillArea += Subtarget->getStackPointerBias(); regSpillArea += Subtarget->getStackPointerBias();
SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
DAG.getConstant(regSpillArea, dl, VT)); DAG.getConstant(regSpillArea, VT));
SDValue Ops[2] = { NewVal, Chain }; SDValue Ops[2] = { NewVal, Chain };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
} }
@ -2448,7 +2446,7 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
if (Subtarget->is64Bit()) if (Subtarget->is64Bit())
FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
DAG.getIntPtrConstant(stackBias, dl)); DAG.getIntPtrConstant(stackBias));
return FrameAddr; return FrameAddr;
} }
@ -2460,13 +2458,13 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
while (depth--) { while (depth--) {
SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
DAG.getIntPtrConstant(Offset, dl)); DAG.getIntPtrConstant(Offset));
FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(), FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
false, false, false, 0); false, false, false, 0);
} }
if (Subtarget->is64Bit()) if (Subtarget->is64Bit())
FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
DAG.getIntPtrConstant(stackBias, dl)); DAG.getIntPtrConstant(stackBias));
return FrameAddr; return FrameAddr;
} }
@ -2509,7 +2507,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
SDValue Ptr = DAG.getNode(ISD::ADD, SDValue Ptr = DAG.getNode(ISD::ADD,
dl, VT, dl, VT,
FrameAddr, FrameAddr,
DAG.getIntPtrConstant(Offset, dl)); DAG.getIntPtrConstant(Offset));
RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
MachinePointerInfo(), false, false, false, 0); MachinePointerInfo(), false, false, false, 0);
@ -2565,7 +2563,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
EVT addrVT = LdNode->getBasePtr().getValueType(); EVT addrVT = LdNode->getBasePtr().getValueType();
SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
LdNode->getBasePtr(), LdNode->getBasePtr(),
DAG.getConstant(8, dl, addrVT)); DAG.getConstant(8, addrVT));
SDValue Lo64 = DAG.getLoad(MVT::f64, SDValue Lo64 = DAG.getLoad(MVT::f64,
dl, dl,
LdNode->getChain(), LdNode->getChain(),
@ -2573,8 +2571,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
LdNode->getPointerInfo(), LdNode->getPointerInfo(),
false, false, false, alignment); false, false, false, alignment);
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, MVT::f128); dl, MVT::f128);
@ -2601,8 +2599,8 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
&& "Unexpected node type"); && "Unexpected node type");
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
dl, dl,
@ -2629,7 +2627,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
EVT addrVT = StNode->getBasePtr().getValueType(); EVT addrVT = StNode->getBasePtr().getValueType();
SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
StNode->getBasePtr(), StNode->getBasePtr(),
DAG.getConstant(8, dl, addrVT)); DAG.getConstant(8, addrVT));
OutChains[1] = DAG.getStore(StNode->getChain(), OutChains[1] = DAG.getStore(StNode->getChain(),
dl, dl,
SDValue(Lo64, 0), SDValue(Lo64, 0),
@ -2680,13 +2678,13 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
SDValue Src1 = Op.getOperand(0); SDValue Src1 = Op.getOperand(0);
SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
SDValue Src2 = Op.getOperand(1); SDValue Src2 = Op.getOperand(1);
SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
@ -2713,7 +2711,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
DAG.getConstant(32, dl, MVT::i64)); DAG.getConstant(32, MVT::i64));
SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
SDValue Ops[2] = { Dst, Carry }; SDValue Ops[2] = { Dst, Carry };
@ -2737,7 +2735,7 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
if (LHS.getValueType() != VT) if (LHS.getValueType() != VT)
return Op; return Op;
SDValue ShiftAmt = DAG.getConstant(63, dl, VT); SDValue ShiftAmt = DAG.getConstant(63, VT);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
@ -2748,14 +2746,14 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
RTLIB::MUL_I128, WideVT, RTLIB::MUL_I128, WideVT,
Args, 4, isSigned, dl).first; Args, 4, isSigned, dl).first;
SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
MulResult, DAG.getIntPtrConstant(0, dl)); MulResult, DAG.getIntPtrConstant(0));
SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
MulResult, DAG.getIntPtrConstant(1, dl)); MulResult, DAG.getIntPtrConstant(1));
if (isSigned) { if (isSigned) {
SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
} else { } else {
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT), TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
ISD::SETNE); ISD::SETNE);
} }
// MulResult is a node with an illegal type. Because such things are not // MulResult is a node with an illegal type. Because such things are not
@ -3121,8 +3119,7 @@ LowerAsmOperandForConstraint(SDValue Op,
case 'I': case 'I':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
if (isInt<13>(C->getSExtValue())) { if (isInt<13>(C->getSExtValue())) {
Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
Op.getValueType());
break; break;
} }
return; return;

11
llvm/lib/Target/Sparc/SparcInstr64Bit.td
View File

@ -63,7 +63,7 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
// The ALU instructions want their simm13 operands as i32 immediates. // The ALU instructions want their simm13 operands as i32 immediates.
def as_i32imm : SDNodeXForm<imm, [{ def as_i32imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
}]>; }]>;
def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
@ -83,12 +83,11 @@ def nimm33 : PatLeaf<(imm), [{
// Bits 10-31 inverted. Same as assembler's %hix. // Bits 10-31 inverted. Same as assembler's %hix.
def HIX22 : SDNodeXForm<imm, [{ def HIX22 : SDNodeXForm<imm, [{
uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(Val, MVT::i32);
}]>; }]>;
// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
def LOX10 : SDNodeXForm<imm, [{ def LOX10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
MVT::i32);
}]>; }]>;
def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
Requires<[Is64Bit]>; Requires<[Is64Bit]>;
@ -122,12 +121,12 @@ def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
// Bits 42-63, same as assembler's %hh. // Bits 42-63, same as assembler's %hh.
def HH22 : SDNodeXForm<imm, [{ def HH22 : SDNodeXForm<imm, [{
uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(Val, MVT::i32);
}]>; }]>;
// Bits 32-41, same as assembler's %hm. // Bits 32-41, same as assembler's %hm.
def HM10 : SDNodeXForm<imm, [{ def HM10 : SDNodeXForm<imm, [{
uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(Val, MVT::i32);
}]>; }]>;
def : Pat<(i64 imm:$val), def : Pat<(i64 imm:$val),
(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),

5
llvm/lib/Target/Sparc/SparcInstrInfo.td
View File

@ -64,14 +64,13 @@ def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
def LO10 : SDNodeXForm<imm, [{ def LO10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N), return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
MVT::i32); MVT::i32);
}]>; }]>;
def HI22 : SDNodeXForm<imm, [{ def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N), return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
MVT::i32);
}]>; }]>;
def SETHIimm : PatLeaf<(imm), [{ def SETHIimm : PatLeaf<(imm), [{

42
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -131,7 +131,7 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
// Used by SystemZOperands.td to create integer constants. // Used by SystemZOperands.td to create integer constants.
inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
} }
const SystemZTargetMachine &getTargetMachine() const { const SystemZTargetMachine &getTargetMachine() const {
@ -596,7 +596,7 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
} }
// Lower the displacement to a TargetConstant. // Lower the displacement to a TargetConstant.
Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT); Disp = CurDAG->getTargetConstant(AM.Disp, VT);
} }
void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM, void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
@ -864,7 +864,6 @@ SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) const {
} }
SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
unsigned Count = 0; unsigned Count = 0;
@ -890,7 +889,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
// Force the new mask into the DAG, since it may include known-one bits. // Force the new mask into the DAG, since it may include known-one bits.
auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode()); auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
if (MaskN->getZExtValue() != RISBG.Mask) { if (MaskN->getZExtValue() != RISBG.Mask) {
SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT); SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask); N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
return SelectCode(N); return SelectCode(N);
} }
@ -910,14 +909,14 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
RISBG.End &= 31; RISBG.End &= 31;
} }
SDValue Ops[5] = { SDValue Ops[5] = {
getUNDEF(DL, OpcodeVT), getUNDEF(SDLoc(N), OpcodeVT),
convertTo(DL, OpcodeVT, RISBG.Input), convertTo(SDLoc(N), OpcodeVT, RISBG.Input),
CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32), CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32), CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32) CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
}; };
N = CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops); N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops);
return convertTo(DL, VT, SDValue(N, 0)).getNode(); return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
} }
SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) { SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
@ -956,17 +955,16 @@ SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
Opcode = SystemZ::RISBGN; Opcode = SystemZ::RISBGN;
} }
SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue Ops[5] = { SDValue Ops[5] = {
convertTo(DL, MVT::i64, Op0), convertTo(SDLoc(N), MVT::i64, Op0),
convertTo(DL, MVT::i64, RxSBG[I].Input), convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32), CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32), CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32) CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
}; };
N = CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops); N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
return convertTo(DL, VT, SDValue(N, 0)).getNode(); return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
} }
SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node, SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
@ -974,12 +972,12 @@ SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
uint64_t LowerVal) { uint64_t LowerVal) {
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
SDLoc DL(Node); SDLoc DL(Node);
SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT); SDValue Upper = CurDAG->getConstant(UpperVal, VT);
if (Op0.getNode()) if (Op0.getNode())
Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
Upper = SDValue(Select(Upper.getNode()), 0); Upper = SDValue(Select(Upper.getNode()), 0);
SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT); SDValue Lower = CurDAG->getConstant(LowerVal, VT);
SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
return Or.getNode(); return Or.getNode();
} }
@ -1113,7 +1111,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
uint64_t ConstCCMask = uint64_t ConstCCMask =
cast<ConstantSDNode>(CCMask.getNode())->getZExtValue(); cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
// Invert the condition. // Invert the condition.
CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node), CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
CCMask.getValueType()); CCMask.getValueType());
SDValue Op4 = Node->getOperand(4); SDValue Op4 = Node->getOperand(4);
Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);

163
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -591,35 +591,35 @@ LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
case 'I': // Unsigned 8-bit constant case 'I': // Unsigned 8-bit constant
if (auto *C = dyn_cast<ConstantSDNode>(Op)) if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isUInt<8>(C->getZExtValue())) if (isUInt<8>(C->getZExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
Op.getValueType())); Op.getValueType()));
return; return;
case 'J': // Unsigned 12-bit constant case 'J': // Unsigned 12-bit constant
if (auto *C = dyn_cast<ConstantSDNode>(Op)) if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isUInt<12>(C->getZExtValue())) if (isUInt<12>(C->getZExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
Op.getValueType())); Op.getValueType()));
return; return;
case 'K': // Signed 16-bit constant case 'K': // Signed 16-bit constant
if (auto *C = dyn_cast<ConstantSDNode>(Op)) if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<16>(C->getSExtValue())) if (isInt<16>(C->getSExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
Op.getValueType())); Op.getValueType()));
return; return;
case 'L': // Signed 20-bit displacement (on all targets we support) case 'L': // Signed 20-bit displacement (on all targets we support)
if (auto *C = dyn_cast<ConstantSDNode>(Op)) if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<20>(C->getSExtValue())) if (isInt<20>(C->getSExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
Op.getValueType())); Op.getValueType()));
return; return;
case 'M': // 0x7fffffff case 'M': // 0x7fffffff
if (auto *C = dyn_cast<ConstantSDNode>(Op)) if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (C->getZExtValue() == 0x7fffffff) if (C->getZExtValue() == 0x7fffffff)
Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
Op.getValueType())); Op.getValueType()));
return; return;
} }
@ -753,8 +753,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
SDValue FIN = DAG.getFrameIndex(FI, PtrVT); SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
DAG.getIntPtrConstant(4, DL));
ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
MachinePointerInfo::getFixedStack(FI), MachinePointerInfo::getFixedStack(FI),
false, false, false, 0); false, false, false, 0);
@ -855,8 +854,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Mark the start of the call. // Mark the start of the call.
if (!IsTailCall) if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
DAG.getConstant(NumBytes, DL, PtrVT, true),
DL); DL);
// Copy argument values to their designated locations. // Copy argument values to their designated locations.
@ -892,7 +890,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
Offset += 4; Offset += 4;
SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
DAG.getIntPtrConstant(Offset, DL)); DAG.getIntPtrConstant(Offset));
// Emit the store. // Emit the store.
MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address, MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
@ -958,8 +956,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Mark the end of the call, which is glued to the call itself. // Mark the end of the call, which is glued to the call itself.
Chain = DAG.getCALLSEQ_END(Chain, Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, DL, PtrVT, true), DAG.getConstant(NumBytes, PtrVT, true),
DAG.getConstant(0, DL, PtrVT, true), DAG.getConstant(0, PtrVT, true),
Glue, DL); Glue, DL);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
@ -1181,7 +1179,7 @@ static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
// If C can be converted to a comparison against zero, adjust the operands // If C can be converted to a comparison against zero, adjust the operands
// as necessary. // as necessary.
static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) { static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
if (C.ICmpType == SystemZICMP::UnsignedOnly) if (C.ICmpType == SystemZICMP::UnsignedOnly)
return; return;
@ -1195,13 +1193,13 @@ static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
(Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) || (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
(Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) { (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
C.CCMask ^= SystemZ::CCMASK_CMP_EQ; C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType()); C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
} }
} }
// If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI, // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
// adjust the operands as necessary. // adjust the operands as necessary.
static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) { static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
// For us to make any changes, it must a comparison between a single-use // For us to make any changes, it must a comparison between a single-use
// load and a constant. // load and a constant.
if (!C.Op0.hasOneUse() || if (!C.Op0.hasOneUse() ||
@ -1266,7 +1264,7 @@ static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
// Make sure that the second operand is an i32 with the right value. // Make sure that the second operand is an i32 with the right value.
if (C.Op1.getValueType() != MVT::i32 || if (C.Op1.getValueType() != MVT::i32 ||
Value != ConstOp1->getZExtValue()) Value != ConstOp1->getZExtValue())
C.Op1 = DAG.getConstant(Value, DL, MVT::i32); C.Op1 = DAG.getConstant(Value, MVT::i32);
} }
// Return true if Op is either an unextended load, or a load suitable // Return true if Op is either an unextended load, or a load suitable
@ -1362,7 +1360,7 @@ static unsigned reverseCCMask(unsigned CCMask) {
// Check whether C tests for equality between X and Y and whether X - Y // Check whether C tests for equality between X and Y and whether X - Y
// or Y - X is also computed. In that case it's better to compare the // or Y - X is also computed. In that case it's better to compare the
// result of the subtraction against zero. // result of the subtraction against zero.
static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) { static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
if (C.CCMask == SystemZ::CCMASK_CMP_EQ || if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
C.CCMask == SystemZ::CCMASK_CMP_NE) { C.CCMask == SystemZ::CCMASK_CMP_NE) {
for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) { for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
@ -1371,7 +1369,7 @@ static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) || ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
(N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) { (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
C.Op0 = SDValue(N, 0); C.Op0 = SDValue(N, 0);
C.Op1 = DAG.getConstant(0, DL, N->getValueType(0)); C.Op1 = DAG.getConstant(0, N->getValueType(0));
return; return;
} }
} }
@ -1427,7 +1425,7 @@ static void adjustForLTGFR(Comparison &C) {
// If C compares the truncation of an extending load, try to compare // If C compares the truncation of an extending load, try to compare
// the untruncated value instead. This exposes more opportunities to // the untruncated value instead. This exposes more opportunities to
// reuse CC. // reuse CC.
static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) { static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
if (C.Op0.getOpcode() == ISD::TRUNCATE && if (C.Op0.getOpcode() == ISD::TRUNCATE &&
C.Op0.getOperand(0).getOpcode() == ISD::LOAD && C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
C.Op1.getOpcode() == ISD::Constant && C.Op1.getOpcode() == ISD::Constant &&
@ -1439,7 +1437,7 @@ static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
(Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) { (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
C.Op0 = C.Op0.getOperand(0); C.Op0 = C.Op0.getOperand(0);
C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType()); C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
} }
} }
} }
@ -1558,7 +1556,7 @@ static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
// See whether C can be implemented as a TEST UNDER MASK instruction. // See whether C can be implemented as a TEST UNDER MASK instruction.
// Update the arguments with the TM version if so. // Update the arguments with the TM version if so.
static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) { static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
// Check that we have a comparison with a constant. // Check that we have a comparison with a constant.
auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1); auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
if (!ConstOp1) if (!ConstOp1)
@ -1636,7 +1634,7 @@ static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
if (Mask && Mask->getZExtValue() == MaskVal) if (Mask && Mask->getZExtValue() == MaskVal)
C.Op1 = SDValue(Mask, 0); C.Op1 = SDValue(Mask, 0);
else else
C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType()); C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
C.CCValid = SystemZ::CCMASK_TM; C.CCValid = SystemZ::CCMASK_TM;
C.CCMask = NewCCMask; C.CCMask = NewCCMask;
} }
@ -1679,7 +1677,7 @@ static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1. // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
ISD::CondCode Cond, SDLoc DL) { ISD::CondCode Cond) {
if (CmpOp1.getOpcode() == ISD::Constant) { if (CmpOp1.getOpcode() == ISD::Constant) {
uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue(); uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
unsigned Opcode, CCValid; unsigned Opcode, CCValid;
@ -1711,11 +1709,11 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
else else
C.ICmpType = SystemZICMP::SignedOnly; C.ICmpType = SystemZICMP::SignedOnly;
C.CCMask &= ~SystemZ::CCMASK_CMP_UO; C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
adjustZeroCmp(DAG, DL, C); adjustZeroCmp(DAG, C);
adjustSubwordCmp(DAG, DL, C); adjustSubwordCmp(DAG, C);
adjustForSubtraction(DAG, DL, C); adjustForSubtraction(DAG, C);
adjustForLTGFR(C); adjustForLTGFR(C);
adjustICmpTruncate(DAG, DL, C); adjustICmpTruncate(DAG, C);
} }
if (shouldSwapCmpOperands(C)) { if (shouldSwapCmpOperands(C)) {
@ -1723,7 +1721,7 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
C.CCMask = reverseCCMask(C.CCMask); C.CCMask = reverseCCMask(C.CCMask);
} }
adjustForTestUnderMask(DAG, DL, C); adjustForTestUnderMask(DAG, C);
return C; return C;
} }
@ -1742,12 +1740,12 @@ static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
} }
if (C.Opcode == SystemZISD::ICMP) if (C.Opcode == SystemZISD::ICMP)
return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1, return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
DAG.getConstant(C.ICmpType, DL, MVT::i32)); DAG.getConstant(C.ICmpType, MVT::i32));
if (C.Opcode == SystemZISD::TM) { if (C.Opcode == SystemZISD::TM) {
bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) != bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1)); bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1, return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
DAG.getConstant(RegisterOnly, DL, MVT::i32)); DAG.getConstant(RegisterOnly, MVT::i32));
} }
return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1); return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
} }
@ -1761,8 +1759,7 @@ static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0); Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1); Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1); SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
DAG.getConstant(32, DL, MVT::i64));
Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi); Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul); Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
} }
@ -1794,18 +1791,18 @@ static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
if (Conversion.XORValue) if (Conversion.XORValue)
Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result, Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
DAG.getConstant(Conversion.XORValue, DL, MVT::i32)); DAG.getConstant(Conversion.XORValue, MVT::i32));
if (Conversion.AddValue) if (Conversion.AddValue)
Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result, Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
DAG.getConstant(Conversion.AddValue, DL, MVT::i32)); DAG.getConstant(Conversion.AddValue, MVT::i32));
// The SHR/AND sequence should get optimized to an RISBG. // The SHR/AND sequence should get optimized to an RISBG.
Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result, Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
DAG.getConstant(Conversion.Bit, DL, MVT::i32)); DAG.getConstant(Conversion.Bit, MVT::i32));
if (Conversion.Bit != 31) if (Conversion.Bit != 31)
Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result, Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, MVT::i32));
return Result; return Result;
} }
@ -1816,7 +1813,7 @@ SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
SDLoc DL(Op); SDLoc DL(Op);
Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL)); Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
SDValue Glue = emitCmp(DAG, DL, C); SDValue Glue = emitCmp(DAG, DL, C);
return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask); return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
} }
@ -1828,11 +1825,11 @@ SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Dest = Op.getOperand(4); SDValue Dest = Op.getOperand(4);
SDLoc DL(Op); SDLoc DL(Op);
Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL)); Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
SDValue Glue = emitCmp(DAG, DL, C); SDValue Glue = emitCmp(DAG, DL, C);
return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(), return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32), Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue); DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
} }
// Return true if Pos is CmpOp and Neg is the negative of CmpOp, // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
@ -1853,7 +1850,7 @@ static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op); Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
if (IsNegative) if (IsNegative)
Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(), Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
DAG.getConstant(0, DL, Op.getValueType()), Op); DAG.getConstant(0, Op.getValueType()), Op);
return Op; return Op;
} }
@ -1866,7 +1863,7 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDLoc DL(Op); SDLoc DL(Op);
Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL)); Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
// Check for absolute and negative-absolute selections, including those // Check for absolute and negative-absolute selections, including those
// where the comparison value is sign-extended (for LPGFR and LNGFR). // where the comparison value is sign-extended (for LPGFR and LNGFR).
@ -1901,14 +1898,14 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
if (!is32Bit(VT)) if (!is32Bit(VT))
Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result); Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
// Sign-extend from the low bit. // Sign-extend from the low bit.
SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32); SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt); SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt); return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
} }
} }
SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32), SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
DAG.getConstant(C.CCMask, DL, MVT::i32), Glue}; DAG.getConstant(C.CCMask, MVT::i32), Glue};
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops); return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
@ -1948,7 +1945,7 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
// addition for it. // addition for it.
if (Offset != 0) if (Offset != 0)
Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
DAG.getConstant(Offset, DL, PtrVT)); DAG.getConstant(Offset, PtrVT));
return Result; return Result;
} }
@ -2009,17 +2006,17 @@ SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
// The high part of the thread pointer is in access register 0. // The high part of the thread pointer is in access register 0.
SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32, SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi); TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
// The low part of the thread pointer is in access register 1. // The low part of the thread pointer is in access register 1.
SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32, SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, MVT::i32));
TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo); TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
// Merge them into a single 64-bit address. // Merge them into a single 64-bit address.
SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi, SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
DAG.getConstant(32, DL, PtrVT)); DAG.getConstant(32, PtrVT));
SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo); SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
// Get the offset of GA from the thread pointer, based on the TLS model. // Get the offset of GA from the thread pointer, based on the TLS model.
@ -2156,7 +2153,7 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
} else { } else {
In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
DAG.getConstant(32, DL, MVT::i64)); DAG.getConstant(32, MVT::i64));
} }
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64); SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
@ -2171,7 +2168,7 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL, return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
MVT::i32, Out64); MVT::i32, Out64);
SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
DAG.getConstant(32, DL, MVT::i64)); DAG.getConstant(32, MVT::i64));
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift); return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
} }
llvm_unreachable("Unexpected bitcast combination"); llvm_unreachable("Unexpected bitcast combination");
@ -2192,8 +2189,8 @@ SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
// The initial values of each field. // The initial values of each field.
const unsigned NumFields = 4; const unsigned NumFields = 4;
SDValue Fields[NumFields] = { SDValue Fields[NumFields] = {
DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT), DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT), DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT), DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT) DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
}; };
@ -2205,7 +2202,7 @@ SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
SDValue FieldAddr = Addr; SDValue FieldAddr = Addr;
if (Offset != 0) if (Offset != 0)
FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr, FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
DAG.getIntPtrConstant(Offset, DL)); DAG.getIntPtrConstant(Offset));
MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr, MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
MachinePointerInfo(SV, Offset), MachinePointerInfo(SV, Offset),
false, false, 0); false, false, 0);
@ -2223,7 +2220,7 @@ SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDLoc DL(Op); SDLoc DL(Op);
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL), return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
/*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false, /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
/*isTailCall*/false, /*isTailCall*/false,
MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
@ -2280,7 +2277,7 @@ SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
// multiplication: // multiplication:
// //
// (ll * rl) - (((lh & rl) + (ll & rh)) << 64) // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
SDValue C63 = DAG.getConstant(63, DL, MVT::i64); SDValue C63 = DAG.getConstant(63, MVT::i64);
SDValue LL = Op.getOperand(0); SDValue LL = Op.getOperand(0);
SDValue RL = Op.getOperand(1); SDValue RL = Op.getOperand(1);
SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63); SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
@ -2430,7 +2427,7 @@ SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
DAG.computeKnownBits(Op, KnownZero, KnownOne); DAG.computeKnownBits(Op, KnownZero, KnownOne);
unsigned NumSignificantBits = (~KnownZero).getActiveBits(); unsigned NumSignificantBits = (~KnownZero).getActiveBits();
if (NumSignificantBits == 0) if (NumSignificantBits == 0)
return DAG.getConstant(0, DL, VT); return DAG.getConstant(0, VT);
// Skip known-zero high parts of the operand. // Skip known-zero high parts of the operand.
int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits); int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
@ -2444,17 +2441,16 @@ SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
// Add up per-byte counts in a binary tree. All bits of Op at // Add up per-byte counts in a binary tree. All bits of Op at
// position larger than BitSize remain zero throughout. // position larger than BitSize remain zero throughout.
for (int64_t I = BitSize / 2; I >= 8; I = I / 2) { for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT)); SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, VT));
if (BitSize != OrigBitSize) if (BitSize != OrigBitSize)
Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp, Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT)); DAG.getConstant(((uint64_t)1 << BitSize) - 1, VT));
Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
} }
// Extract overall result from high byte. // Extract overall result from high byte.
if (BitSize > 8) if (BitSize > 8)
Op = DAG.getNode(ISD::SRL, DL, VT, Op, Op = DAG.getNode(ISD::SRL, DL, VT, Op, DAG.getConstant(BitSize - 8, VT));
DAG.getConstant(BitSize - 8, DL, VT));
return Op; return Op;
} }
@ -2505,23 +2501,23 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB) if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
Opcode = SystemZISD::ATOMIC_LOADW_ADD; Opcode = SystemZISD::ATOMIC_LOADW_ADD;
Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType()); Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
} }
// Get the address of the containing word. // Get the address of the containing word.
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
DAG.getConstant(-4, DL, PtrVT)); DAG.getConstant(-4, PtrVT));
// Get the number of bits that the word must be rotated left in order // Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32. // to bring the field to the top bits of a GR32.
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr, SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
DAG.getConstant(3, DL, PtrVT)); DAG.getConstant(3, PtrVT));
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
// Get the complementing shift amount, for rotating a field in the top // Get the complementing shift amount, for rotating a field in the top
// bits back to its proper position. // bits back to its proper position.
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
DAG.getConstant(0, DL, WideVT), BitShift); DAG.getConstant(0, WideVT), BitShift);
// Extend the source operand to 32 bits and prepare it for the inner loop. // Extend the source operand to 32 bits and prepare it for the inner loop.
// ATOMIC_SWAPW uses RISBG to rotate the field left, but all other // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
@ -2530,23 +2526,23 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
// bits must be set, while for other opcodes they should be left clear. // bits must be set, while for other opcodes they should be left clear.
if (Opcode != SystemZISD::ATOMIC_SWAPW) if (Opcode != SystemZISD::ATOMIC_SWAPW)
Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
DAG.getConstant(32 - BitSize, DL, WideVT)); DAG.getConstant(32 - BitSize, WideVT));
if (Opcode == SystemZISD::ATOMIC_LOADW_AND || if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
Opcode == SystemZISD::ATOMIC_LOADW_NAND) Opcode == SystemZISD::ATOMIC_LOADW_NAND)
Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT)); DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
// Construct the ATOMIC_LOADW_* node. // Construct the ATOMIC_LOADW_* node.
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
DAG.getConstant(BitSize, DL, WideVT) }; DAG.getConstant(BitSize, WideVT) };
SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
NarrowVT, MMO); NarrowVT, MMO);
// Rotate the result of the final CS so that the field is in the lower // Rotate the result of the final CS so that the field is in the lower
// bits of a GR32, then truncate it. // bits of a GR32, then truncate it.
SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift, SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
DAG.getConstant(BitSize, DL, WideVT)); DAG.getConstant(BitSize, WideVT));
SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift); SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
SDValue RetOps[2] = { Result, AtomicOp.getValue(1) }; SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
@ -2572,10 +2568,10 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
// available or the negative value is in the range of A(G)FHI. // available or the negative value is in the range of A(G)FHI.
int64_t Value = (-Op2->getAPIntValue()).getSExtValue(); int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1()) if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
NegSrc2 = DAG.getConstant(Value, DL, MemVT); NegSrc2 = DAG.getConstant(Value, MemVT);
} else if (Subtarget.hasInterlockedAccess1()) } else if (Subtarget.hasInterlockedAccess1())
// Use LAA(G) if available. // Use LAA(G) if available.
NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT), NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
Src2); Src2);
if (NegSrc2.getNode()) if (NegSrc2.getNode())
@ -2614,23 +2610,23 @@ SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
// Get the address of the containing word. // Get the address of the containing word.
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
DAG.getConstant(-4, DL, PtrVT)); DAG.getConstant(-4, PtrVT));
// Get the number of bits that the word must be rotated left in order // Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32. // to bring the field to the top bits of a GR32.
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr, SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
DAG.getConstant(3, DL, PtrVT)); DAG.getConstant(3, PtrVT));
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
// Get the complementing shift amount, for rotating a field in the top // Get the complementing shift amount, for rotating a field in the top
// bits back to its proper position. // bits back to its proper position.
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
DAG.getConstant(0, DL, WideVT), BitShift); DAG.getConstant(0, WideVT), BitShift);
// Construct the ATOMIC_CMP_SWAPW node. // Construct the ATOMIC_CMP_SWAPW node.
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
NegBitShift, DAG.getConstant(BitSize, DL, WideVT) }; NegBitShift, DAG.getConstant(BitSize, WideVT) };
SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL, SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
VTList, Ops, NarrowVT, MMO); VTList, Ops, NarrowVT, MMO);
return AtomicOp; return AtomicOp;
@ -2659,16 +2655,15 @@ SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
// Just preserve the chain. // Just preserve the chain.
return Op.getOperand(0); return Op.getOperand(0);
SDLoc DL(Op);
bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
auto *Node = cast<MemIntrinsicSDNode>(Op.getNode()); auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
SDValue Ops[] = { SDValue Ops[] = {
Op.getOperand(0), Op.getOperand(0),
DAG.getConstant(Code, DL, MVT::i32), DAG.getConstant(Code, MVT::i32),
Op.getOperand(1) Op.getOperand(1)
}; };
return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL, return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
Node->getVTList(), Ops, Node->getVTList(), Ops,
Node->getMemoryVT(), Node->getMemOperand()); Node->getMemoryVT(), Node->getMemOperand());
} }
@ -2676,11 +2671,10 @@ SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
// Return an i32 that contains the value of CC immediately after After, // Return an i32 that contains the value of CC immediately after After,
// whose final operand must be MVT::Glue. // whose final operand must be MVT::Glue.
static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) { static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
SDLoc DL(After);
SDValue Glue = SDValue(After, After->getNumValues() - 1); SDValue Glue = SDValue(After, After->getNumValues() - 1);
SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32)); DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
} }
SDValue SDValue
@ -2857,10 +2851,9 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
Inner.getOperand(0)); Inner.getOperand(0));
SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext, SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
DAG.getConstant(NewShlAmt, SDLoc(Inner), DAG.getConstant(NewShlAmt, ShiftVT));
ShiftVT));
return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT)); DAG.getConstant(NewSraAmt, ShiftVT));
} }
} }
} }

33
llvm/lib/Target/SystemZ/SystemZOperands.td
View File

@ -134,79 +134,72 @@ class BDLMode<string type, string bitsize, string dispsize, string suffix,
// Bits 0-15 (counting from the lsb). // Bits 0-15 (counting from the lsb).
def LL16 : SDNodeXForm<imm, [{ def LL16 : SDNodeXForm<imm, [{
uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// Bits 16-31 (counting from the lsb). // Bits 16-31 (counting from the lsb).
def LH16 : SDNodeXForm<imm, [{ def LH16 : SDNodeXForm<imm, [{
uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// Bits 32-47 (counting from the lsb). // Bits 32-47 (counting from the lsb).
def HL16 : SDNodeXForm<imm, [{ def HL16 : SDNodeXForm<imm, [{
uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// Bits 48-63 (counting from the lsb). // Bits 48-63 (counting from the lsb).
def HH16 : SDNodeXForm<imm, [{ def HH16 : SDNodeXForm<imm, [{
uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// Low 32 bits. // Low 32 bits.
def LF32 : SDNodeXForm<imm, [{ def LF32 : SDNodeXForm<imm, [{
uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// High 32 bits. // High 32 bits.
def HF32 : SDNodeXForm<imm, [{ def HF32 : SDNodeXForm<imm, [{
uint64_t Value = N->getZExtValue() >> 32; uint64_t Value = N->getZExtValue() >> 32;
return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); return CurDAG->getTargetConstant(Value, MVT::i64);
}]>; }]>;
// Truncate an immediate to a 8-bit signed quantity. // Truncate an immediate to a 8-bit signed quantity.
def SIMM8 : SDNodeXForm<imm, [{ def SIMM8 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Truncate an immediate to a 8-bit unsigned quantity. // Truncate an immediate to a 8-bit unsigned quantity.
def UIMM8 : SDNodeXForm<imm, [{ def UIMM8 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Truncate an immediate to a 16-bit signed quantity. // Truncate an immediate to a 16-bit signed quantity.
def SIMM16 : SDNodeXForm<imm, [{ def SIMM16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Truncate an immediate to a 16-bit unsigned quantity. // Truncate an immediate to a 16-bit unsigned quantity.
def UIMM16 : SDNodeXForm<imm, [{ def UIMM16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Truncate an immediate to a 32-bit signed quantity. // Truncate an immediate to a 32-bit signed quantity.
def SIMM32 : SDNodeXForm<imm, [{ def SIMM32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Truncate an immediate to a 32-bit unsigned quantity. // Truncate an immediate to a 32-bit unsigned quantity.
def UIMM32 : SDNodeXForm<imm, [{ def UIMM32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
// Negate and then truncate an immediate to a 32-bit unsigned quantity. // Negate and then truncate an immediate to a 32-bit unsigned quantity.
def NEGIMM32 : SDNodeXForm<imm, [{ def NEGIMM32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N), return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
MVT::i64);
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

42
llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
View File

@ -46,10 +46,10 @@ static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence,
// number of straight-line MVCs as 6 * 256 - 1. // number of straight-line MVCs as 6 * 256 - 1.
if (Size > 6 * 256) if (Size > 6 * 256)
return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
DAG.getConstant(Size, DL, PtrVT), DAG.getConstant(Size, PtrVT),
DAG.getConstant(Size / 256, DL, PtrVT)); DAG.getConstant(Size / 256, PtrVT));
return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
DAG.getConstant(Size, DL, PtrVT)); DAG.getConstant(Size, PtrVT));
} }
SDValue SystemZSelectionDAGInfo:: SDValue SystemZSelectionDAGInfo::
@ -78,8 +78,7 @@ static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
for (unsigned I = 1; I < Size; ++I) for (unsigned I = 1; I < Size; ++I)
StoreVal |= ByteVal << (I * 8); StoreVal |= ByteVal << (I * 8);
return DAG.getStore(Chain, DL, return DAG.getStore(Chain, DL,
DAG.getConstant(StoreVal, DL, DAG.getConstant(StoreVal, MVT::getIntegerVT(Size * 8)),
MVT::getIntegerVT(Size * 8)),
Dst, DstPtrInfo, false, false, Align); Dst, DstPtrInfo, false, false, Align);
} }
@ -113,7 +112,7 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
if (Size2 == 0) if (Size2 == 0)
return Chain1; return Chain1;
Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
DAG.getConstant(Size1, DL, PtrVT)); DAG.getConstant(Size1, PtrVT));
DstPtrInfo = DstPtrInfo.getWithOffset(Size1); DstPtrInfo = DstPtrInfo.getWithOffset(Size1);
SDValue Chain2 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2, SDValue Chain2 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2,
std::min(Align, Size1), DstPtrInfo); std::min(Align, Size1), DstPtrInfo);
@ -127,7 +126,7 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
if (Bytes == 1) if (Bytes == 1)
return Chain1; return Chain1;
SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
DAG.getConstant(1, DL, PtrVT)); DAG.getConstant(1, PtrVT));
SDValue Chain2 = DAG.getStore(Chain, DL, Byte, Dst2, SDValue Chain2 = DAG.getStore(Chain, DL, Byte, Dst2,
DstPtrInfo.getWithOffset(1), DstPtrInfo.getWithOffset(1),
false, false, 1); false, false, 1);
@ -147,7 +146,7 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
Chain = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo, Chain = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo,
false, false, Align); false, false, Align);
SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
DAG.getConstant(1, DL, PtrVT)); DAG.getConstant(1, PtrVT));
return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
Chain, DstPlus1, Dst, Bytes - 1); Chain, DstPlus1, Dst, Bytes - 1);
} }
@ -170,10 +169,10 @@ static SDValue emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
// needs 2 branches, whereas a straight-line sequence would need 3 or more. // needs 2 branches, whereas a straight-line sequence would need 3 or more.
if (Size > 3 * 256) if (Size > 3 * 256)
return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
DAG.getConstant(Size, DL, PtrVT), DAG.getConstant(Size, PtrVT),
DAG.getConstant(Size / 256, DL, PtrVT)); DAG.getConstant(Size / 256, PtrVT));
return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
DAG.getConstant(Size, DL, PtrVT)); DAG.getConstant(Size, PtrVT));
} }
// Convert the current CC value into an integer that is 0 if CC == 0, // Convert the current CC value into an integer that is 0 if CC == 0,
@ -183,9 +182,9 @@ static SDValue emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
static SDValue addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) { static SDValue addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) {
SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue); SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32)); DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
DAG.getConstant(31, DL, MVT::i32)); DAG.getConstant(31, MVT::i32));
return ROTL; return ROTL;
} }
@ -214,7 +213,7 @@ EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
Length = DAG.getZExtOrTrunc(Length, DL, PtrVT); Length = DAG.getZExtOrTrunc(Length, DL, PtrVT);
Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32); Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32);
Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
DAG.getConstant(255, DL, MVT::i32)); DAG.getConstant(255, MVT::i32));
SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length); SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain, SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
Limit, Src, Char); Limit, Src, Char);
@ -223,10 +222,9 @@ EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
// Now select between End and null, depending on whether the character // Now select between End and null, depending on whether the character
// was found. // was found.
SDValue Ops[] = {End, DAG.getConstant(0, DL, PtrVT), SDValue Ops[] = {End, DAG.getConstant(0, PtrVT),
DAG.getConstant(SystemZ::CCMASK_SRST, DL, MVT::i32), DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32),
DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, DL, MVT::i32), DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32), Glue};
Glue};
VTs = DAG.getVTList(PtrVT, MVT::Glue); VTs = DAG.getVTList(PtrVT, MVT::Glue);
End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops); End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
return std::make_pair(End, Chain); return std::make_pair(End, Chain);
@ -239,7 +237,7 @@ EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
MachinePointerInfo SrcPtrInfo, bool isStpcpy) const { MachinePointerInfo SrcPtrInfo, bool isStpcpy) const {
SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other); SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other);
SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src, SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
return std::make_pair(isStpcpy ? EndDest : Dest, EndDest.getValue(1)); return std::make_pair(isStpcpy ? EndDest : Dest, EndDest.getValue(1));
} }
@ -250,7 +248,7 @@ EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
MachinePointerInfo Op2PtrInfo) const { MachinePointerInfo Op2PtrInfo) const {
SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue); SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue);
SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2,
DAG.getConstant(0, DL, MVT::i32)); DAG.getConstant(0, MVT::i32));
Chain = Unused.getValue(1); Chain = Unused.getValue(1);
SDValue Glue = Chain.getValue(2); SDValue Glue = Chain.getValue(2);
return std::make_pair(addIPMSequence(DL, Glue, DAG), Chain); return std::make_pair(addIPMSequence(DL, Glue, DAG), Chain);
@ -267,7 +265,7 @@ static std::pair<SDValue, SDValue> getBoundedStrlen(SelectionDAG &DAG, SDLoc DL,
EVT PtrVT = Src.getValueType(); EVT PtrVT = Src.getValueType();
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other, MVT::Glue); SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other, MVT::Glue);
SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain, SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
Limit, Src, DAG.getConstant(0, DL, MVT::i32)); Limit, Src, DAG.getConstant(0, MVT::i32));
Chain = End.getValue(1); Chain = End.getValue(1);
SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src); SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
return std::make_pair(Len, Chain); return std::make_pair(Len, Chain);
@ -277,7 +275,7 @@ std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::
EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
SDValue Src, MachinePointerInfo SrcPtrInfo) const { SDValue Src, MachinePointerInfo SrcPtrInfo) const {
EVT PtrVT = Src.getValueType(); EVT PtrVT = Src.getValueType();
return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, DL, PtrVT)); return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, PtrVT));
} }
std::pair<SDValue, SDValue> SystemZSelectionDAGInfo:: std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::

96
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -233,15 +233,14 @@ namespace {
void EmitSpecialCodeForMain(); void EmitSpecialCodeForMain();
inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL, inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
SDValue &Base, SDValue &Scale, SDValue &Scale, SDValue &Index,
SDValue &Index, SDValue &Disp, SDValue &Disp, SDValue &Segment) {
SDValue &Segment) {
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
TLI->getPointerTy()) TLI->getPointerTy())
: AM.Base_Reg; : AM.Base_Reg;
Scale = getI8Imm(AM.Scale, DL); Scale = getI8Imm(AM.Scale);
Index = AM.IndexReg; Index = AM.IndexReg;
// These are 32-bit even in 64-bit mode since RIP relative offset // These are 32-bit even in 64-bit mode since RIP relative offset
// is 32-bit. // is 32-bit.
@ -262,7 +261,7 @@ namespace {
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp, Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
AM.SymbolFlags); AM.SymbolFlags);
else else
Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32); Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
if (AM.Segment.getNode()) if (AM.Segment.getNode())
Segment = AM.Segment; Segment = AM.Segment;
@ -272,14 +271,14 @@ namespace {
/// getI8Imm - Return a target constant with the specified value, of type /// getI8Imm - Return a target constant with the specified value, of type
/// i8. /// i8.
inline SDValue getI8Imm(unsigned Imm, SDLoc DL) { inline SDValue getI8Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, DL, MVT::i8); return CurDAG->getTargetConstant(Imm, MVT::i8);
} }
/// getI32Imm - Return a target constant with the specified value, of type /// getI32Imm - Return a target constant with the specified value, of type
/// i32. /// i32.
inline SDValue getI32Imm(unsigned Imm, SDLoc DL) { inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, DL, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
/// getGlobalBaseReg - Return an SDNode that returns the value of /// getGlobalBaseReg - Return an SDNode that returns the value of
@ -802,11 +801,11 @@ static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
MVT VT = N.getSimpleValueType(); MVT VT = N.getSimpleValueType();
SDLoc DL(N); SDLoc DL(N);
SDValue Eight = DAG.getConstant(8, DL, MVT::i8); SDValue Eight = DAG.getConstant(8, MVT::i8);
SDValue NewMask = DAG.getConstant(0xff, DL, VT); SDValue NewMask = DAG.getConstant(0xff, VT);
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8); SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
// Insert the new nodes into the topological ordering. We must do this in // Insert the new nodes into the topological ordering. We must do this in
@ -850,7 +849,7 @@ static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
MVT VT = N.getSimpleValueType(); MVT VT = N.getSimpleValueType();
SDLoc DL(N); SDLoc DL(N);
SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask); SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
@ -956,9 +955,9 @@ static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
X = NewX; X = NewX;
} }
SDLoc DL(N); SDLoc DL(N);
SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8); SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
// Insert the new nodes into the topological ordering. We must do this in // Insert the new nodes into the topological ordering. We must do this in
@ -1199,7 +1198,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
} }
// Ok, the transformation is legal and appears profitable. Go for it. // Ok, the transformation is legal and appears profitable. Go for it.
SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType()); SDValue Zero = CurDAG->getConstant(0, N.getValueType());
SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
AM.IndexReg = Neg; AM.IndexReg = Neg;
AM.Scale = 1; AM.Scale = 1;
@ -1358,7 +1357,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
if (!AM.IndexReg.getNode()) if (!AM.IndexReg.getNode())
AM.IndexReg = CurDAG->getRegister(0, VT); AM.IndexReg = CurDAG->getRegister(0, VT);
getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment); getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
return true; return true;
} }
@ -1414,7 +1413,7 @@ bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
if ((uint32_t)ImmVal != (uint64_t)ImmVal) if ((uint32_t)ImmVal != (uint64_t)ImmVal)
return false; return false;
Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64); Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
return true; return true;
} }
@ -1450,9 +1449,9 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
// Base could already be %rip, particularly in the x32 ABI. // Base could already be %rip, particularly in the x32 ABI.
Base = SDValue(CurDAG->getMachineNode( Base = SDValue(CurDAG->getMachineNode(
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
CurDAG->getTargetConstant(0, DL, MVT::i64), CurDAG->getTargetConstant(0, MVT::i64),
Base, Base,
CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)), CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
0); 0);
} }
@ -1464,10 +1463,9 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
"Expect to be extending 32-bit registers for use in LEA"); "Expect to be extending 32-bit registers for use in LEA");
Index = SDValue(CurDAG->getMachineNode( Index = SDValue(CurDAG->getMachineNode(
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
CurDAG->getTargetConstant(0, DL, MVT::i64), CurDAG->getTargetConstant(0, MVT::i64),
Index, Index,
CurDAG->getTargetConstant(X86::sub_32bit, DL, CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
MVT::i32)),
0); 0);
} }
@ -1533,7 +1531,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
if (Complexity <= 2) if (Complexity <= 2)
return false; return false;
getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment); getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
return true; return true;
} }
@ -1557,7 +1555,7 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
AM.IndexReg = CurDAG->getRegister(0, MVT::i64); AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
} }
getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment); getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
return true; return true;
} }
@ -1727,7 +1725,7 @@ static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
// an immediate operand to sub. However, it still fits in 32 bits for the // an immediate operand to sub. However, it still fits in 32 bits for the
// add (since it is not negated) so we can return target-constant. // add (since it is not negated) so we can return target-constant.
if (CNVal == INT32_MIN) if (CNVal == INT32_MIN)
return CurDAG->getTargetConstant(CNVal, dl, NVT); return CurDAG->getTargetConstant(CNVal, NVT);
// For atomic-load-add, we could do some optimizations. // For atomic-load-add, we could do some optimizations.
if (Op == ADD) { if (Op == ADD) {
// Translate to INC/DEC if ADD by 1 or -1. // Translate to INC/DEC if ADD by 1 or -1.
@ -1742,7 +1740,7 @@ static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
CNVal = -CNVal; CNVal = -CNVal;
} }
} }
return CurDAG->getTargetConstant(CNVal, dl, NVT); return CurDAG->getTargetConstant(CNVal, NVT);
} }
// If the value operand is single-used, try to optimize it. // If the value operand is single-used, try to optimize it.
@ -2055,14 +2053,12 @@ SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(), SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
MVT::Other); MVT::Other);
SDLoc DL(Node);
// Memory Operands: Base, Scale, Index, Disp, Segment // Memory Operands: Base, Scale, Index, Disp, Segment
SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32); SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
SDValue Segment = CurDAG->getRegister(0, MVT::i32); SDValue Segment = CurDAG->getRegister(0, MVT::i32);
const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx, const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
Disp, Segment, VMask, Chain}; Disp, Segment, VMask, Chain};
SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops); SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
// Node has 2 outputs: VDst and MVT::Other. // Node has 2 outputs: VDst and MVT::Other.
// ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other. // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
// We replace VDst of Node with VDst of ResNode, and Other of Node with Other // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
@ -2236,13 +2232,13 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
} }
// Emit the smaller op and the shift. // Emit the smaller op and the shift.
SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT); SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst); SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
if (ShlVal == 1) if (ShlVal == 1)
return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0), return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
SDValue(New, 0)); SDValue(New, 0));
return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0), return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
getI8Imm(ShlVal, dl)); getI8Imm(ShlVal));
} }
case X86ISD::UMUL8: case X86ISD::UMUL8:
case X86ISD::SMUL8: { case X86ISD::SMUL8: {
@ -2406,8 +2402,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
// Shift AX down 8 bits. // Shift AX down 8 bits.
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
Result, Result,
CurDAG->getTargetConstant(8, dl, MVT::i8)), CurDAG->getTargetConstant(8, MVT::i8)), 0);
0);
// Then truncate it down to i8. // Then truncate it down to i8.
ReplaceUses(SDValue(Node, 1), ReplaceUses(SDValue(Node, 1),
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
@ -2527,8 +2522,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
ClrNode = ClrNode =
SDValue(CurDAG->getMachineNode( SDValue(CurDAG->getMachineNode(
TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode, TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
CurDAG->getTargetConstant(X86::sub_16bit, dl, CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
MVT::i32)),
0); 0);
break; break;
case MVT::i32: case MVT::i32:
@ -2537,9 +2531,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
ClrNode = ClrNode =
SDValue(CurDAG->getMachineNode( SDValue(CurDAG->getMachineNode(
TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode, CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
CurDAG->getTargetConstant(X86::sub_32bit, dl, CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
MVT::i32)),
0); 0);
break; break;
default: default:
@ -2591,9 +2584,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
Result = Result =
SDValue(CurDAG->getMachineNode( SDValue(CurDAG->getMachineNode(
TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
CurDAG->getTargetConstant(0, dl, MVT::i64), Result, CurDAG->getTargetConstant(0, MVT::i64), Result,
CurDAG->getTargetConstant(X86::sub_32bit, dl, CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
MVT::i32)),
0); 0);
} }
} else { } else {
@ -2650,7 +2642,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 && if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
(!(C->getZExtValue() & 0x80) || (!(C->getZExtValue() & 0x80) ||
HasNoSignedComparisonUses(Node))) { HasNoSignedComparisonUses(Node))) {
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8); SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
SDValue Reg = N0.getNode()->getOperand(0); SDValue Reg = N0.getNode()->getOperand(0);
// On x86-32, only the ABCD registers have 8-bit subregisters. // On x86-32, only the ABCD registers have 8-bit subregisters.
@ -2661,7 +2653,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
default: llvm_unreachable("Unsupported TEST operand type!"); default: llvm_unreachable("Unsupported TEST operand type!");
} }
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
Reg.getValueType(), Reg, RC), 0); Reg.getValueType(), Reg, RC), 0);
} }
@ -2686,7 +2678,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
HasNoSignedComparisonUses(Node))) { HasNoSignedComparisonUses(Node))) {
// Shift the immediate right by 8 bits. // Shift the immediate right by 8 bits.
SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8, SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
dl, MVT::i8); MVT::i8);
SDValue Reg = N0.getNode()->getOperand(0); SDValue Reg = N0.getNode()->getOperand(0);
// Put the value in an ABCD register. // Put the value in an ABCD register.
@ -2697,7 +2689,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
default: llvm_unreachable("Unsupported TEST operand type!"); default: llvm_unreachable("Unsupported TEST operand type!");
} }
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
Reg.getValueType(), Reg, RC), 0); Reg.getValueType(), Reg, RC), 0);
@ -2722,8 +2714,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
N0.getValueType() != MVT::i16 && N0.getValueType() != MVT::i16 &&
(!(C->getZExtValue() & 0x8000) || (!(C->getZExtValue() & 0x8000) ||
HasNoSignedComparisonUses(Node))) { HasNoSignedComparisonUses(Node))) {
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
MVT::i16);
SDValue Reg = N0.getNode()->getOperand(0); SDValue Reg = N0.getNode()->getOperand(0);
// Extract the 16-bit subregister. // Extract the 16-bit subregister.
@ -2745,8 +2736,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
N0.getValueType() == MVT::i64 && N0.getValueType() == MVT::i64 &&
(!(C->getZExtValue() & 0x80000000) || (!(C->getZExtValue() & 0x80000000) ||
HasNoSignedComparisonUses(Node))) { HasNoSignedComparisonUses(Node))) {
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
MVT::i32);
SDValue Reg = N0.getNode()->getOperand(0); SDValue Reg = N0.getNode()->getOperand(0);
// Extract the 32-bit subregister. // Extract the 32-bit subregister.

974
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

4
llvm/lib/Target/X86/X86InstrCompiler.td
View File

@ -17,12 +17,12 @@
def GetLo32XForm : SDNodeXForm<imm, [{ def GetLo32XForm : SDNodeXForm<imm, [{
// Transformation function: get the low 32 bits. // Transformation function: get the low 32 bits.
return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N)); return getI32Imm((unsigned)N->getZExtValue());
}]>; }]>;
def GetLo8XForm : SDNodeXForm<imm, [{ def GetLo8XForm : SDNodeXForm<imm, [{
// Transformation function: get the low 8 bits. // Transformation function: get the low 8 bits.
return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); return getI8Imm((uint8_t)N->getZExtValue());
}]>; }]>;

12
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
View File

@ -566,7 +566,7 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{
def I8Imm : SDNodeXForm<imm, [{ def I8Imm : SDNodeXForm<imm, [{
// Transformation function: get the low 8 bits. // Transformation function: get the low 8 bits.
return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); return getI8Imm((uint8_t)N->getZExtValue());
}]>; }]>;
def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>; def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
@ -577,31 +577,31 @@ def FROUND_CURRENT : ImmLeaf<i32, [{
// BYTE_imm - Transform bit immediates into byte immediates. // BYTE_imm - Transform bit immediates into byte immediates.
def BYTE_imm : SDNodeXForm<imm, [{ def BYTE_imm : SDNodeXForm<imm, [{
// Transformation function: imm >> 3 // Transformation function: imm >> 3
return getI32Imm(N->getZExtValue() >> 3, SDLoc(N)); return getI32Imm(N->getZExtValue() >> 3);
}]>; }]>;
// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
// to VEXTRACTF128/VEXTRACTI128 imm. // to VEXTRACTF128/VEXTRACTI128 imm.
def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N)); return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
}]>; }]>;
// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
// VINSERTF128/VINSERTI128 imm. // VINSERTF128/VINSERTI128 imm.
def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N)); return getI8Imm(X86::getInsertVINSERT128Immediate(N));
}]>; }]>;
// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
// to VEXTRACTF64x4 imm. // to VEXTRACTF64x4 imm.
def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N)); return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
}]>; }]>;
// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
// VINSERTF64x4 imm. // VINSERTF64x4 imm.
def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N)); return getI8Imm(X86::getInsertVINSERT256Immediate(N));
}]>; }]>;
def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),

2
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -2223,7 +2223,7 @@ let Predicates = [HasBMI2], Defs = [EFLAGS] in {
def CountTrailingOnes : SDNodeXForm<imm, [{ def CountTrailingOnes : SDNodeXForm<imm, [{
// Count the trailing ones in the immediate. // Count the trailing ones in the immediate.
return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); return getI8Imm(countTrailingOnes(N->getZExtValue()));
}]>; }]>;
def BZHIMask : ImmLeaf<i64, [{ def BZHIMask : ImmLeaf<i64, [{

4
llvm/lib/Target/X86/X86InstrShiftRotate.td
View File

@ -850,12 +850,12 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
def ROT32L2R_imm8 : SDNodeXForm<imm, [{ def ROT32L2R_imm8 : SDNodeXForm<imm, [{
// Convert a ROTL shamt to a ROTR shamt on 32-bit integer. // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
return getI8Imm(32 - N->getZExtValue(), SDLoc(N)); return getI8Imm(32 - N->getZExtValue());
}]>; }]>;
def ROT64L2R_imm8 : SDNodeXForm<imm, [{ def ROT64L2R_imm8 : SDNodeXForm<imm, [{
// Convert a ROTL shamt to a ROTR shamt on 64-bit integer. // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
return getI8Imm(64 - N->getZExtValue(), SDLoc(N)); return getI8Imm(64 - N->getZExtValue());
}]>; }]>;
multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> { multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {

25
llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
View File

@ -138,22 +138,22 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
default: // Byte aligned default: // Byte aligned
AVT = MVT::i8; AVT = MVT::i8;
ValReg = X86::AL; ValReg = X86::AL;
Count = DAG.getIntPtrConstant(SizeVal, dl); Count = DAG.getIntPtrConstant(SizeVal);
break; break;
} }
if (AVT.bitsGT(MVT::i8)) { if (AVT.bitsGT(MVT::i8)) {
unsigned UBytes = AVT.getSizeInBits() / 8; unsigned UBytes = AVT.getSizeInBits() / 8;
Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); Count = DAG.getIntPtrConstant(SizeVal / UBytes);
BytesLeft = SizeVal % UBytes; BytesLeft = SizeVal % UBytes;
} }
Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
InFlag); InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
} else { } else {
AVT = MVT::i8; AVT = MVT::i8;
Count = DAG.getIntPtrConstant(SizeVal, dl); Count = DAG.getIntPtrConstant(SizeVal);
Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
} }
@ -174,8 +174,7 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
Count = Size; Count = Size;
EVT CVT = Count.getValueType(); EVT CVT = Count.getValueType();
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
DAG.getConstant((AVT == MVT::i64) ? 7 : 3, dl, DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
CVT));
Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
X86::ECX, X86::ECX,
Left, InFlag); Left, InFlag);
@ -191,9 +190,9 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
Chain = DAG.getMemset(Chain, dl, Chain = DAG.getMemset(Chain, dl,
DAG.getNode(ISD::ADD, dl, AddrVT, Dst, DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
DAG.getConstant(Offset, dl, AddrVT)), DAG.getConstant(Offset, AddrVT)),
Src, Src,
DAG.getConstant(BytesLeft, dl, SizeVT), DAG.getConstant(BytesLeft, SizeVT),
Align, isVolatile, false, Align, isVolatile, false,
DstPtrInfo.getWithOffset(Offset)); DstPtrInfo.getWithOffset(Offset));
} }
@ -249,7 +248,7 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
unsigned UBytes = AVT.getSizeInBits() / 8; unsigned UBytes = AVT.getSizeInBits() / 8;
unsigned CountVal = SizeVal / UBytes; unsigned CountVal = SizeVal / UBytes;
SDValue Count = DAG.getIntPtrConstant(CountVal, dl); SDValue Count = DAG.getIntPtrConstant(CountVal);
unsigned BytesLeft = SizeVal % UBytes; unsigned BytesLeft = SizeVal % UBytes;
SDValue InFlag; SDValue InFlag;
@ -280,12 +279,10 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
EVT SizeVT = Size.getValueType(); EVT SizeVT = Size.getValueType();
Results.push_back(DAG.getMemcpy(Chain, dl, Results.push_back(DAG.getMemcpy(Chain, dl,
DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getNode(ISD::ADD, dl, DstVT, Dst,
DAG.getConstant(Offset, dl, DAG.getConstant(Offset, DstVT)),
DstVT)),
DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getNode(ISD::ADD, dl, SrcVT, Src,
DAG.getConstant(Offset, dl, DAG.getConstant(Offset, SrcVT)),
SrcVT)), DAG.getConstant(BytesLeft, SizeVT),
DAG.getConstant(BytesLeft, dl, SizeVT),
Align, isVolatile, AlwaysInline, false, Align, isVolatile, AlwaysInline, false,
DstPtrInfo.getWithOffset(Offset), DstPtrInfo.getWithOffset(Offset),
SrcPtrInfo.getWithOffset(Offset))); SrcPtrInfo.getWithOffset(Offset)));

13
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -47,8 +47,8 @@ namespace {
/// getI32Imm - Return a target constant with the specified value, of type /// getI32Imm - Return a target constant with the specified value, of type
/// i32. /// i32.
inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { inline SDValue getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32); return CurDAG->getTargetConstant(Imm, MVT::i32);
} }
inline bool immMskBitp(SDNode *inN) const { inline bool immMskBitp(SDNode *inN) const {
@ -90,7 +90,7 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
FrameIndexSDNode *FIN = nullptr; FrameIndexSDNode *FIN = nullptr;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true; return true;
} }
if (Addr.getOpcode() == ISD::ADD) { if (Addr.getOpcode() == ISD::ADD) {
@ -100,8 +100,7 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
// Constant positive word offset from frame index // Constant positive word offset from frame index
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
MVT::i32);
return true; return true;
} }
} }
@ -139,7 +138,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
if (immMskBitp(N)) { if (immMskBitp(N)) {
// Transformation function: get the size of a mask // Transformation function: get the size of a mask
// Look for the first non-zero bit // Look for the first non-zero bit
SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl); SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val));
return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
MVT::i32, MskSize); MVT::i32, MskSize);
} }
@ -257,7 +256,7 @@ SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
// after with clrsr 1. If any resources owned by the thread are ready an event // after with clrsr 1. If any resources owned by the thread are ready an event
// will be taken. If no resource is ready we branch to the address which was // will be taken. If no resource is ready we branch to the address which was
// the operand to the checkevent intrinsic. // the operand to the checkevent intrinsic.
SDValue constOne = getI32Imm(1, dl); SDValue constOne = getI32Imm(1);
SDValue Glue = SDValue Glue =
SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
constOne, Chain), 0); constOne, Chain), 0);

115
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -298,7 +298,7 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
GA = getGlobalAddressWrapper(GA, GV, DAG); GA = getGlobalAddressWrapper(GA, GV, DAG);
// Handle the rest of the offset. // Handle the rest of the offset.
if (Offset != FoldedOffset) { if (Offset != FoldedOffset) {
SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32); SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32);
GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
} }
return GA; return GA;
@ -368,7 +368,7 @@ LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
} }
assert((NumEntries >> 31) == 0); assert((NumEntries >> 31) == 0);
SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
DAG.getConstant(1, dl, MVT::i32)); DAG.getConstant(1, MVT::i32));
return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
ScaledIndex); ScaledIndex);
} }
@ -393,12 +393,12 @@ lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base,
HighOffset); HighOffset);
} else { } else {
LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
DAG.getConstant(LowOffset, DL, MVT::i32)); DAG.getConstant(LowOffset, MVT::i32));
HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
DAG.getConstant(HighOffset, DL, MVT::i32)); DAG.getConstant(HighOffset, MVT::i32));
} }
SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32); SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);
SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32); SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32);
SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
LowAddr, MachinePointerInfo(), LowAddr, MachinePointerInfo(),
@ -469,14 +469,14 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LD->isVolatile(), LD->isNonTemporal(), LD->isVolatile(), LD->isNonTemporal(),
LD->isInvariant(), 2); LD->isInvariant(), 2);
SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
HighAddr, HighAddr,
LD->getPointerInfo().getWithOffset(2), LD->getPointerInfo().getWithOffset(2),
MVT::i16, LD->isVolatile(), MVT::i16, LD->isVolatile(),
LD->isNonTemporal(), LD->isInvariant(), 2); LD->isNonTemporal(), LD->isInvariant(), 2);
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
DAG.getConstant(16, DL, MVT::i32)); DAG.getConstant(16, MVT::i32));
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
High.getValue(1)); High.getValue(1));
@ -529,13 +529,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) const
if (ST->getAlignment() == 2) { if (ST->getAlignment() == 2) {
SDValue Low = Value; SDValue Low = Value;
SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
DAG.getConstant(16, dl, MVT::i32)); DAG.getConstant(16, MVT::i32));
SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
ST->getPointerInfo(), MVT::i16, ST->getPointerInfo(), MVT::i16,
ST->isVolatile(), ST->isNonTemporal(), ST->isVolatile(), ST->isNonTemporal(),
2); 2);
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
DAG.getConstant(2, dl, MVT::i32)); DAG.getConstant(2, MVT::i32));
SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
ST->getPointerInfo().getWithOffset(2), ST->getPointerInfo().getWithOffset(2),
MVT::i16, ST->isVolatile(), MVT::i16, ST->isVolatile(),
@ -573,7 +573,7 @@ LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
SDLoc dl(Op); SDLoc dl(Op);
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant(0, dl, MVT::i32); SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
LHS, RHS); LHS, RHS);
@ -590,7 +590,7 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
SDLoc dl(Op); SDLoc dl(Op);
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant(0, dl, MVT::i32); SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
Zero, Zero); Zero, Zero);
@ -675,13 +675,13 @@ TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
SDLoc dl(N); SDLoc dl(N);
SDValue LL, RL, AddendL, AddendH; SDValue LL, RL, AddendL, AddendH;
LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32)); Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Other, DAG.getConstant(0, dl, MVT::i32)); Other, DAG.getConstant(0, MVT::i32));
AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Other, DAG.getConstant(1, dl, MVT::i32)); Other, DAG.getConstant(1, MVT::i32));
APInt HighMask = APInt::getHighBitsSet(64, 32); APInt HighMask = APInt::getHighBitsSet(64, 32);
unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
@ -704,9 +704,9 @@ TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
} }
SDValue LH, RH; SDValue LH, RH;
LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32)); Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32)); Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
DAG.getVTList(MVT::i32, MVT::i32), AddendH, DAG.getVTList(MVT::i32, MVT::i32), AddendH,
AddendL, LL, RL); AddendL, LL, RL);
@ -735,22 +735,18 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
// Extract components // Extract components
SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
N->getOperand(0), N->getOperand(0), DAG.getConstant(0, MVT::i32));
DAG.getConstant(0, dl, MVT::i32));
SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
N->getOperand(0), N->getOperand(0), DAG.getConstant(1, MVT::i32));
DAG.getConstant(1, dl, MVT::i32));
SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
N->getOperand(1), N->getOperand(1), DAG.getConstant(0, MVT::i32));
DAG.getConstant(0, dl, MVT::i32));
SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
N->getOperand(1), N->getOperand(1), DAG.getConstant(1, MVT::i32));
DAG.getConstant(1, dl, MVT::i32));
// Expand // Expand
unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
XCoreISD::LSUB; XCoreISD::LSUB;
SDValue Zero = DAG.getConstant(0, dl, MVT::i32); SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSL, RHSL, Zero); LHSL, RHSL, Zero);
SDValue Carry(Lo.getNode(), 1); SDValue Carry(Lo.getNode(), 1);
@ -779,8 +775,7 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG) const
false, false, false, 0); false, false, false, 0);
// Increment the pointer, VAList, to the next vararg // Increment the pointer, VAList, to the next vararg
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList, SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
DAG.getIntPtrConstant(VT.getSizeInBits() / 8, DAG.getIntPtrConstant(VT.getSizeInBits() / 8));
dl));
// Store the incremented VAList to the legalized pointer // Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr, InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
MachinePointerInfo(SV), false, false, 0); MachinePointerInfo(SV), false, false, 0);
@ -915,30 +910,30 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
SDValue Addr = Trmp; SDValue Addr = Trmp;
SDLoc dl(Op); SDLoc dl(Op);
OutChains[0] = DAG.getStore(Chain, dl, OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr, Addr, MachinePointerInfo(TrmpAddr), false, false,
MachinePointerInfo(TrmpAddr), false, false, 0); 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(4, dl, MVT::i32)); DAG.getConstant(4, MVT::i32));
OutChains[1] = DAG.getStore(Chain, dl, OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr, Addr, MachinePointerInfo(TrmpAddr, 4), false,
MachinePointerInfo(TrmpAddr, 4), false, false, 0); false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(8, dl, MVT::i32)); DAG.getConstant(8, MVT::i32));
OutChains[2] = DAG.getStore(Chain, dl, OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr, Addr, MachinePointerInfo(TrmpAddr, 8), false,
MachinePointerInfo(TrmpAddr, 8), false, false, 0); false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(12, dl, MVT::i32)); DAG.getConstant(12, MVT::i32));
OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
MachinePointerInfo(TrmpAddr, 12), false, false, MachinePointerInfo(TrmpAddr, 12), false, false,
0); 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(16, dl, MVT::i32)); DAG.getConstant(16, MVT::i32));
OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
MachinePointerInfo(TrmpAddr, 16), false, false, MachinePointerInfo(TrmpAddr, 16), false, false,
0); 0);
@ -1101,7 +1096,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag,
int offset = ResultMemLocs[i].first; int offset = ResultMemLocs[i].first;
unsigned index = ResultMemLocs[i].second; unsigned index = ResultMemLocs[i].second;
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) }; SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops); SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
InVals[index] = load; InVals[index] = load;
MemOpChains.push_back(load.getValue(1)); MemOpChains.push_back(load.getValue(1));
@ -1150,7 +1145,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
// Get a count of how many bytes are to be pushed on the stack. // Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = RetCCInfo.getNextStackOffset(); unsigned NumBytes = RetCCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, dl, Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy(), true), dl); getPointerTy(), true), dl);
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
@ -1187,8 +1182,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
Chain, Arg, Chain, Arg,
DAG.getConstant(Offset/4, dl, DAG.getConstant(Offset/4, MVT::i32)));
MVT::i32)));
} }
} }
@ -1239,9 +1233,8 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
// Create the CALLSEQ_END node. // Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, Chain = DAG.getCALLSEQ_END(Chain,
DAG.getConstant(NumBytes, dl, getPointerTy(), DAG.getConstant(NumBytes, getPointerTy(), true),
true), DAG.getConstant(0, getPointerTy(), true),
DAG.getConstant(0, dl, getPointerTy(), true),
InFlag, dl); InFlag, dl);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -1429,7 +1422,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(FIN); InVals.push_back(FIN);
MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
DAG.getConstant(Size, dl, MVT::i32), DAG.getConstant(Size, MVT::i32),
Align, false, false, false, Align, false, false, false,
MachinePointerInfo(), MachinePointerInfo(),
MachinePointerInfo())); MachinePointerInfo()));
@ -1494,7 +1487,7 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
SmallVector<SDValue, 4> RetOps(1, Chain); SmallVector<SDValue, 4> RetOps(1, Chain);
// Return on XCore is always a "retsp 0" // Return on XCore is always a "retsp 0"
RetOps.push_back(DAG.getConstant(0, dl, MVT::i32)); RetOps.push_back(DAG.getConstant(0, MVT::i32));
SmallVector<SDValue, 4> MemOpChains; SmallVector<SDValue, 4> MemOpChains;
// Handle return values that must be copied to memory. // Handle return values that must be copied to memory.
@ -1678,9 +1671,9 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
// fold (ladd 0, 0, x) -> 0, x & 1 // fold (ladd 0, 0, x) -> 0, x & 1
if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
SDValue Carry = DAG.getConstant(0, dl, VT); SDValue Carry = DAG.getConstant(0, VT);
SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
DAG.getConstant(1, dl, VT)); DAG.getConstant(1, VT));
SDValue Ops[] = { Result, Carry }; SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
} }
@ -1693,7 +1686,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
VT.getSizeInBits() - 1); VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne); DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Carry = DAG.getConstant(0, dl, VT); SDValue Carry = DAG.getConstant(0, VT);
SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
SDValue Ops[] = { Result, Carry }; SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
@ -1718,7 +1711,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Borrow = N2; SDValue Borrow = N2;
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
DAG.getConstant(0, dl, VT), N2); DAG.getConstant(0, VT), N2);
SDValue Ops[] = { Result, Borrow }; SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
} }
@ -1732,7 +1725,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
VT.getSizeInBits() - 1); VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne); DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Borrow = DAG.getConstant(0, dl, VT); SDValue Borrow = DAG.getConstant(0, VT);
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
SDValue Ops[] = { Result, Borrow }; SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
@ -1798,13 +1791,13 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
DAG.MaskedValueIsZero(Addend0, HighMask) && DAG.MaskedValueIsZero(Addend0, HighMask) &&
DAG.MaskedValueIsZero(Addend1, HighMask)) { DAG.MaskedValueIsZero(Addend1, HighMask)) {
SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul0, DAG.getConstant(0, dl, MVT::i32)); Mul0, DAG.getConstant(0, MVT::i32));
SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Mul1, DAG.getConstant(0, dl, MVT::i32)); Mul1, DAG.getConstant(0, MVT::i32));
SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Addend0, DAG.getConstant(0, dl, MVT::i32)); Addend0, DAG.getConstant(0, MVT::i32));
SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Addend1, DAG.getConstant(0, dl, MVT::i32)); Addend1, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
Addend0L, Addend1L); Addend0L, Addend1L);
@ -1844,7 +1837,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
bool isTail = isInTailCallPosition(DAG, ST, Chain); bool isTail = isInTailCallPosition(DAG, ST, Chain);
return DAG.getMemmove(Chain, dl, ST->getBasePtr(), return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
LD->getBasePtr(), LD->getBasePtr(),
DAG.getConstant(StoreBits/8, dl, MVT::i32), DAG.getConstant(StoreBits/8, MVT::i32),
Alignment, false, isTail, ST->getPointerInfo(), Alignment, false, isTail, ST->getPointerInfo(),
LD->getPointerInfo()); LD->getPointerInfo());
} }

11
llvm/lib/Target/XCore/XCoreInstrInfo.td
View File

@ -94,34 +94,33 @@ def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER,
def div4_xform : SDNodeXForm<imm, [{ def div4_xform : SDNodeXForm<imm, [{
// Transformation function: imm/4 // Transformation function: imm/4
assert(N->getZExtValue() % 4 == 0); assert(N->getZExtValue() % 4 == 0);
return getI32Imm(N->getZExtValue()/4, SDLoc(N)); return getI32Imm(N->getZExtValue()/4);
}]>; }]>;
def msksize_xform : SDNodeXForm<imm, [{ def msksize_xform : SDNodeXForm<imm, [{
// Transformation function: get the size of a mask // Transformation function: get the size of a mask
assert(isMask_32(N->getZExtValue())); assert(isMask_32(N->getZExtValue()));
// look for the first non-zero bit // look for the first non-zero bit
return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()), return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));
SDLoc(N));
}]>; }]>;
def neg_xform : SDNodeXForm<imm, [{ def neg_xform : SDNodeXForm<imm, [{
// Transformation function: -imm // Transformation function: -imm
uint32_t value = N->getZExtValue(); uint32_t value = N->getZExtValue();
return getI32Imm(-value, SDLoc(N)); return getI32Imm(-value);
}]>; }]>;
def bpwsub_xform : SDNodeXForm<imm, [{ def bpwsub_xform : SDNodeXForm<imm, [{
// Transformation function: 32-imm // Transformation function: 32-imm
uint32_t value = N->getZExtValue(); uint32_t value = N->getZExtValue();
return getI32Imm(32 - value, SDLoc(N)); return getI32Imm(32-value);
}]>; }]>;
def div4neg_xform : SDNodeXForm<imm, [{ def div4neg_xform : SDNodeXForm<imm, [{
// Transformation function: -imm/4 // Transformation function: -imm/4
uint32_t value = N->getZExtValue(); uint32_t value = N->getZExtValue();
assert(-value % 4 == 0); assert(-value % 4 == 0);
return getI32Imm(-value/4, SDLoc(N)); return getI32Imm(-value/4);
}]>; }]>;
def immUs4Neg : PatLeaf<(imm), [{ def immUs4Neg : PatLeaf<(imm), [{

37
llvm/test/DebugInfo/AArch64/constant-dbgloc.ll
View File

@ -1,37 +0,0 @@
; RUN: llc -filetype=asm %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "aarch64--linux-gnueabihf"
; int
; main(void)
; {
; return -1;
; }
; CHECK: test.c:4:5
; CHECK: movn
; Function Attrs: nounwind
define i32 @main() {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval
ret i32 -1, !dbg !11
}
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!8, !9}
!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")
!2 = !{}
!3 = !{!4}
!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
!5 = !MDSubroutineType(types: !6)
!6 = !{!7}
!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!8 = !{i32 2, !"Dwarf Version", i32 4}
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !{i32 1, !"wchar_size", i32 4}
!11 = !MDLocation(line: 4, column: 5, scope: !4)

37
llvm/test/DebugInfo/ARM/constant-dbgloc.ll
View File

@ -1,37 +0,0 @@
; RUN: llc -filetype=asm %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7--linux-gnueabihf"
; int
; main(void)
; {
; return -1;
; }
; CHECK: test.c:4:5
; CHECK: mvn
; Function Attrs: nounwind
define i32 @main() {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval
ret i32 -1, !dbg !11
}
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!8, !9}
!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")
!2 = !{}
!3 = !{!4}
!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
!5 = !MDSubroutineType(types: !6)
!6 = !{!7}
!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!8 = !{i32 2, !"Dwarf Version", i32 4}
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !{i32 1, !"wchar_size", i32 4}
!11 = !MDLocation(line: 4, column: 5, scope: !4)

25
llvm/test/DebugInfo/constant-sdnodes-have-dbg-location.ll
View File

@ -1,25 +0,0 @@
; RUN: llc -debug < %s 2>&1 | FileCheck %s
; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<-1>test.c:4:5
define i32 @main() {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval
ret i32 -1, !dbg !10
}
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!8, !9}
!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)
!1 = !MDFile(filename: "test.c", directory: "/home/user/clang-llvm/build")
!2 = !{}
!3 = !{!4}
!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)
!5 = !MDSubroutineType(types: !6)
!6 = !{!7}
!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!8 = !{i32 2, !"Dwarf Version", i32 4}
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !MDLocation(line: 4, column: 5, scope: !4)