maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[LVI][CVP] Add support for abs/nabs select pattern flavor 

Based on ConstantRange support added in D61084, we can now handle
abs and nabs select pattern flavors in LVI.

Differential Revision: https://reviews.llvm.org/D61794

llvm-svn: 360700
This commit is contained in:
Nikita Popov 2019-05-14 18:53:47 +00:00
parent 0333dd9563
commit 48c4e4fa80
2 changed files with 26 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
llvm/lib/Analysis/LazyValueInfo.cpp
View File

@ -893,7 +893,28 @@ bool LazyValueInfoImpl::solveBlockValueSelect(ValueLatticeElement &BBLV,
return true;
}
// TODO: ABS, NABS from the SelectPatternResult
if (SPR.Flavor == SPF_ABS) {
if (LHS == SI->getTrueValue()) {
BBLV = ValueLatticeElement::getRange(TrueCR.abs());
return true;
}
if (LHS == SI->getFalseValue()) {
BBLV = ValueLatticeElement::getRange(FalseCR.abs());
return true;
}
}
if (SPR.Flavor == SPF_NABS) {
ConstantRange Zero(APInt::getNullValue(TrueCR.getBitWidth()));
if (LHS == SI->getTrueValue()) {
BBLV = ValueLatticeElement::getRange(Zero.sub(TrueCR.abs()));
return true;
}
if (LHS == SI->getFalseValue()) {
BBLV = ValueLatticeElement::getRange(Zero.sub(FalseCR.abs()));
return true;
}
}
}
// Can we constrain the facts about the true and false values by using the

12
llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
View File

@ -633,8 +633,7 @@ define void @abs1(i32 %a, i1* %p) {
; CHECK-NEXT: store i1 true, i1* [[P:%.*]]
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[ABS]], 19
; CHECK-NEXT: store i1 [[C2]], i1* [[P]]
; CHECK-NEXT: [[C3:%.*]] = icmp sge i32 [[ABS]], 0
; CHECK-NEXT: store i1 [[C3]], i1* [[P]]
; CHECK-NEXT: store i1 true, i1* [[P]]
; CHECK-NEXT: [[C4:%.*]] = icmp sge i32 [[ABS]], 1
; CHECK-NEXT: store i1 [[C4]], i1* [[P]]
; CHECK-NEXT: br label [[EXIT]]
@ -684,8 +683,7 @@ define void @abs2(i32 %a, i1* %p) {
; CHECK-NEXT: store i1 true, i1* [[P:%.*]]
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[ABS]], 19
; CHECK-NEXT: store i1 [[C2]], i1* [[P]]
; CHECK-NEXT: [[C3:%.*]] = icmp sge i32 [[ABS]], 0
; CHECK-NEXT: store i1 [[C3]], i1* [[P]]
; CHECK-NEXT: store i1 true, i1* [[P]]
; CHECK-NEXT: [[C4:%.*]] = icmp sge i32 [[ABS]], 1
; CHECK-NEXT: store i1 [[C4]], i1* [[P]]
; CHECK-NEXT: br label [[EXIT]]
@ -735,8 +733,7 @@ define void @nabs1(i32 %a, i1* %p) {
; CHECK-NEXT: store i1 true, i1* [[P:%.*]]
; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[NABS]], -19
; CHECK-NEXT: store i1 [[C2]], i1* [[P]]
; CHECK-NEXT: [[C3:%.*]] = icmp sle i32 [[NABS]], 0
; CHECK-NEXT: store i1 [[C3]], i1* [[P]]
; CHECK-NEXT: store i1 true, i1* [[P]]
; CHECK-NEXT: [[C4:%.*]] = icmp sle i32 [[NABS]], -1
; CHECK-NEXT: store i1 [[C4]], i1* [[P]]
; CHECK-NEXT: br label [[EXIT]]
@ -786,8 +783,7 @@ define void @nabs2(i32 %a, i1* %p) {
; CHECK-NEXT: store i1 true, i1* [[P:%.*]]
; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[NABS]], -19
; CHECK-NEXT: store i1 [[C2]], i1* [[P]]
; CHECK-NEXT: [[C3:%.*]] = icmp sle i32 [[NABS]], 0
; CHECK-NEXT: store i1 [[C3]], i1* [[P]]
; CHECK-NEXT: store i1 true, i1* [[P]]
; CHECK-NEXT: [[C4:%.*]] = icmp sle i32 [[NABS]], -1
; CHECK-NEXT: store i1 [[C4]], i1* [[P]]
; CHECK-NEXT: br label [[EXIT]]