forked from OSchip/llvm-project
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset
Add a test for a bug (uncovered by D88808) fixed by f34bb06935.
Also delete cmpxchg16b.ll which is covered by atomic128.ll
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D89163
This commit is contained in:
Fangrui Song
parent
278299b0f0
commit
488f1c4893
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@ -80,6 +80,43 @@ define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
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ret i128 %val
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}
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@cmpxchg16b_global = external dso_local global { i128, i128 }, align 16
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;; Make sure we retain the offset of the global variable.
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define void @cmpxchg16b_global_with_offset() nounwind {
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; CHECK-LABEL: cmpxchg16b_global_with_offset:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: lock cmpxchg16b _cmpxchg16b_global+{{.*}}(%rip)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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;
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; CHECK32-LABEL: cmpxchg16b_global_with_offset:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: subl $36, %esp
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; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $0
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; CHECK32-NEXT: pushl $cmpxchg16b_global+16
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; CHECK32-NEXT: pushl %eax
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; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
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; CHECK32-NEXT: addl $72, %esp
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; CHECK32-NEXT: retl
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entry:
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%0 = load atomic i128, i128* getelementptr inbounds ({i128, i128}, {i128, i128}* @cmpxchg16b_global, i64 0, i32 1) acquire, align 16
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ret void
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}
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define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK: ## %bb.0:
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@ -90,7 +127,7 @@ define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB1_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB2_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: andq %r8, %rcx
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@ -99,7 +136,7 @@ define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-NEXT: notq %rbx
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; CHECK-NEXT: notq %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB1_1
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; CHECK-NEXT: jne LBB2_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -160,14 +197,14 @@ define void @fetch_and_or(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB2_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB3_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: orq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: orq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB2_1
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; CHECK-NEXT: jne LBB3_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -228,14 +265,14 @@ define void @fetch_and_add(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB3_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB4_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: addq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: adcq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB3_1
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; CHECK-NEXT: jne LBB4_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -296,14 +333,14 @@ define void @fetch_and_sub(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB4_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB5_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: subq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: sbbq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB4_1
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; CHECK-NEXT: jne LBB5_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -364,7 +401,7 @@ define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB5_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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@ -374,7 +411,7 @@ define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovgeq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB5_1
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; CHECK-NEXT: jne LBB6_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -435,7 +472,7 @@ define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB7_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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@ -445,7 +482,7 @@ define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovlq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB6_1
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; CHECK-NEXT: jne LBB7_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -506,7 +543,7 @@ define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB7_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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@ -516,7 +553,7 @@ define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovaeq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB7_1
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; CHECK-NEXT: jne LBB8_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -577,7 +614,7 @@ define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB9_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: movq %r8, %rcx
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@ -587,7 +624,7 @@ define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: cmovbq %rax, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB8_1
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; CHECK-NEXT: jne LBB9_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: movq %rax, {{.*}}(%rip)
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; CHECK-NEXT: movq %rdx, _var+{{.*}}(%rip)
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@ -793,10 +830,10 @@ define void @atomic_store_seq_cst(i128* %p, i128 %in) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB11_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB11_1
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; CHECK-NEXT: jne LBB12_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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@ -838,10 +875,10 @@ define void @atomic_store_release(i128* %p, i128 %in) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB12_1
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; CHECK-NEXT: jne LBB13_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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@ -883,10 +920,10 @@ define void @atomic_store_relaxed(i128* %p, i128 %in) {
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 8(%rdi), %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
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; CHECK-NEXT: LBB14_1: ## %atomicrmw.start
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne LBB13_1
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; CHECK-NEXT: jne LBB14_1
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; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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@ -1,21 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
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; Basic 128-bit cmpxchg
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define void @t1(i128* nocapture %p) nounwind ssp {
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; CHECK-LABEL: t1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: movl $1, %ebx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
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ret void
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}
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; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic
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