forked from OSchip/llvm-project
AMDGPU/GlobalISel: Use live in helper function for returnaddress
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@ -1094,8 +1094,6 @@ bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
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!RBI.constrainGenericRegister(DstReg, *RC, *MRI))
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!RBI.constrainGenericRegister(DstReg, *RC, *MRI))
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return false;
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return false;
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MachineBasicBlock &EntryMBB = MF.front();
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// Check for kernel and shader functions
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// Check for kernel and shader functions
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if (Depth != 0 ||
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if (Depth != 0 ||
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MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction()) {
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MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction()) {
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@ -1105,22 +1103,14 @@ bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
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return true;
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return true;
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}
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}
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Register ReturnAddrReg = TRI.getReturnAddressReg(MF);
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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// There is a call to @llvm.returnaddress in this function
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// There is a call to @llvm.returnaddress in this function
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MFI.setReturnAddressIsTaken(true);
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MFI.setReturnAddressIsTaken(true);
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// Get the return address reg and mark it as an implicit live-in
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// Get the return address reg and mark it as an implicit live-in
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Register LiveIn = MRI->getLiveInVirtReg(ReturnAddrReg);
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Register ReturnAddrReg = TRI.getReturnAddressReg(MF);
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if (!LiveIn) {
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Register LiveIn = getFunctionLiveInPhysReg(MF, TII, ReturnAddrReg,
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LiveIn = MF.addLiveIn(ReturnAddrReg, RC);
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AMDGPU::SReg_64RegClass);
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BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(AMDGPU::COPY), LiveIn)
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.addReg(ReturnAddrReg);
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if (!EntryMBB.isLiveIn(ReturnAddrReg))
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EntryMBB.addLiveIn(ReturnAddrReg);
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}
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BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
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BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
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.addReg(LiveIn);
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.addReg(LiveIn);
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I.eraseFromParent();
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I.eraseFromParent();
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