forked from OSchip/llvm-project
[RegisterBankInfo] Implement the verify method of the InstructionMapping helper class.
This checks that all the register operands get a proper mapping. llvm-svn: 265563
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@ -89,7 +89,7 @@ public:
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public:
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/// Constructor for the mapping of an instruction.
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/// \p NumOperands should be equal to number of all the operands of
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/// \p NumOperands must be equal to number of all the operands of
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/// the related instruction.
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/// The rationale is that it is more efficient for the optimizers
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/// to be able to assume that the mapping of the ith operand is
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@ -14,6 +14,9 @@
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -231,4 +234,26 @@ void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
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void RegisterBankInfo::InstructionMapping::verify(
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const MachineInstr &MI) const {
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// Check that all the register operands are properly mapped.
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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// Check the constructor invariant.
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assert(NumOperands == MI.getNumOperands() &&
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"NumOperands must match, see constructor");
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for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
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const MachineOperand &MO = MI.getOperand(Idx);
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const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
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if (!MO.isReg()) {
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assert(MOMapping.BreakDown.empty() &&
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"We should not care about non-reg mapping");
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continue;
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}
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unsigned Reg = MO.getReg();
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// Register size in bits.
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// This size must match what the mapping expect.
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unsigned RegSize = MRI.getSize(Reg);
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// If Reg is not a generic register, query the register class to
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// get its size.
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if (!RegSize)
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RegSize = MRI.getRegClass(Reg)->getSize() * 8;
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MOMapping.verify(RegSize);
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}
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}
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